阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 内田慎一 中柴康隆 桑原慎一 于 2021-05-21 设计创作，主要内容包括：本公开涉及一种半导体器件。该半导体器件包括：第一基板；形成在第一基板上的多层布线层；第一电感器,在平面图中,该第一电感器被形成为多层布线层上的曲折形状；以及第二电感器,在平面图中,该第二电感器被形成为多层布线层上的曲折形状,并且被布置为在平面图中与第一电感器靠近且与第一电感器不重叠。变压器由第一电感器和第二电感器来构造；并且在平面图中,第一电感器和第二电感器沿着第一方向延伸,第一基板的一侧在该第一方向上延伸。(The present disclosure relates to a semiconductor device. The semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed in a meandering shape on the multilayer wiring layer in a plan view; and a second inductor formed in a meandering shape on the multilayer wiring layer in a plan view, and arranged close to and not overlapping with the first inductor in a plan view. The transformer is constructed by a first inductor and a second inductor; and the first and second inductors extend along a first direction in a plan view, the first direction being a direction in which one side of the first substrate extends.)

1. A semiconductor device, comprising:

a first substrate;

a plurality of wiring layers formed on the first substrate;

a first inductor formed in a meandering shape on the multilayer wiring layer in a plan view; and

a second inductor formed in a meandering shape on the multilayer wiring layer in a plan view and arranged close to and not overlapping with the first inductor in a plan view,

wherein a transformer is constructed from the first inductor and the second inductor; and

in a plan view, the first and second inductors extend along a first direction, and one side of the first substrate extends in the first direction.

2. The semiconductor device according to claim 1, wherein respective wirings configuring the first inductor and the second inductor are extended in the first direction while being bent alternately at 90 degrees and 270 degrees in a plan view.

3. The semiconductor device according to claim 1, wherein respective wirings configuring the first inductor and the second inductor extend in the first direction while being alternately bent into a semicircular shape in a plan view.

4. The semiconductor device according to claim 1, wherein in a plan view, respective wirings configuring the first inductor and the second inductor are extended in the first direction while being bent twice at 90 degrees and bent twice at 270 degrees alternately.

5. The semiconductor device according to claim 1, wherein the first inductor and the second inductor are formed in mutually different wiring layers.

6. The semiconductor device according to claim 5, wherein in a plan view, respective wirings configuring the first inductor and the second inductor are extended in the first direction while being bent twice at 90 degrees and bent twice at 270 degrees alternately.

7. The semiconductor device of claim 1, further comprising:

the first substrate;

a transistor;

an element separator of the transistor; and

a separation portion configured such that an insulator is embedded in a groove deeper than a groove of the element separation member,

wherein the width of the separation portion is configured to become larger than a width of: a wiring configuring the first inductor and a wiring configuring the second inductor.

8. The semiconductor device according to claim 7, wherein in a plan view, respective wirings configuring the first inductor and the second inductor are extended in the first direction while being bent twice at 90 degrees and bent twice at 270 degrees alternately.

9. The semiconductor device of claim 1, further comprising:

a first circuit connected to the first inductor and formed on the first substrate,

wherein the first inductor is disposed closer to the first circuit than the second inductor.

10. The semiconductor device according to claim 9, wherein the first inductor and the second inductor are arranged close to the one side of the first substrate, and the second inductor is arranged closer to the one side than the first inductor in a plan view.

11. The semiconductor device of claim 10, further comprising:

a second substrate;

a second plate formed on the second substrate; and

a wiring connecting the second inductor and the second circuit on the first substrate.

12. The semiconductor device of claim 11, further comprising a bond pad formed on the first substrate,

wherein the second inductor is connected to the bonding pad, an

The wiring is a bonding wire connected to the bonding pad.

13. The semiconductor device as set forth in claim 9,

wherein the first circuit is a transmit circuit and includes a transmit side driver circuit connected to the first inductor.

14. The semiconductor device of claim 13, wherein the first inductor has: one end connected to the transmission side driver circuit; and the other end connected to the power supply wiring or the ground wiring.

15. The semiconductor device according to claim 9, wherein the first inductor and the second inductor are formed in mutually different wiring layers.

Technical Field

The present disclosure relates to a semiconductor device, and is applicable to, for example, a semiconductor device having an inductor.

Background

When an electrical signal is transmitted between two circuits, which are different from each other in potential, of the electrical signal to be input, a photocoupler is often used as an opto-isolator. The photocoupler has a light emitting element (such as a light emitting diode) and a light receiving element (such as a phototransistor), converts an input electric signal into light by a light transmitting element, and returns the light to the electric signal by the light receiving element, thereby transmitting the electric signal.

However, since the photocoupler has a light emitting element and a light receiving element, it is difficult to miniaturize. In addition, when the frequency of the electric signal is high, the photocoupler cannot follow the electric signal. As a technique for solving these problems, a technique for transmitting an electrical signal through a transformer that inductively couples two inductors has been developed. An isolator is constructed by using the transformer. For example, patent document 1 (japanese patent application laid-open No. 2010-219122) is disclosed.

Disclosure of Invention

When an electric signal is transmitted by inductively coupling two inductors provided in a semiconductor device, the size of the semiconductor device may become large by providing the two inductors.

In one aspect of the disclosure, the two inductors are each shaped in a meander to form a transformer. In addition, the isolator is constructed by using a transformer.

According to the above semiconductor device, the increase in size thereof can be reduced.

Drawings

Fig. 1 is a plan view of a semiconductor device according to an embodiment.

Fig. 2 is a cross-sectional view of the semiconductor device shown in fig. 1.

Fig. 3 is a cross-sectional view for explaining the method of manufacturing the semiconductor device shown in fig. 1.

Fig. 4 is a cross-sectional view for explaining a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 5 is a cross-sectional view for explaining a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 6 is a cross-sectional view for explaining the method of manufacturing the semiconductor device shown in fig. 1.

Fig. 7 is a cross-sectional view for explaining the method of manufacturing the semiconductor device shown in fig. 1.

Fig. 8 is a cross-sectional view for explaining the method of manufacturing the semiconductor device shown in fig. 1.

Fig. 9 is a cross-sectional view for explaining the method of manufacturing the semiconductor device shown in fig. 1.

Fig. 10 is a cross-sectional view for explaining a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 11 is a cross-sectional view for explaining a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 12 is a cross-sectional view for explaining a method of manufacturing the semiconductor device shown in fig. 1.

Fig. 13 is a plan view of the two inductors shown in fig. 1.

Fig. 14 is a plan view of the inductor in the first modified example.

Fig. 15 is a plan view of an inductor in the second modified example.

Fig. 16 is a graph showing respective inductance values of the inductors in the embodiment and the second modified example.

Fig. 17 is a graph showing a Q value of each of the inductors in the embodiment and the second modified example.

Fig. 18 is a plan view of an inductor in the third modified example.

Fig. 19 is a plan view of an inductor in a fourth modified example.

Detailed Description

Hereinafter, embodiments and modified examples will be described with reference to the accompanying drawings. However, in the following description, the same components may be denoted by the same reference numerals, and repeated descriptions thereof may be omitted. Incidentally, for clarity of the description, the drawings may schematically show the width, thickness, shape, and the like of each portion compared to the actual embodiment, but this is merely an example, and the schematic representations are not intended to limit the explanation of the present disclosure.

Fig. 1 is a schematic plan view of a semiconductor device according to an embodiment. Fig. 2 is a cross-sectional view showing the configuration of the semiconductor device shown in fig. 1.

As shown in fig. 1, the semiconductor device 1 has a first semiconductor chip 10 and a second semiconductor chip 20, and the semiconductor device 1 is configured with an isolator. In a plan view, the first side 10a extending in the Y-axis direction of the first semiconductor chip 10 is arranged close to and opposite to the first side 20a extending in the Y-axis direction of the second semiconductor chip 20. The first semiconductor chip 10 includes a first circuit 100, a first inductor 310, and a second inductor 320. The second semiconductor chip 20 has a second circuit 200.

In plan view, the first inductor 310 and the second inductor 320 are close to the first side 10a and extend along the first side 10 a. At least a part of the first circuit 100 is located at a second side 10b facing the first side 10a with respect to the first inductor 310 and the second inductor 320.

The first inductor 310 and the second inductor 320 configure the transformer 300 as a signal transmission element and transmit electrical signals to each other through mutual inductive coupling. The electrical signal is, for example, a digital signal, but may be an analog signal.

The first inductor 310 is connected to the first circuit 100, and the second inductor 320 is connected to the second semiconductor chip 20. The first circuit 100 is a transmission circuit. That is, the first inductor 310 serves as a transmission-side inductor, and the second inductor 320 serves as a reception-side inductor. The wirings connecting the second inductor 320 and the second semiconductor chip 20 are, for example, bonding wires 521 and 522. The second circuit 200 includes a receiving circuit and is connected to the second inductor 320 via bonding wires 521 and 522.

The first circuit 100 includes: a modulation processing unit 155 that modulates the digital signal into a signal for transmission; and a transmission side driver circuit 150 outputting the modulated signal to the first inductor 310. The second circuit 200 includes: a receiving circuit 260 connected to the second inductor 320; and a receive driver circuit 250 (e.g., a gate driver). The receiving circuit 260 demodulates the modulated signal into a digital signal. The digital signal demodulated by the reception circuit 260 is output to the reception driver circuit 250.

In the first circuit 100 and the second circuit 200, the potentials of the input electrical signals are different from each other, but since the first inductor 310 and the second inductor 320 transmit and receive the electrical signals by using the inductive coupling, problems with the first circuit 100 and the second circuit 200 do not occur. That is, the first inductor 310 and the second inductor 320 constitute a transformer. Incidentally, the case of "the potentials of the inputted electric signals are different from each other" in the configuration of fig. 1 is, for example, as follows:

(a) a case where the amplitudes of the electric signals (the difference between the potential indicating 0 and the potential indicating 1) are different from each other;

(b) a case where the reference potential (potential indicating 0) of the electric signal is different; and

(c) the amplitudes of the electric signals are different from each other and the reference potentials of the electric signals are different.

As shown in fig. 2, the first circuit 100 of the first semiconductor chip 10 is formed on the first substrate 102. Here, the first substrate 102 is a semiconductor substrate such as a silicon substrate. The multilayer wiring layer 400 is formed on the first substrate 102. The first inductor 310 is formed on the multilayer wiring layer 400. The second inductor 320 is formed in the multilayer wiring layer 400, and as shown in fig. 1, the second inductor 320 does not overlap with the first inductor 310 in a plan view.

The first circuit 100 of the first semiconductor chip 10 has a first transistor. The first transistors include a first transistor 121 of a first conductivity type and a first transistor 141 of a second conductivity type. The first transistor 121 of the first conductivity type is formed in the second conductivity type well 120, and has two impurity regions 124 of the first conductivity type each serving as a source and a drain, and a gate electrode 126. The first transistor 141 of the second conductivity type is formed on the first conductivity type well 140, and has two impurity regions 144 of the second conductivity type each serving as a source and a drain, and a gate electrode 146. A gate insulating film is located under each of the gate electrodes 126 and 146. The thicknesses of the two gate insulating films are substantially equal. The first transistors 121 and 141 configure the above-mentioned transmission-side driver circuit, for example, an inverter.

The second conductive-type impurity region 122 is formed in the well 120, and the first conductive-type impurity region 142 is formed in the well 140. A wiring which supplies a ground potential as a reference potential of the first conductivity type first transistor 121 is connected to the impurity region 122, and a wiring which supplies a reference potential of the second conductivity type first transistor 141 is connected to the impurity region 142.

The second circuit 200 of the second semiconductor chip 20 is formed in the second substrate 202. Here, the second substrate 202 is a semiconductor substrate such as a silicon substrate. The multilayer wiring layer 600 is formed on the second substrate 202.

The second circuit 200 has a second transistor. The second transistors further include a second transistor 221 of the first conductive type and a second transistor 241 of the second conductive type. The second transistor 221 of the first conductivity type is formed in the second conductivity type well 220, and has two impurity regions 224 of the first conductivity type each serving as a source and a drain, and a gate electrode 226. The second transistor 241 of the second conductive type is formed in the first conductive type well 240, and has two impurity regions 244 of the second conductive type and a gate electrode 246 each serving as a source and a drain. A gate insulating film is located under each of the gate electrodes 226 and 246. As described above, the second transistors 221 and 241 configure the reception driver circuit 250 and the reception circuit 260.

The second conductive-type impurity region 222 is formed in the well 220, and the first conductive-type impurity region 242 is formed in the well 240. A wiring which supplies a reference potential of the second transistor 221 of the first conductivity type is connected to the impurity region 222, and a wiring which supplies a reference potential of the second transistor 241 of the second conductivity type is connected to the impurity region 242.

In the example shown in fig. 2, the first transistors 121 and 141 and the second transistors 221 and 241 have gate insulating films different from each other, but may be the same.

The first inductor 310 and the second inductor 320 are wiring patterns having a meandering shape and formed in mutually different wiring layers. The first inductor 310 is located, for example, in the upper wiring layer 442 and the second inductor 320 is located, for example, in the wiring layer 432, the wiring layer 432 being a layer below the uppermost layer.

The multilayer wiring layer 400 is formed by alternately stacking insulating layers and wiring layers t times (t.gtoreq.3) or more times in sequence. The second inductor 320 is disposed in the nth wiring layer of the multilayer wiring layer 400. The first inductor 310 is disposed in an mth wiring layer (t ≧ m ≧ n +1) of the multilayer wiring layers, and is located above the second inductor 320. That is, the first inductor 310 and the second inductor 320 are formed in mutually different wiring layers. Further, the wiring layer located between the nth wiring layer and the mth wiring layer is not provided with an inductor located above the second inductor 320. In the present embodiment, the multilayer wiring layer 400 has the following configuration: the insulating layer 410, the wiring layer 412, the insulating layer 420, the wiring layer 422, the insulating layer 430, the wiring layer 432, the insulating layer 440, and the wiring layer 442 are stacked in this order. Here, the wiring layers 412, 422, 432, and 442 are composed of an insulating film and a conductor film. The insulating layers 410, 420, 430, and 440 may have a structure in which a plurality of insulating films are stacked, or may be a single insulating film.

The wirings located in the wiring layers 412, 422, 432, and 442 are copper (Cu) wirings formed by a damascene method, and are embedded in each trench formed in the insulating layer of the wiring layers 412, 422, 432, and 432. A pad (not shown) is formed on or in the uppermost wiring. Incidentally, at least one of the wiring layers 412, 422, 432, and 442 as described above may be an aluminum alloy wiring. Incidentally, the wirings formed in the wiring layers 412, 422, 432, and 442 are connected to each other via plugs embedded in the insulating layers 410, 420, 430, and 440.

Each of the insulating films configuring the insulating layer and the wiring layer may be silicon dioxide (SiO)₂) A film or a low dielectric constant film. The low dielectric constant film may be provided as, for example, an insulating film having a relative dielectric constant of 3.3 or less (preferably 2.9 or less).

The bonding pads 161 and 162 are located at the first side 10a, the side facing the second semiconductor chip 20 (opposite the second semiconductor chip 20), and the first inductor 310 and the second inductor 320 extend along the first side 10a and between the bonding pads 161 and 162. As described above, the first circuit 100 is located at the second side 10b, opposite to the first inductor 310 and the second inductor 320. The first circuit 100 includes a transmit side driver circuit 150. As described above, the transmission side driver circuit 150 is composed of at least a part (e.g., a part of an inverter) of the first transistors 121 and 141. One end 312 of the first inductor 310 is connected to the transmission side driver circuit 150. Incidentally, the other end 314 of the first inductor 310 is connected to a power supply wiring or a ground wiring.

Next, an outline of a method of manufacturing the first semiconductor chip 10 will be described. First, the first circuit 100 is formed on the first substrate 102. Next, a multilayer wiring layer 400 is formed on the first substrate 102. When the multilayer wiring layer 400 is formed, the first inductor 310 and the second inductor 320 are formed. Further, the first inductor 310 is connected to the first circuit 100 via a wiring provided in the multilayer wiring layer 400.

The first semiconductor chip 10 and the second semiconductor chip 20 will be described in more detail below with reference to fig. 3 to 12. Fig. 3 is a cross-sectional view for explaining a process of forming a DTI. Fig. 4 is a cross-sectional view for explaining a process of forming STI. Fig. 5 is a cross-sectional view for explaining a process of forming a well. Fig. 6 is a cross-sectional view for explaining a process of forming a source and a drain. Fig. 7 is a cross-sectional view for explaining a process of forming a gate electrode. Fig. 8 is a cross-sectional view for explaining a process of forming an insulating layer. Fig. 9 is a cross-sectional view for explaining a process of forming a contact and a first insulating layer. Fig. 10 is a cross-sectional view for explaining a process of forming a wiring of the first layer. Fig. 11 is a cross-sectional view for explaining a process of forming wirings of second to fourth layers. Fig. 12 is a cross-sectional view for explaining a process of forming a protective film.

As shown in fig. 3, a DTI (deep trench isolation) 151 is formed in the first substrate 102, the DTI 151 having a deeper trench than that of the STI (shallow trench isolation) 152 of the first transistors 121 and 141. The width (a) of the DTI 151 is preferably wider than each width (b) of wirings for forming the first inductor 310 and the second inductor 320, which are to be formed in the DTI 151, and more preferably, "a" is wider rightward and leftward by 2 μm to 8 μm with respect to "b". That is, it is preferable that "a" is wider than "b" by 4 μm to 16 μm. Incidentally, no DTI is formed on the second substrate 202.

Next, as shown in fig. 4, an STI 152 for each of the first transistors 121 and 141 is formed in the first substrate 102 or on the first substrate 102. The STI 252 for each of the second transistors 221 and 241 is formed in the second substrate 202 or on the second substrate 202.

Next, as shown in fig. 5, a second conductive type well 120 and a first conductive type well 140 are formed on the first substrate 102 or in the first substrate 102. A second conductive type well 220 and a first conductive type well 240 are formed on the second substrate 202 or in the second substrate 202.

Next, as shown in fig. 6, a first conductive-type impurity region 124 and a second conductive-type impurity region 122 that serve as a source and a drain are formed in the well 120. Impurity regions 144 of the second conductivity type and impurity regions 142 of the first conductivity type, which serve as a source and a drain, are formed in the well 140. Impurity regions 224 of the first conductivity type and impurity regions 222 of the second conductivity type, which serve as a source and a drain, are formed in the well 220. Impurity regions 244 of the second conductivity type and impurity regions 242 of the first conductivity type, which serve as a source and a drain, are formed in the well 240.

Next, as shown in fig. 7, the gate electrodes 126 and 146 are formed by forming a gate insulating film on the first substrate 102 and forming a conductor film on the gate insulating film. The gate electrodes 226 and 246 are formed by forming a gate insulating film on the second substrate 202 and forming a conductor film on the gate insulating film.

Next, as shown in fig. 8, an insulating layer 410 is formed as a wiring interlayer film on the gate electrodes 126 and 146. An insulating layer 610 is formed as a wiring interlayer film on the gate electrodes 226 and 246.

Next, as shown in fig. 9, after a contact hole is formed in the insulating layer 410, a conductor film is formed in the contact hole to form a contact 411. Thereafter, an insulating film 412a is formed over the contact 411 and the insulating layer 410. After forming a contact hole in the insulating layer 610, a conductor film is formed in the contact hole to form a contact 611. Thereafter, an insulating film 612a is formed over the contact 611 and the insulating layer 610.

Next, as shown in fig. 10, a trench is formed in the insulating film 412a, and a conductor film 412b is formed in the trench to form the wiring layer 412. A trench is formed in the insulating film 612a, and a conductor film 612b is formed in the trench to form the wiring layer 612.

Next, as shown in fig. 11, insulating layers 420, 430, and 440 of an oxide film for damascene wiring are stacked, and wiring layers 422, 432, and 442 are formed by damascene. The wiring layers 422, 432, and 442 form the following: wiring for constructing the first inductor 310; wiring for constructing the second inductor 320; and other wirings 422b, 432b, and 442 b. Insulating layers 620, 630, and 640 of oxide films for damascene wiring are stacked, and wiring layers 622, 632, 642 are formed by damascene.

Finally, as shown in fig. 12, a bonding pad (not shown) and a protective film 450 are formed on the wiring layer 442. A bonding pad (not shown) and a protective film 650 are formed on the wiring layer 642.

The shapes of the first inductor 310 and the second inductor 320, which first inductor 310 and second inductor 320 construct the transformer in the embodiment, will be described with reference to fig. 13. Fig. 13 is a plan view showing two inductors in the embodiment.

The wirings configuring the first inductor 310 and the second inductor 320 each have a width of "b" and are arranged (in parallel) at equal intervals in a plan view. Here, the distance between the wirings configuring the first inductor 310 and the second inductor 320 is "c", and "c" is greater than "b". In a plan view, the wiring configuring the first inductor 310 and the second inductor 320 is composed of wiring at 45 degrees or 135 degrees with respect to the Y-axis direction. In addition, the wiring configuring the first inductor 310 and the second inductor 320 is formed as: extending the wiring length while bending at 90 ° and 270 °; alternately arranged at bending angles of 90 ° and 270 ° and extending in the Y-axis direction.

Both ends of the second inductor 320 are electrically connected to the bonding pads 161 and 162, and the first inductor 310 is connected to the transmission side driver circuit 150 as an internal circuit of the first semiconductor chip 10. The modulated signal is transmitted from the transmission side driver circuit 150 to the first inductor 310 and further to the second inductor 320 through inductive coupling. The bonding pads 161 and 162 connected to the second inductor 320 are connected to the bonding pads 261 and 262 of the second semiconductor chip 20 via bonding wires 521 and 522 and demodulated by the second semiconductor chip 20. For example, when a withstand voltage of 250V is required, the distance between the first inductor 310 and the second inductor 320 is about 2 μm long and 10 μm wide.

Next, the action and effect of the present embodiment will be described. According to the present embodiment, it has one or more of the following.

(1) Since the inductor requires a relatively large area, when the first inductor 310 and the second inductor 320 are disposed on the first semiconductor chip 10 to transmit an electrical signal, the first semiconductor chip 10 is easily made large. In contrast, in the present embodiment, the inductor is formed in a meandering shape. Therefore, the inductance value per unit length is larger than that of the inductor formed by the straight line, and a required inductance value can be obtained without arranging the inductor at the entire periphery of the chip. Therefore, the area from the creepage distance between the inductor and the internal circuit (caused by the creepage distance between the inductor and the internal circuit) can be reduced.

(2) By reducing the number of sides on which the inductor is arranged, the area to be considered for the creepage distance between the chip internal circuit and the inductor becomes small, and the chip area thereof becomes small.

(3) Since there is no region where the wirings are arranged in parallel at 180 °, a transformer can be formed without canceling out the magnetic field generated between the wirings.

< modified example >

Hereinafter, some typical modified examples of the embodiments will be illustrated. In the description of the following modified examples, the same reference numerals as those in the above-described embodiments may be used for portions having the same configurations and functions as those described in the above-described embodiments. With regard to the description of this section, the descriptions in the above embodiments may be appropriately combined within a technically consistent range. In addition, all or part of the above-described embodiments and various modified examples may be appropriately applied in combination within a technically consistent range.

(first modified example)

Shapes of the first inductor 310 and the second inductor 320 configuring the transformer in the first modified example will be described with reference to fig. 14. Fig. 14 is a plan view of two inductors in the first modified example.

The first inductor 310 and the second inductor 320 include a wiring group 301 and a wiring group 302. The wiring group 301 is configured by: a semicircular wiring 3101 formed of a certain radius (r 1); and semicircular wiring 3201 formed with a radius consisting of radius (r1) + wiring width (b) + wiring interval (c). The wiring 3101 and the wiring 3201 are formed to be uniformly separated by a wiring interval (c). The wiring group 302 is configured by: a semicircular wiring 3202 formed of a certain radius (r 2); and a semicircular wiring 3102 formed by a radius consisting of the radius (r2) + the wiring width (b) + the wiring interval (c). The wiring 3102 and the wiring 3202 are formed to be uniformly separated by a wiring interval (c). Here, "c" is larger than "b" as in the embodiment.

The wiring group 301 and the wiring group 302 are symmetrically arranged with respect to a line 303 connecting both ends of the wiring 3101. Here, the line 303 extends in the Y-axis direction. The first inductor 310 and the second inductor 320 are configured by alternately connecting the wiring group 301 and the wiring group 302, and are configured to extend in the Y-axis direction.

In the first modified example, the wiring has no edge portion as compared with the embodiment, and the electric field concentration in the high-frequency signal is smaller than that of the embodiment, so that the series resistance at the high frequency can be reduced.

(second modified example)

Shapes of the first inductor 310 and the second inductor 320 constructing the transformer in the second modified example will be described with reference to fig. 15 to 17. Fig. 15 is a plan view of two inductors in the second modified example. Fig. 16 is a graph showing respective inductance values of the inductors in the embodiment and the second modified example. Fig. 17 is a graph showing respective Q values of inductors in the embodiment and the second modified example.

As shown in fig. 15, the wiring configuring the first inductor 310 and the second inductor 320 is composed of a wiring extending in the X-axis direction and a wiring extending in the Y-axis direction in a plan view. Similarly to the embodiment, two wirings configuring the first inductor 310 and the second inductor 320 are formed as: arranged in parallel at a spacing "c"; bending 90 ° and 270 °; and extends in the Y-axis direction. The bending is performed twice in succession by 90 °, and then the bending is performed twice in succession by 270 °, and the wiring is extended in the Y-axis direction while repeating these steps. When W1 is L1 and S1 is S2, the inductance value per unit area is large. Here, "W1" is the length of the wiring configuring the first inductor 310 and the second inductor 320 in the X-axis direction. "L1" is the respective lengths of the two wires that make up the first inductor 310 and the second inductor 320 in the Y-axis direction. "S1" is the interval between the wirings configuring the second inductor 320 in the Y-axis direction. "S2" is the interval between the wirings configuring the first inductor 310 in the Y-axis direction. S1 is preferably 30 μm or more.

The vertical axis of fig. 16 indicates the inductance value, and the horizontal axis of fig. 16 indicates the wiring density. As shown in fig. 16, in the second modified example, when W1 is L1, the inductance value is almost the same as that of the embodiment. In fig. 16, "a" indicates the inductance value of the embodiment, and "B" indicates the inductance value of the second modified example. In this case, in the second modified example, the coupling coefficient and the resistance value are larger than in the embodiment. The horizontal axis of fig. 17 indicates the Q value, and the vertical axis of fig. 17 indicates the frequency. The Q value is also referred to as the Q factor. As shown in fig. 17, the Q value of the embodiment is larger than that of the second modified example. In fig. 17, "a" indicates a Q value of the embodiment, and "B" indicates a Q value of the second modified example.

(third modified example)

Shapes of the first inductor 310 and the second inductor 320 configuring the transformer in the third modified example will be described with reference to fig. 18. Fig. 18 is a plan view of two inductors in the third modified example.

The wiring configuring the first inductor 310 and the second inductor 320 is composed of: a wiring extending in the X-axis direction; and a wiring extending in a direction of 45 degrees with respect to the Y-axis direction in a plan view. Similar to the embodiment, two wirings configuring the first inductor 310 and the second inductor 320 are arranged at equal intervals. Further, the two wirings configuring the first inductor 310 and the second inductor 320 are formed to be bent at 90 °, 135 °, 225 °, and 270 ° and extended in the Y-axis direction by repeating the bending.

(fourth modified example)

Shapes of the first inductor 310 and the second inductor 320 configuring the transformer in the fourth modified example will be described with reference to fig. 19. Fig. 19 is a plan view of two inductors in the fourth modified example.

Similarly to the embodiment, in a macroscopic region, the wirings configuring the first inductor 310 and the second inductor 320 are composed of wirings at 45 degrees or 135 degrees with respect to the Y-axis direction in a plan view. Further, the wiring configuring the first inductor 310 and the second inductor 320 is formed as: extending the respective wiring lengths while bending at 90 ° and 270 °; alternately arranged at respective bending angles of 90 ° and 270 °; and extends in the Y-axis direction.

On the other hand, in the microscopic region, the wiring configuring the first inductor 310 and the second inductor 320 is not composed of wiring at 45 degrees or 135 degrees with respect to the Y-axis direction in a plan view, but is composed of wiring extending in the X-axis direction and wiring extending in the axial direction. Further, two wirings configuring the first inductor 310 and the second inductor 320 are formed as: bent at 90 ° and 270 °; and extends in a direction of 45 ° with respect to the Y-axis direction by repeating the bending. However, the microscopic region at each folded portion of the wiring in the macroscopic region is continuous at 90 ° or continuous at 270 °, and this results in extension of the wiring. When the folding angle is repeated at 90 ° and 90 °, or 270 ° and 270 °, the wiring length is preferably 30 μm or more.

It is difficult to incorporate an optical isolator in one package using an optical coupler, and the isolator of the present disclosure can be integrated over multiple channels. Therefore, for example, the inverter system can be miniaturized. That is, the system can be miniaturized in applications such as motor control, isolated DC-DC, UPS (uninterruptible power supply), display, and lighting control.

Further, it may be integrated with the IGBT or integrated to the MCU. Integration with the MCU can miniaturize the system in applications such as switching power supplies, medical devices, LED lighting, and vehicle-mounted devices such as body systems and drivelines.

The disclosure made by the present disclosure has been specifically described based on the embodiments and the modified examples. However, the present disclosure is not limited to the above-mentioned embodiments and modified examples, and may be changed or altered in various ways.

For example, an example has been explained in the embodiment in which the first semiconductor chip 10 is provided with a transmission circuit, the first inductor 310, and the second inductor 320, and the second semiconductor chip 20 is provided with a reception circuit. The first semiconductor chip 10 may be provided with a receiving circuit, a first inductor 310 and a second inductor 320, and the second semiconductor chip 20 may be provided with a transmitting circuit. In this case, the second inductor 320 serves as a transmission-side inductor, and the first inductor 310 serves as a reception-side inductor.

Further, in the embodiment, the semiconductor device is formed by dividing the semiconductor device into two semiconductor chips, but the semiconductor device may be formed on one semiconductor chip. In this case, the first substrate 102 is formed of an SOI (silicon on insulator) substrate, and the first circuit 100 and the second circuit 200 are formed on the first substrate 102. The element separation film is embedded in the silicon layer of the first substrate 102. The lower end of the element separation film reaches the insulating layer of the first substrate 102. The element separation film insulates the first circuit 100 and the second circuit 200.