阅读说明：本技术 芯片定位结构、芯片封装结构及形成方法、半导体器件 (Chip positioning structure, chip packaging structure, forming method and semiconductor device ) 是由 杨芳 曹立强 方志丹 丁才华 于 2020-12-31 设计创作，主要内容包括：本发明提供一种芯片定位结构、芯片封装结构及形成方法、半导体器件。芯片定位结构包括两个平行设置的第一芯片定位凸台和两个平行设置的第二芯片定位凸台,两个第一芯片定位凸台的平行线垂直于两个第二芯片定位凸台的平行线。本发明的芯片定位结构,使得埋入芯片的位移影响由“开槽精度”转变为“定位结构形成精度”,定位结构的形成可以通过选择比现有技术的开槽精度更高的工艺实现,如此可实现更小的芯片位移。(The invention provides a chip positioning structure, a chip packaging structure, a forming method and a semiconductor device. The chip positioning structure comprises two first chip positioning bosses arranged in parallel and two second chip positioning bosses arranged in parallel, and parallel lines of the two first chip positioning bosses are perpendicular to parallel lines of the two second chip positioning bosses. The chip positioning structure of the invention enables the displacement influence of the embedded chip to be changed from 'slotting precision' to 'positioning structure forming precision', and the forming of the positioning structure can be realized by selecting a process with higher slotting precision than that of the prior art, so that smaller chip displacement can be realized.)

1. A chip positioning structure is characterized by comprising

The positioning device comprises two first chip positioning bosses arranged in parallel and two second chip positioning bosses arranged in parallel, wherein parallel lines of the first chip positioning bosses are perpendicular to parallel lines of the second chip positioning bosses.

2. The chip positioning structure according to claim 1,

the adjacent first chip positioning lug boss and the second chip positioning lug boss are connected to form a group of corner chip positioning lug bosses, and the two groups of corner chip positioning lug bosses are arranged diagonally.

3. The chip positioning structure according to claim 2,

in each group of corner chip positioning bosses, a gap exists between the first chip positioning boss and the second chip positioning boss.

4. The chip positioning structure according to any one of claims 1 to 3,

the chip positioning structure is a metal structure;

preferably, the height of the first chip positioning boss is 5-8 μm, and the height of the second chip positioning boss is 5-8 μm.

5. A chip package structure, comprising:

the chip positioning structure of any one of claims 1-4;

the chip embedded base layer is arranged on the surface of one side of the chip embedded base layer; the chip positioning structure defines a chip embedding region;

and the embedded chip is attached to a chip embedding area of the chip embedding base layer, and the side part of the embedded chip is attached and limited by the positioning structure.

6. The chip package structure of claim 5,

the height of the first chip positioning boss and the height of the second chip positioning boss are less than or equal to half of the height of the embedded chip;

preferably, the chip embedding base layer is a metal structure.

7. A method for forming a chip packaging structure is characterized by comprising the following steps:

two first chip positioning bosses arranged in parallel and two second chip positioning bosses arranged in parallel are formed, and parallel lines of the two first chip positioning bosses are perpendicular to parallel lines of the two second chip positioning bosses.

8. The method for forming the chip packaging structure according to claim 7, further comprising the steps of:

forming a chip positioning structure protruding from the surface of a chip embedded base layer on the surface of the chip embedded base layer, wherein the chip positioning structure defines a chip embedded region, and the size of the chip embedded region is suitable for embedding the embedded chip;

and mounting an embedded chip on the surface of the chip embedding base layer of the chip embedding area, wherein the side part of the embedded chip is attached and limited by the positioning structure.

9. The method as claimed in claim 8, wherein the step of forming the chip positioning structure protruding from the surface of the chip embedding base layer on the surface of the chip embedding base layer comprises:

photoetching the chip embedded base layer to form a chip positioning structure preset position pattern, and then electroplating the chip positioning structure preset position pattern to form the chip positioning structure;

preferably, in the step of forming the chip positioning structure preset position pattern, the formed chip positioning structure preset position pattern includes two first chip positioning boss preset position patterns arranged in parallel and two second chip positioning boss preset position patterns arranged in parallel, and a parallel line of the two first chip positioning boss preset position patterns is perpendicular to a parallel line of the two second chip positioning boss preset position patterns;

preferably, the adjacent preset position patterns of the first chip positioning boss and the second chip positioning boss form a group of preset position patterns of corner chip positioning bosses, and the two groups of preset position patterns of the corner chip positioning bosses form diagonal arrangement.

10. A semiconductor device comprising the chip packaging structure according to claim 5 or 6.

Technical Field

The invention relates to the technical field of chip manufacturing, in particular to a chip positioning structure, a chip packaging structure, a forming method and a semiconductor device.

Background

As a means for downsizing and improving the performance of an electronic device, embedding a chip in a substrate and connecting the chip to another device through a wiring is a technical means for effectively reducing the size of the entire device. After a chip with high-density, small-size and narrow-pitch surface bonding pads is embedded into a substrate, if large displacement of tens of microns to tens of microns occurs horizontally, the position of an opening of a dielectric layer is inaccurate when the bonding pads are butted, and interconnection failure is caused. The positioning accuracy of the chip embedding is an important factor influencing the displacement of the chip.

In the chip embedding in the prior art, generally, a groove is formed in a preset embedded dielectric layer, and the groove is formed by etching the dielectric layer or laser grooving of the dielectric layer; after which the chip is buried. And the displacement of the chip is affected by the slotting precision.

Disclosure of Invention

Therefore, the invention provides a chip positioning structure, a chip packaging structure and a forming method, which are used for reducing chip displacement in the chip embedding process in the prior art.

The invention provides a chip positioning structure which comprises two first chip positioning bosses arranged in parallel and two second chip positioning bosses arranged in parallel, wherein parallel lines of the two first chip positioning bosses are perpendicular to parallel lines of the two second chip positioning bosses.

Optionally, the adjacent first chip positioning boss and the second chip positioning boss are connected to form a group of corner chip positioning bosses, and the two groups of corner chip positioning bosses are arranged diagonally.

Optionally, in each group of corner chip positioning bosses, a gap exists between the first chip positioning boss and the second chip positioning boss.

Optionally, the chip positioning structure is a metal structure;

optionally, the height of the first chip positioning boss is 5 μm to 8 μm, and the height of the second chip positioning boss is 5 μm to 8 μm.

The invention provides a chip packaging structure, comprising: the chip positioning structure as described above. The chip embedded base layer is arranged on the surface of one side of the chip embedded base layer; the chip positioning structure defines a chip embedding region; and the embedded chip is attached to a chip embedding area of the chip embedding base layer, and the side part of the embedded chip is attached and limited by the positioning structure.

Optionally, the height of the first chip positioning boss and the height of the second chip positioning boss are less than or equal to half of the height of the embedded chip.

Optionally, the chip embedding base layer is of a metal structure.

The invention also provides a forming method of the chip packaging structure, which comprises the following steps: two first chip positioning bosses arranged in parallel and two second chip positioning bosses arranged in parallel are formed, and parallel lines of the two first chip positioning bosses are perpendicular to parallel lines of the two second chip positioning bosses.

Optionally, the method further comprises the following steps: forming a chip positioning structure protruding from the surface of a chip embedded base layer on the surface of the chip embedded base layer, wherein the chip positioning structure defines a chip embedded region, and the size of the chip embedded region is suitable for embedding the embedded chip; and mounting an embedded chip on the surface of the chip embedding base layer of the chip embedding area, wherein the side part of the embedded chip is attached and limited by the positioning structure.

Optionally, the step of forming the chip positioning structure protruding from the surface of the chip-embedded base layer on the surface of the chip-embedded base layer includes: and photoetching the chip embedded base layer to form a chip positioning structure preset position pattern, and then electroplating the chip positioning structure at the chip positioning structure preset position pattern to form the chip positioning structure.

Optionally, in the step of forming the chip positioning structure preset position pattern, the formed chip positioning structure preset position pattern includes two first chip positioning boss preset position patterns arranged in parallel and two second chip positioning boss preset position patterns arranged in parallel, and parallel lines of the first chip positioning boss preset position patterns are perpendicular to parallel lines of the second chip positioning boss preset position patterns.

Optionally, the preset position patterns of the first chip positioning boss and the preset position patterns of the second chip positioning boss are adjacent to each other to form a group of preset position patterns of corner chip positioning bosses, and the preset position patterns of the corner chip positioning bosses are two groups of diagonal positions.

The technical scheme of the invention has the following advantages:

1. according to the chip positioning structure provided by the invention, the embedded chip is limited in two directions by the four positioning bosses in a mode that the two first chip positioning bosses arranged in parallel and the two second chip positioning bosses arranged in parallel are perpendicular to the parallel lines of the two second chip positioning bosses, so that accurate positioning can be realized.

2. According to the chip positioning provided by the invention, the adjacent first chip positioning lug boss and the second chip positioning lug boss form a group of corner chip positioning lug bosses, and the two groups of corner chip positioning lug bosses are arranged in a diagonal manner. Two groups of chip positioning structures can be arranged at diagonal positions only, so that the chips can be positioned by occupying as little as possible, and a large amount of design space can be saved.

3. In the chip packaging structure provided by the invention, in each group of corner chip positioning bosses, a gap can exist between the first chip positioning boss and the second chip positioning boss. Namely, the formed corner chip positioning lug boss is a discontinuous pattern, and the discontinuous pattern is convenient for exchange of the flash etching liquid medicine and flowing of the medium layer during pressing.

4. According to the chip positioning structure provided by the invention, the height of the positioning structure is less than or equal to half of the height of the embedded chip. Enough process stability can be ensured in the process of forming the positioning structure, and the formed protection structure has good stability and strong binding force.

5. According to the chip packaging structure provided by the invention, the chip positioning structure is arranged on the surface of the chip embedding base layer, the chip positioning structure defines the chip embedding area, the embedded chip is attached to the chip embedding area, and the side wall of the embedded chip is attached and limited by the chip positioning structure, so that the displacement influence of the embedded chip is converted from slotting precision to positioning structure forming precision, the positioning structure can be formed by selecting a process with higher slotting precision than that in the prior art, and thus, smaller chip displacement can be realized.

6. According to the chip packaging structure provided by the invention, the chip positioning structure is a metal structure. The chip positioning structure is a metal structure and can be formed in a pattern electroplating mode after photoetching, the addition method of the pattern electroplating metal after photoetching can achieve higher precision compared with a subtractive method for etching a dielectric layer groove or a dielectric layer laser groove method, and possible displacement of the embedded chip can be effectively reduced. Furthermore, the chip embedding base layer is of a metal structure. The chip embedding base layer embedded into the bottom of the chip is a metal layer, so that the chip embedding base layer has a better heat dissipation function and signal transmission capability.

7. According to the chip packaging structure provided by the invention, the chip embedding region is defined by the plurality of chip positioning structures together, so that the definition of the chip embedding region can be realized by relatively less materials, and the structural space is saved. Meanwhile, the volume of the positioning structure or the occupied space is reduced to some extent compared with the structure of a full surrounding type, so that the arrangement of other structures or devices in the packaging structure is more free correspondingly, and the design of the packaging structure is facilitated.

8. The chip packaging structure manufacturing method provided by the invention comprises the steps that a chip positioning structure protruding from the surface of a chip embedding base layer is formed on the surface of the chip embedding base layer, a chip embedding area is defined by the chip positioning structure, and the size of the chip embedding area is suitable for embedding the embedded chip; the chip embedded base layer surface of the embedded chip surface-mounted to the chip embedded area, the lateral part of the embedded chip is bonded and limited by the positioning structure, the chip packaging structure can be manufactured, the displacement influence of the embedded chip is changed from slotting precision to positioning structure forming precision, the positioning structure can be formed by selecting a process higher than the slotting precision in the prior art, and thus smaller chip displacement can be realized.

9. According to the manufacturing method of the chip packaging structure, the chip positioning structure is formed by pattern electroplating after photoetching, compared with a subtractive method for etching a dielectric layer slot or a dielectric layer laser slot method, the additive method for pattern electroplating metal after photoetching can achieve higher precision, and possible displacement of a buried chip can be effectively reduced.

10. According to the manufacturing method of the chip packaging structure, the preset position patterns of the chip positioning structure formed by photoetching are the preset position patterns of two parallel first chip positioning bosses and the preset position patterns of two parallel second chip positioning bosses, so that the finally formed chip positioning structure can form the two parallel first chip positioning bosses and the two parallel second chip positioning bosses, the embedded chip can be limited in two directions through the four positioning bosses, and more accurate positioning can be realized. Furthermore, the chip positioning structure preset position patterns can only be arranged at the diagonal positions to form two groups of chip positioning structures, so that the chip can be positioned by occupying as small as possible, and a large amount of design space can be saved. Furthermore, the adjacent first chip positioning boss preset position pattern and the second chip positioning boss preset position pattern can form two discontinuous corner chip positioning boss preset position patterns, so that the finally formed chip positioning structure can form two discontinuous patterns, and the discontinuous patterns are convenient for flash etching liquid medicine exchange and medium layer flowing during pressing.

11. The semiconductor device comprises the chip positioning structure or the chip packaging structure, wherein the chip positioning structure which is protruded out of the surface of the chip embedding base layer is formed on the surface of the chip embedding base layer, the chip positioning structure defines a chip embedding area, and the size of the chip embedding area is suitable for embedding the embedded chip; the embedded chip is pasted to the chip embedded base layer, the side part of the embedded chip is attached to the limit position by the positioning structure, the chip packaging structure can be manufactured, the displacement influence of the embedded chip is changed from slotting precision to positioning structure forming precision, the positioning structure can be formed by selecting a process higher than the slotting precision in the prior art, and thus smaller chip displacement can be realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic top view of a buried chip package unit according to an embodiment of the present invention;

FIG. 2 is a schematic side view of a buried chip package unit according to an embodiment of the present invention;

FIGS. 3-11 are schematic diagrams of various states in the fabrication of a semiconductor device in an embodiment of the present invention;

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Example 1

As shown in fig. 1 and 2, the present embodiment provides a chip package structure, which includes a chip-embedded base layer 1 and an embedded chip 2. The surface of the chip embedded base layer 1 is provided with a chip positioning structure protruding from the surface of the chip embedded base layer 1. The chip positioning structure defines a chip embedding region (the position covered by the embedded chip 2 in fig. 1), and the size of the chip embedding region is suitable for embedding the embedded chip 2. The embedded chip 2 is attached to the chip embedding region of the chip embedded base layer 1, and the side part of the embedded chip 2 is limited by the attachment of a positioning structure.

According to the chip packaging structure provided by the invention, the chip positioning structure is arranged on the surface of the chip embedding base layer, the chip positioning structure defines the chip embedding area, the embedded chip is attached to the chip embedding area, and the side wall of the embedded chip is attached and limited by the chip positioning structure, so that the displacement influence of the embedded chip is converted from slotting precision to positioning structure forming precision, and the positioning structure can be formed by selecting a process with higher slotting precision than that in the prior art.

Specifically, the chip positioning structure is a metal structure. The chip positioning structure is a metal structure and can be formed in a pattern electroplating mode after photoetching, the addition method of the pattern electroplating metal after photoetching can achieve higher precision compared with a subtractive method for etching a dielectric layer groove or a dielectric layer laser groove method, and possible displacement of the embedded chip can be effectively reduced. For a common method of etching the dielectric layer slot or laser slot of the dielectric layer, the displacement of the embedded chip is about ten microns to tens of microns, but the chip packaging structure of the embodiment can form a chip positioning structure by a method of electroplating metal after photoetching, the chip is embedded in a chip embedding area defined by the chip positioning structure, and the displacement of the embedded chip can be controlled below 10 microns.

Specifically, the chip embedded base layer 1 is a metal structure. The chip embedding base layer 1 embedded into the bottom of the chip is a metal layer, so that the chip embedding base layer has a better heat dissipation function and signal transmission capability.

In some embodiments of the present invention, the chip positioning structure may be a plurality of chip positioning structures, and all the chip positioning structures collectively define the chip embedding region.

According to the chip packaging structure provided by the invention, the chip embedding region is defined by the plurality of chip positioning structures together, so that the definition of the chip embedding region can be realized by relatively less materials, and the structural space is saved. Meanwhile, the volume or the occupation of the chip positioning structure is reduced to some extent compared with the fully-enclosed structure, so that the arrangement of other structures or devices in the packaging structure is more free correspondingly, and the design of the packaging structure is facilitated.

In some embodiments of the present invention, the number of the chip positioning structures is four, and the chip positioning structures are divided into two first chip positioning bosses 11 arranged in parallel and two second chip positioning bosses 12 arranged in parallel, and parallel lines of the two first chip positioning bosses 11 are perpendicular to parallel lines of the two second chip positioning bosses 12. The embedded chip is limited in two directions by the four positioning bosses, so that more accurate positioning can be realized.

In some embodiments of the present invention, the first chip positioning boss and the second chip positioning boss are adjacent to each other to form a set of corner chip positioning bosses, and the two sets of corner chip positioning bosses are arranged diagonally. Through setting up like this, can only set up two sets of chip location structures in diagonal position to occupation of space as far as possible little realizes the location to the chip, can practice thrift a large amount of design spaces.

In some embodiments of the present invention, a gap exists between the first chip positioning boss and the second chip positioning boss in each set of corner chip positioning bosses. Namely, the formed corner chip positioning lug boss is a discontinuous pattern, and the discontinuous pattern is convenient for exchange of the flash etching liquid medicine and flowing of the medium layer during pressing.

In some embodiments of the present invention, the height of the positioning structure is less than or equal to half the height of the embedded chip. Further, the height of the positioning structure may be 5 μm to 8 μm. The height of the positioning structure is less than or equal to half of the height of the embedded chip, so that sufficient process stability can be ensured in the process of forming the positioning structure, and the formed protection structure has good stability and strong binding force.

Example 2

The present invention also provides a method for manufacturing a chip package structure according to embodiment 1, referring to fig. 1, fig. 2, fig. 5, fig. 6, and fig. 8. The method mainly comprises the following steps:

forming a chip positioning structure protruding from the surface of the chip embedded base layer on the surface of the chip embedded base layer 1, wherein the chip positioning structure defines a chip embedded region, and the size of the chip embedded region is suitable for embedding the embedded chip;

the embedded chip 2 is pasted to the surface of the chip embedded base layer 1 of the chip embedded area, and the side part of the embedded chip 2 is limited by the joint of the positioning structure.

In the steps shown in fig. 1, fig. 2, fig. 5, fig. 6 and fig. 8, two first chip positioning bosses 11 and two second chip positioning bosses 12 jointly define a chip embedding region, the embedded chip 2 is attached to the surface of the chip embedding base layer 1 in the chip embedding region, and the side portion of the embedded chip 2 is abutted and limited by the first chip positioning bosses 11 and the second chip positioning bosses 12.

The chip packaging structure manufacturing method provided by the invention comprises the steps that a chip positioning structure protruding from the surface of a chip embedding base layer is formed on the surface of the chip embedding base layer, a chip embedding area is defined by the chip positioning structure, and the size of the chip embedding area is suitable for embedding the embedded chip; the chip embedded base layer surface of the embedded chip surface-mounted to the chip embedded area, the lateral part of the embedded chip is bonded and limited by the positioning structure, the chip packaging structure can be manufactured, the displacement influence of the embedded chip is changed from 'slotting precision' to 'positioning structure forming precision', the forming of the positioning structure can be realized by selecting a process higher than the slotting etching precision of the prior art, and thus, smaller chip displacement can be realized. In the general method for etching the dielectric layer slot or laser slot of the dielectric layer, the displacement of the embedded chip is about ten microns to tens of microns, while the displacement of the embedded chip of the chip packaging structure of the invention can be controlled below 10 microns.

Further, the step of forming the chip positioning structure protruding from the surface of the chip-embedded base layer on the surface of the chip-embedded base layer includes:

and photoetching the chip embedded base layer to form a preset position pattern of the chip positioning structure, and electroplating the preset position pattern of the chip positioning structure to form the chip positioning structure.

According to the manufacturing method of the chip packaging structure, the chip positioning structure can be formed by pattern electroplating after photoetching, compared with a subtractive method for etching a dielectric layer slot or a dielectric layer laser slot method, the additive method for pattern electroplating metal after photoetching can achieve higher precision, and possible displacement of a buried chip can be effectively reduced.

Furthermore, in the step of forming the chip positioning structure preset position pattern, the formed chip positioning structure preset position pattern includes two first chip positioning boss preset position patterns arranged in parallel and two second chip positioning boss preset position patterns arranged in parallel, and parallel lines of the two first chip positioning boss preset position patterns are perpendicular to parallel lines of the two second chip positioning boss preset position patterns. Therefore, the finally formed chip positioning structure can form two parallel first chip positioning bosses and two parallel second chip positioning bosses, so that the embedded chips can be limited in two directions through the four positioning bosses, and more accurate positioning can be realized.

Furthermore, the chip positioning structure preset position patterns can only be arranged at the diagonal positions to form two groups of chip positioning structures, so that the chip can be positioned by occupying as small as possible, and a large amount of design space can be saved.

Furthermore, the adjacent first chip positioning boss preset position pattern and the second chip positioning boss preset position pattern can form two discontinuous corner chip positioning boss preset position patterns, so that the finally formed chip positioning structure can form the two discontinuous corner chip positioning boss preset position patterns, and the discontinuous patterns are convenient for flash etching liquid medicine exchange and medium layer flowing during pressing.

Example 3

The present embodiment also provides a semiconductor device including the chip package structure according to embodiment 1 above.

Referring to fig. 11, the semiconductor device includes a core board 4, a through-hole 5 penetrating the core board 4, an inner layer wiring 7 on a surface of the core board 4, an inner layer filling dielectric layer 6 covering the core board 4 and exposing the inner layer wiring 7, a sub-outer layer wiring 8 on the inner layer wiring 7, and a chip package structure as in embodiment 1 on the inner layer filling dielectric layer 6.

The chip that is formed with on the inlayer packing medium layer 6 and buries chip packaging unit buries basic unit 1, chip buries basic unit 1 and is the metal level, the chip buries and is formed with chip location structure on the basic unit 1, chip location structure divide into two first chip location bosss 11 and two second chip location bosss 12, a chip embedding region is defined jointly to four chip location structures, it buries basic unit 1 surface to bury the chip that chip 2 pasted dress to this chip embedding region, it is spacing to bury the lateral part of chip 2 by 4 chip location structure laminating.

In addition, the semiconductor device of the embodiment further includes an outer layer filling dielectric layer 3, and the outer layer filling dielectric layer 3 covers the embedded chip packaging unit, the inner layer filling dielectric layer 6 and a part of the outer layer circuit 8. The outer-layer filling dielectric layer 3 is formed with an opening that exposes a portion of the sub-outer-layer wiring 8. The semiconductor device of the present embodiment further includes an outer layer wiring 9 over the sub-outer layer wiring 8 and a solder resist layer over the outer layer filling dielectric layer 3.

The semiconductor device comprises the chip packaging structure, wherein a chip positioning structure which is protruded from the surface of a chip embedding base layer is formed on the surface of the chip embedding base layer, the chip positioning structure defines a chip embedding area, and the size of the chip embedding area is suitable for embedding the embedded chip; the embedded chip is pasted to the chip embedded base layer, the side part of the embedded chip is attached to the limit position by the positioning structure, the chip packaging structure can be manufactured, the displacement influence of the embedded chip is changed from slotting precision to positioning structure forming precision, the positioning structure can be formed by selecting a process higher than the slotting precision in the prior art, and thus smaller chip displacement can be realized. In the conventional method of etching the dielectric layer slot or laser slot of the dielectric layer, the displacement of the embedded chip is about ten microns to tens of microns, whereas the displacement of the embedded chip can be controlled below 10 microns in the chip packaging structure manufactured by the manufacturing method of the chip packaging structure of the embodiment.

Example 4

Referring to fig. 3 to 11, the present embodiment provides a method of manufacturing the semiconductor device in embodiment 3 described above.

The method for manufacturing a semiconductor device of the present embodiment includes the steps of:

referring to fig. 3, through holes 5 penetrating through the core board are formed on the core board 4, and inner layer circuits 7 are formed on the upper and lower surfaces of the core board 4, respectively; the inner layer wiring 7 and the core board 4 constitute a first substrate.

In some embodiments, the step may be: and (3) mechanically drilling after baking the core plate 4 to realize the interconnection through holes of the upper layer and the lower layer of the core plate, ultrasonically cleaning the copper to realize in-hole metallization and an inner layer circuit seed layer, then pasting a film, exposing and developing the pattern for electroplating, and removing the inner layer circuit seed layer which is not covered by the electroplated metal to form an inner layer circuit 7 on the surface of the core plate 4.

Referring to fig. 4, the via hole 5 is filled, and an inner layer filling dielectric layer 6 is formed on the first substrate, and planarization is performed on the upper and lower surfaces.

In some embodiments, the step of forming the interlayer dielectric layer 6 may be: and performing lamination according to the laminated structure of the upper medium prepreg, the first substrate and the lower medium prepreg to form an inner filling medium layer 6.

Referring to fig. 5, holes are drilled at desired locations on the inner fill dielectric layer 6 and a first metal layer is formed to cover the surface.

In some embodiments, the step may be: and forming an opening by a conventional laser blind hole drilling process, and forming a first metal layer by surfacing copper of the inner-layer filling dielectric layer 6 after ultrasonic cleaning.

Referring to fig. 6, a chip positioning structure is formed on the first metal layer.

In some embodiments, the step may be: and pattern electroplating is carried out after the pattern of the chip positioning structure is exposed and developed, two discontinuous L-shaped chip positioning structures (respectively consisting of a first chip positioning boss 11 and a second chip positioning boss 12) are formed at diagonal positions, and the height of the chip positioning structure is half of the height of a normal circuit.

Referring to fig. 7, the sub-outer layer lines 8 are formed at corresponding positions.

In some embodiments, the step may be: and covering and protecting the chip positioning structure by using a dry film, adhering a film, exposing and developing the circuit layer pattern for electroplating, wherein the height of the electroplating layer is twice of that of the chip positioning structure, and removing the seed layer to form the circuit pattern.

Referring to fig. 8, the embedded chip 2 is attached to the surface of the chip-embedding base layer 1 of the chip-embedding region.

Referring to fig. 9, an outer-layer filling dielectric layer 3 and a sub-outer-layer wiring 8 are formed.

In some embodiments, the step may be: selecting a semi-solidified material with better filling performance to press the two surfaces of the metal substrate with the chip, so as to form an outer filling dielectric layer 3; drilling blind holes by laser, and metallizing copper after ultrasonic cleaning to form a secondary outer layer circuit 8;

referring to fig. 10, an outer layer wire 9 is formed on the sub-outer layer wire 8.

In some embodiments, the step may be: and carrying out pattern electroplating after film pasting exposure and development to form an outer layer circuit 9.

Referring to fig. 11, a solder resist layer is formed on the surface of the outer layer filling dielectric layer 3, and the solder resist layer exposes the outer layer wiring 9.

The semiconductor device provided by the embodiment comprises the chip packaging structure, wherein a chip positioning structure protruding from the surface of the chip embedding base layer is formed on the surface of the chip embedding base layer, the chip positioning structure defines a chip embedding area, and the size of the chip embedding area is suitable for embedding the embedded chip; the embedded chip is pasted to the chip embedded base layer, the side part of the embedded chip is attached to the limit position by the positioning structure, the chip packaging structure can be manufactured, the displacement influence of the embedded chip is changed from slotting precision to positioning structure forming precision, the positioning structure can be formed by selecting a process higher than the slotting precision in the prior art, and thus smaller chip displacement can be realized. In the conventional method of etching the dielectric layer slot or laser slot of the dielectric layer, the displacement of the embedded chip is about ten microns to tens of microns, whereas the displacement of the embedded chip can be controlled below 10 microns in the chip packaging structure manufactured by the manufacturing method of the chip packaging structure of the embodiment.

The present invention has been described above by way of examples, and it is believed that one skilled in the art can appreciate the present invention by way of the above examples. It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.