阅读说明：本技术 半导体设备封装和其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 李志成 于 2020-02-20 设计创作，主要内容包括：本公开提供一种半导体设备封装。所述半导体设备封装包含：电子组件；第一钝化层,其具有包围所述电子组件的内表面；以及导电层,其安置在所述第一钝化层的所述内表面上。所述电子组件具有第一表面、与所述第一表面相对的第二表面以及在所述第一表面与所述第二表面之间延伸的侧面。所述导电层具有相对粗糙的表面。还公开了一种制造半导体设备封装的方法。(The present disclosure provides a semiconductor device package. The semiconductor device package includes: an electronic component; a first passivation layer having an inner surface surrounding the electronic component; and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a side extending between the first surface and the second surface. The conductive layer has a relatively rough surface. A method of manufacturing a semiconductor device package is also disclosed.)

1. A semiconductor device package, comprising:

an electronic component having a first surface, a second surface opposite the first surface, and a side extending between the first surface and the second surface;

a first passivation layer having an inner surface surrounding the electronic component;

a conductive layer disposed on the inner surface of the first passivation layer and having a relatively rough surface.

2. The semiconductor device package of claim 1, wherein the conductive layer has a first portion that extends into the first passivation layer.

3. The semiconductor device package of claim 1, wherein the inner surface of the first passivation layer has a step.

4. The semiconductor device package of claim 3, wherein the step is in direct contact with the conductive layer.

5. The semiconductor device package of claim 3, wherein the conductive layer has a sloped surface.

6. The semiconductor device package of claim 3, wherein the conductive layer has a curved surface.

7. The semiconductor device package of claim 1, wherein the relatively rough surface of the conductive layer has an arithmetic average roughness (Ra) in a range of about 0.3 micrometers (μ ι η) to about 1.0 μ ι η.

8. The semiconductor device package of claim 1, wherein the relatively rough surface of the conductive layer has a ten point average roughness (Rz) in a range of about 3.0 μ ι η to about 10.0 μ ι η.

9. The semiconductor device package of claim 1, further comprising:

a second passivation layer between the electronic component (20) and the conductive layer.

10. The semiconductor device package of claim 9, wherein the second passivation layer is in direct contact with the conductive layer.

11. The semiconductor device package of claim 1, wherein the first passivation layer includes a core substrate defining a space and the electronic component is received in the space.

12. The semiconductor apparatus package of claim 11, further comprising:

a second passivation layer disposed in the space defined by the core layer.

13. A semiconductor device package, comprising:

an electronic component having a first surface, a second surface opposite the first surface, and a side extending between the first surface and the second surface; and

a first passivation layer having a first surface, a second surface opposite the first surface, and an inner surface surrounding the electronic component, wherein the inner surface includes a first portion and a second portion on the first portion; and

a conductive layer disposed on the inner surface of the first passivation layer;

wherein the first portion of the inner surface of the first passivation layer has a first width and the second portion of the inner surface of the first passivation layer has a second width, and the second width is greater than the first width.

14. The semiconductor device package of claim 13, wherein the inner surface has a step.

15. The semiconductor device package of claim 14, wherein the step is in direct contact with the conductive layer.

16. The semiconductor device package of claim 15, wherein the conductive layer has a sloped surface.

17. The semiconductor device package of claim 13, wherein the conductive layer has an extension into the first passivation layer.

18. A method for manufacturing a semiconductor device package, comprising:

providing a first passivation layer having a first surface and a second surface opposite the first surface;

forming a recess through the first passivation layer, wherein an inner surface extending between the first surface and the second surface is defined after the recess is formed;

disposing a conductive layer on the inner surface of the first passivation layer; and

performing a surface treatment on the conductive layer.

19. The method of claim 18, further comprising:

forming a stepped feature on the inner surface of the first passivation layer.

20. The method of claim 19, further comprising:

covering the stepped feature with the conductive layer.

Technical Field

The present disclosure relates generally to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package having a conductive layer and a method of manufacturing the same.

Background

A semiconductor device package may include some semiconductor devices (e.g., chips or dies) disposed on a carrier. Some devices may be removable or embedded in a carrier to reduce the size of the semiconductor device package.

As technology advances, it is desirable to embed relatively more components into a carrier for miniaturization, which necessarily reduces the distance between the components and the sidewalls defining the space (e.g., cavity or void) in which the components are received. The above mentioned reduction of the distance can be a great challenge when filling dielectric or passivation material into the space. Furthermore, if more components are integrated into the carrier, the heat dissipation problem may become severe.

Disclosure of Invention

In one or more embodiments, a semiconductor device package includes an electronic component; a first passivation layer having an inner surface surrounding the electronic component and a conductive layer disposed on the inner surface of the first passivation layer. The electronic component has a first surface, a second surface opposite the first surface, and a side extending between the first surface and the second surface. The conductive layer has a relatively rough surface.

In one or more embodiments, a semiconductor device package includes an electronic component having a first surface, a second surface opposite the first surface, and a side extending between the first surface and the second surface. The semiconductor device package further includes a first passivation layer having a first surface, a second surface opposite the first surface, and an inner surface surrounding an electronic component. The semiconductor device package further includes a conductive layer disposed on an inner surface of the first passivation layer. The inner surface includes a first portion and a second portion on the first portion. A first portion of the inner surface of the first passivation layer has a first width and a second portion of the inner surface of the first passivation layer has a second width. The second width is greater than the first width.

In one or more embodiments, a method for fabricating a semiconductor device package includes providing a first passivation layer. The first passivation layer has a first surface and a second surface opposite the first surface. The method further includes forming a recess through the first passivation layer. An inner surface extending between the first surface and the second surface is defined after the recess is formed. The method further includes disposing a conductive layer on an inner surface of the first passivation layer. The method further includes performing a surface treatment on the conductive layer.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. The dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2A illustrates an enlarged view of a portion of a semiconductor device package according to some embodiments of the present disclosure.

Fig. 2B illustrates an enlarged view of a portion of a semiconductor device package according to some embodiments of the present disclosure.

Fig. 3 illustrates an enlarged cross-sectional view of a portion of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 4 illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5A illustrates one or more stages of a method of manufacturing a semiconductor apparatus package, in accordance with some embodiments of the present disclosure.

Fig. 5B illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5C illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5D illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5E illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5F illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5G illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Fig. 5H illustrates one or more stages of a method of manufacturing a semiconductor device package, in accordance with some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. The present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In the present disclosure, in the following description, a reference to forming a first feature over or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Fig. 1 illustrates a cross-sectional view of a semiconductor device package 1, according to some embodiments of the present disclosure.

Referring to fig. 1, a semiconductor apparatus package 1 may include: interconnect structure 10, further interconnect structure 11, electronic component 12, further electronic component 13, encapsulation layer 14, electrical contacts 15, electronic component 20, carrier 21, conductive layer 22, and passivation layer 23.

The carrier 21 may comprise a surface 211 and a surface 212 opposite the surface 211. The carrier 21 may include a cavity or space extending between the surface 211 and the surface 212. The carrier 21 may comprise a surface 213 (or an inner surface) and a surface 214 (or an outer surface) opposite the surface 213. Surface 213 may be referred to as a sidewall or side of the cavity or space.

In some embodiments, carrier 21 may include interconnect structures such as conductive traces (e.g., portion 22a) or vias. The carrier 21 may comprise a core substrate or core substrate. In some embodiments, the core substrate of the carrier 21 may comprise, for example but not limited to, a molding compound, Bismaleimide Triazine (BT), Polyimide (PI), Polybenzoxazole (PBO), solder mask, ajinomoto film (ABF), polypropylene (PP), epoxy-based material, or a combination of two or more thereof.

The electronic component 20 may be positioned in a space defined by the surface 213 of the carrier 21. The electronic component 20 may be received in a space defined by the surface 213 of the carrier 21. The electronic component 20 may be surrounded by a surface 213 of the carrier 21.

The electronic component 20 may include a surface 201, a surface 202 opposite the surface 201, and a surface 203 (or side) extending between the surface 201 and the surface 202. The surface 203 may face the surface 213 of the carrier 21.

As more components, such as a plurality of electronic components 20, need to be received in the cavities or spaces defined in the carrier, such as carrier 21, to achieve miniaturization, the distance between the components and the sides of the space, such as the distance between surface 213 of carrier 21 and surface 203 of electronic component 20, may necessarily be reduced, such that processing difficulties arise in subsequent filling operations (such as the operations illustrated in fig. 5F) of the dielectric material in the space, such as the dielectric material of passivation layer 23. Furthermore, if more components are integrated into the carrier, the heat dissipation problem may become severe.

By providing the conductive layer 22 on the surface 213 of the carrier 21 and performing a surface treatment on the conductive layer 22 to adjust the surface roughness of the conductive layer 22, the fluidity of the dielectric material of the passivation layer 23 to be filled in the space can be promoted and a good adhesion between the conductive layer 22 and the passivation layer 23 can be obtained. Furthermore, conductive layer 22 may help promote heat dissipation in semiconductor device package 1.

As shown in fig. 1, electronic component 20 may be surrounded by passivation layer 23, conductive layer 22, and carrier 21. Passivation layer 23 may surround electronic component 20 and be surrounded by conductive layer 22. The conductive layer 22 may surround the passivation layer 23 and be surrounded by the carrier 21.

The conductive layer 22 may be disposed on the inner surface 213 of the carrier 21. The conductive layer 22 may be in direct contact with the inner surface 213 of the carrier 21.

The conductive layer 22 may be connected to a portion 22a of the carrier 21. In some embodiments, portion 22a may be of the same material as conductive layer 22. In some embodiments, portion 22a may be an extension of conductive layer 22. For example, the portion 22a may extend toward the outer surface 214. Extended portions of conductive layer 22 (e.g., portion 22a) may help to enhance adhesion of conductive layer 22. The extended portion (e.g., portion 22a) of conductive layer 22 may help prevent delamination of conductive layer 22.

In some embodiments, conductive layer 22 may include, for example, but not limited to, aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni), or stainless steel or mixtures or other combinations thereof. In some embodiments, portion 22a may be of a different material than conductive layer 22.

A passivation layer 23 may be disposed between the conductive layer 22 and the electronic component 20. The passivation layer 23 may be in direct contact with the electronic component 20. The passivation layer 23 may be in direct contact with the conductive layer 22.

In some embodiments, the passivation layer 23 may include, for example but not limited to, a dielectric material, such as a prepreg composite fiber (e.g., prepreg), ajinomoto film, a resin, an epoxy-based material, or a combination of two or more thereof.

The passivation layer 23 may comprise a flowable dielectric material that may be filled into the spaces of the carrier 21 (as in the filling operation illustrated in fig. 5F).

In some embodiments, the space may be provided with a wider opening to promote fluidity of the dielectric material of the passivation layer 23. In some embodiments, the wider opening can help fill the dielectric material in the space without introducing voids into the space.

For example, the surface 213 of the carrier 21 may comprise a portion having a first width "w 1" (which may also be referred to as a first portion of the surface 213) and another portion having a second width "w 2" (which may also be referred to as a second portion of the surface 213). The second portion may be proximate to the surface 211 of the carrier 21. The second portion may be defined by a sidewall 21s1 (as indicated in fig. 2B) of the carrier 21 connected to the surface 211.

The first width w1 may be different from the second width w 2. For example, as illustrated in fig. 1, the first width w1 is less than the second width w 2. The second width w2 is greater than the first width w 1.

In some embodiments, the height of the surface 201 of the electronic component 20 may be different from the height of the surface 211 of the carrier 21. For example, as illustrated in fig. 1, the surface 201 of the electronic component 20 is lower than the surface 211 of the carrier 21. The surface 211 of the carrier 21 is higher than the surface 201 of the electronic component 20.

The interconnect structures 10 and 11 may be disposed on surfaces (e.g., top and bottom surfaces) of the carrier 21. Interconnect structures 10 and 11 may include redistribution layers (RDLs) and may include conductive elements, such as pads, wires, and/or vias, and dielectric layers. A portion of the conductive element is covered or encapsulated by the dielectric layer, while another portion of the conductive element is exposed from the dielectric layer to provide electrical connections for the carrier 21 (and the electronic component 20 embedded in the carrier 21), the electronic components 12 and 13, and the electrical contacts 15.

Electronic components 12 and 13 may be disposed on a surface of interconnect structure 10 facing away from carrier 21.

An encapsulation layer 14 may be disposed on the interconnect structure 10 to cover or encapsulate the electronic components 12 and 13. In some embodiments, the encapsulation layer 14 may include, for example but not limited to, an epoxy with filler, a molding compound (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material having silicone dispersed therein, or a combination thereof.

Electrical contacts 15, such as solder balls, may be disposed on a surface of interconnect structure 11 facing away from carrier 21 and may provide electrical connections between semiconductor package apparatus 1 and external components, such as external circuitry or circuit boards. In some embodiments, the electrical contacts 15 may include controlled collapse chip connection (C4) bumps, Ball Grid Arrays (BGAs), or Land Grid Arrays (LGAs).

Each of electronic components 12, 13, and 20 may include a chip or die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures. An integrated circuit device may include active devices such as transistors and/or passive devices such as resistors, capacitors, inductors, or combinations thereof.

In some embodiments, any number of electronic components may be present in the semiconductor device package 1 depending on product specifications. For example, there may be any number of electronic components embedded in carrier 21. For example, there may be any number of electronic components disposed on the interconnect structure 10.

Fig. 2A illustrates an enlarged view of a portion of a semiconductor device package according to some embodiments of the present disclosure. For example, the portion in the dashed box 2A in fig. 1 may be the portion illustrated in fig. 2A.

As shown in fig. 2A, conductive layer 22 may include a surface in contact with surface 213 of carrier 21 and an opposing surface 223 in contact with passivation layer 23. The surface 223 of the conductive layer 22 may be a relatively rough (or relatively uneven) surface.

For example, a portion of the surface 223 in direct contact with the passivation layer 23 may have a roughness that is greater than a roughness of other portions of the surface 223. For example, the roughness of the surface 223 of the conductive layer 22 may be greater than the roughness of the surface of the conductive layer 22 opposite the surface 223.

In some embodiments, the roughness of the surface 223 of the conductive layer 22 may be less than the roughness of the surface 213 of the carrier 21.

In some embodiments, the surface 223 of the conductive layer 22 has an arithmetic average roughness (Ra) in a range of about 0.3 micrometers (μm) to about 1.0 μm. In some embodiments, the surface 223 of the conductive layer 22 has a ten point average roughness (Rz) in a range of about 3.0 μm to about 10.0 μm.

In some embodiments, the roughness of the surface 223 of the conductive layer 22 may be designed to be less than or equal to a value to promote flowability of the dielectric material of the passivation layer 23. In some embodiments, the roughness of the surface 223 of the conductive layer 22 may be designed to be higher than or equal to a value to avoid delamination of the passivation layer 23 from the conductive layer 22.

In some embodiments, the passivation layer 23 may have a surface 233 in contact with the electronic component 20 and an opposite surface in contact with the conductive layer 22. The surface of the passivation layer 23 in contact with the conductive layer 22 may be a relatively rough or relatively uneven surface.

Passivation layer 23 may be bonded to conductive layer 22. For example, the surface of passivation layer 23 in contact with conductive layer 22 may bond with the relatively rough surface 223 of conductive layer 22, which enhances adhesion between conductive layer 22 and passivation layer 23.

Fig. 2B illustrates an enlarged view of a portion of a semiconductor device package according to some embodiments of the present disclosure. For example, the portion in the dashed box 2B in fig. 1 may be the portion illustrated in fig. 2A.

As shown in fig. 2B, surface 213 of carrier 21 includes sidewall 21s1, top surface 21t, and sidewall 21s 2. The sidewall 21s1 may be substantially perpendicular to the surface 211. The top surface 21t may be substantially coplanar with the surface 211. Surface 211 may be connected to top surface 21t via sidewalls 21s 1. The surface 211, the side walls 21s1, and the top surface 21t can define steps (or stepped features or stepped structures) on the surface 213 of the carrier 21.

The conductive layer 22 covers or encapsulates a portion of the surface 211 of the carrier. The conductive layer 22 covers or encapsulates the steps on the surface 213 of the carrier 21. Conductive layer 22 covers or encapsulates sidewalls 21s1 and top surface 21t of carrier 21.

The conductive layer 22 is in direct contact with a portion of the surface 211 of the carrier. The conductive layer 22 is in direct contact with the step on the surface 213 of the carrier 21. Conductive layer 22 is in direct contact with sidewalls 21s1 and top surface 21t of carrier 21.

The surface 223 of the conductive layer 22 above the step may be an inclined or curved surface. For example, the conductive layer 22 fills in the angle defined by the surface 21s1 and the surface 21 t. For example, conductive layer 22 covers the angle defined by surface 21s1 and surface 21 t.

In some embodiments, the inclined or curved surface of the conductive layer 22 above the step may help to guide the dielectric material of the passivation layer 23 into the space of the carrier 21.

Fig. 3 illustrates an enlarged cross-sectional view of structure 3 of a semiconductor device package according to some embodiments of the present disclosure. In some embodiments, the structure 3 in fig. 3 may be substituted for the structure in dashed box 2 in fig. 1.

The structure 3 in fig. 3 is similar to the structure within the dashed box 2 in fig. 1, and the differences between the two structures are described below.

The conductive layer 22 may be connected to a tapered portion 22b in the carrier 21. In some embodiments, tapered portion 22b may be a portion of conductive layer 22 that extends into carrier 21. For example, the portion 22b of the conductive layer 22 may taper from the surface 213 of the carrier 21 towards the surface 214 of the carrier 21. In some embodiments, the tapered structure may help to enhance adhesion between carrier 21 and conductive layer 22.

Although the drawings illustrate specific shapes, the disclosure is not so limited. The extension of the conductive layer into the carrier 21 may have any shape.

Fig. 4 illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure. In some embodiments, the top view of the semiconductor device package 1 in fig. 1 may be similar to the top view in fig. 4.

The conductive layer 22 and passivation layer 23 as shown in fig. 1 are omitted in fig. 4 for clarity and simplicity.

As shown in fig. 4, the carrier 21 includes an outer surface 214, a surface 211, and an inner surface 213 (including the side wall 21s1, the side wall 21s2, and the top surface 21 t). The sidewall 21s1 may be substantially perpendicular to the surface 211. The sidewall 21s2 may be substantially perpendicular to the surface 211. The top surface 21t may be substantially coplanar with the surface 211. The surface 211 may be connected to the top surface 21t via the side wall 21 s.

The space defined by the side wall 21s1 has a width w 2. The space defined by the side wall 21s2 has a width w 1. Width w2 may be immediately adjacent to surface 211. In some embodiments, the space defined by the side walls 21s1 may have any suitable shape, and the invention is not limited to the specific embodiments illustrated in the drawings.

In fig. 4, there is more than one electronic component (e.g., electronic components 20A, 20B, 20C, and 20D) housed in the space in the carrier 21. As mentioned, in case a conductive layer having a surface roughness is provided on the surface 213 of the carrier 21, the flowability of the dielectric material into the space may be promoted. Accordingly, the capacity of the electronic components in the semiconductor device package can be increased.

Fig. 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are cross-sectional views of wiring structures at various stages of fabrication according to some embodiments of the present disclosure. At least some of these drawings have been simplified for a better understanding of the various aspects of the disclosure.

Referring to fig. 5A, a carrier 21 may be provided. The carrier 21 may include a surface 211, a surface 212 opposite the surface 211, and a surface 214 extending between the surface 211 and the surface 212. The carrier 21 may comprise an interconnect structure such as a plurality of conductive traces 21a or vias.

Referring to fig. 5B, a space or recess 21r may be formed in the carrier 21. The recess 21r may penetrate the carrier 21. The recess 21r may have a surface 213 extending between the surface 211 and the surface 212.

The surface 21a1 of the conductive trace 21a in the carrier 21 may be exposed after the recess 21r is formed.

Referring to fig. 5C, a step is formed on surface 213. In some embodiments, the ladder may be formed by a router (router machine), laser, or other cutting or shaping means. The step may promote the mobility of the dielectric material in subsequent operations.

The side walls 21s1 and the top surface 21t may be formed after a cutting or shaping operation.

Referring to fig. 5D, a conductive layer 22 may be disposed on surface 213. The steps may be covered by a conductive layer 22.

Conductive layer 22 and conductive trace 21a in carrier 21 may be bonded to enhance the adhesion of conductive layer 22.

A surface treatment may be performed on the conductive layer 22 to adjust the surface roughness of the conductive layer 22. In some embodiments, the surface treatment may be performed by, for example, an etchant or via other suitable surface treatment.

After the surface treatment, the conductive layer 22 may include a relatively rough surface surrounding the recess 21 r. The relatively rough surface maintains good adhesion between the conductive layer 22 and the dielectric material formed in subsequent operations.

Referring to fig. 5E, the structure resulting from the operation in fig. 5D may be disposed on a temporary carrier or adhesive layer 20 a. The electronic component 20 may be disposed on the adhesive layer 20 a.

The electronic component 20 may be received in the recess 21r as shown in fig. 5D. The electronic component 20 may be surrounded by a conductive layer 22 on the surface 213 of the carrier 21. After the electronic component 20 is received in the recess 21r, a remaining space 21r1 may be defined between the electronic component 20 and the conductive layer 22.

The electronic component 20 may include a surface 201, a surface 202 opposite the surface 201, and a surface 203 (or side) extending between the surface 201 and the surface 202. Electronic assembly 20 may include conductive pad 20c1 on surface 201 and conductive pad 20c2 on surface 202.

Referring to fig. 5F, the remaining space 21r1 as shown in fig. 5E may be filled with a dielectric material, forming a passivation layer 23. In some embodiments, the filling operation may be performed by, for example, an inkjet printing process. The height of the surface 201 of the electronic component 20 may be lower than the height of the surface 211 of the carrier 21 to facilitate filling with the dielectric material. After the dielectric material is filled in the remaining space 21r1, the adhesive layer 20a as shown in fig. 5E may be removed.

Referring to fig. 5G, a dielectric layer 101 may be disposed on the carrier 21 and the passivation layer 23. In some embodiments, dielectric layer 101 may be formed by, for example, coating, lamination, or other suitable processes. Subsequently, a photoresist film (or mask) may be formed on the dielectric layer 101, and the dielectric layer 101 may be patterned via the mask to form a cavity and expose a portion of the conductive pad 20c 1. A conductive material may be disposed on exposed surfaces of dielectric layer 101 and conductive pad 20c1, forming conductive traces and vias that are electrically connected to conductive pad 20c 1.

Similar to dielectric layer 101, dielectric layer 111 can be disposed and patterned on carrier 21 and passivation layer 23. A conductive material may be disposed on the exposed surfaces of the dielectric layer 111 and the conductive pad 20c2 forming conductive traces and vias that are electrically connected to the conductive pad 20c 2.

The operations described above for forming dielectric layers 101 and 111 and conductive traces and vias may be performed repeatedly two or more times to form multiple layers of dielectric layers and conductive traces, and the resulting structure is shown in fig. 5H.

Referring to fig. 5H, interconnect structures 10 and 11 may be disposed on surfaces (e.g., top and bottom surfaces) of carrier 21.

In some embodiments, one or more electronic components (such as electronic components 12 and 13 illustrated in fig. 1) may be disposed on a surface of the interconnect layer 10 that faces away from the carrier 21 through a capillary or via other means. In some embodiments, the electronic components may be disposed on an adhesive layer, glue, or other intermediate layer for die attachment. In some embodiments, an encapsulation layer (such as the encapsulation layer 14 illustrated in fig. 1) may be disposed on the interconnect layer 10 to cover or encapsulate the electronic component. In some embodiments, the encapsulation layer may be formed by a molding technique (e.g., transfer molding or compression molding). In some embodiments, one or more electrical contacts (such as electrical contact 15 illustrated in fig. 1) may be provided on a surface of the interconnect layer 11 facing away from the carrier 21. The resulting structure may be similar to the semiconductor device package 1 as illustrated in fig. 1.

Spatially relative terms, such as "below," "below … …," "lower," "above … …," "upper," "left," "right," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain the minor variations. When used in conjunction with an event or circumstance, the terms can refer to the exact occurrence of the event or circumstance, as well as to the very approximate occurrence of the event or circumstance. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces located along the same plane within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm. When referring to "substantially" the same numerical value or property, the term can refer to a value that is within ± 10%, ± 5%, ± 1%, or ± 0.5% of the mean of the values.

The foregoing summarizes features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present disclosure.