阅读说明：本技术 感测装置的封装结构以及其制造方法 (Packaging structure of sensing device and manufacturing method thereof ) 是由 曾昭崇 许哲玮 于 2020-11-25 设计创作，主要内容包括：一种感测装置的封装结构,包括一感测芯片、一介电层、一第一导线层、一第二导线层、至少一导电柱、至少一正面扇出线路。感测芯片的作用面具有一感测区域以及一设有金属垫的金属垫区域。介电层包覆该感测芯片的周身、背面及局部的该作用面,且其第一表面高于该感测芯片的该作用面,以曝露出该感测芯片的该感测区域。第一导线层与第二导线层分别设置于该介电层的该第一表面与第二表面。导电柱设于该介电层内,且连接该第一导线层及该第二导线层。正面扇出线路连接该第一导线层与该感测芯片的该金属垫。本发明复提供一种制造上述感测装置的封装结构的方法。(A packaging structure of a sensing device comprises a sensing chip, a dielectric layer, a first conducting wire layer, a second conducting wire layer, at least one conducting column and at least one front fan-out circuit. The active surface of the sensing chip is provided with a sensing area and a metal pad area provided with a metal pad. The dielectric layer covers the whole body, the back surface and part of the action surface of the sensing chip, and the first surface of the dielectric layer is higher than the action surface of the sensing chip so as to expose the sensing area of the sensing chip. The first and second conductive layers are disposed on the first and second surfaces of the dielectric layer, respectively. The conductive column is arranged in the dielectric layer and connected with the first conducting wire layer and the second conducting wire layer. The fan-out circuit on the front surface is connected with the first lead layer and the metal pad of the sensing chip. The invention further provides a method for manufacturing the packaging structure of the sensing device.)

1. The packaging structure of the sensing device is characterized by comprising: the sensing chip is provided with an action surface and a back surface which are oppositely arranged, and the action surface is provided with a sensing area and a metal pad area provided with at least one metal pad;

a dielectric layer, which covers the whole body, the back surface and the metal pad region of the sensing chip and is provided with a first surface and a second surface which are oppositely arranged, wherein the first surface of the dielectric layer is higher than the action surface of the sensing chip and exposes the sensing region of the sensing chip;

a first conductive line layer disposed on the first surface of the dielectric layer;

a second conductive line layer disposed on the second surface of the dielectric layer;

at least one conductive column arranged in the dielectric layer and connected with the first conducting wire layer and the second conducting wire layer; and

at least one front fan-out circuit connecting the first conductive layer and the metal pad of the sensing chip.

2. The package structure of claim 1, wherein the metal pad and the region of the metal pad between the inner side of the metal pad and the sensing region are exposed at the first surface of the dielectric layer, and the region of the metal pad between the outer side of the metal pad and the edge of the active surface is covered by the dielectric layer.

3. The package structure of the sensing device as claimed in claim 1 or 2, wherein at least one back fan-out line is further disposed in the dielectric layer for connecting the back surface of the sensing chip and the second conductive layer.

4. The package structure of the sensor device as claimed in claim 1 or 2, wherein the first surface of the dielectric layer is further provided with a passivation layer to cover the first conductive layer and expose the sensing region.

5. The package structure of claim 1, wherein the front fan-out trace is at least one conductive via post.

6. The package structure of sensing device as claimed in claim 2, wherein the front fan-out line is at least one conductive pillar.

7. The manufacturing method of the packaging structure of the sensing device is characterized by comprising the following steps:

providing a sensing chip, which is provided with an action surface and a back surface which are oppositely arranged, wherein the action surface is provided with a sensing area and a metal pad area provided with at least one metal pad;

arranging an attaching layer on the action surface of the sensing chip to cover at least the sensing area;

arranging the sensing chip on a carrier plate at the side of the attaching layer, wherein one upper surface of the attaching layer is connected with the carrier plate;

forming a dielectric layer on the carrier plate to cover the whole body, the back surface and the metal pad region of the sensing chip, wherein the dielectric layer is provided with a first surface and a second surface which are oppositely arranged, the first surface of the dielectric layer is jointed with the carrier plate and is coplanar with the upper surface of the attaching layer;

removing the carrier plate to expose the first surface of the dielectric layer and the upper surface of the attaching layer;

forming a first conductive line layer on the first surface of the dielectric layer;

forming at least one front fan-out circuit between the first wire layer and the metal pad of the sensing chip to connect the first wire layer and the metal pad;

forming a second conductive line layer on the second surface of the dielectric layer;

forming at least one conductive column between the first conductive layer and the second conductive layer to connect the first conductive layer and the second conductive layer; and

the adhesive layer is removed to expose at least the sensing region of the sensing chip, wherein the first surface of the dielectric layer is higher than the active surface of the sensing chip.

8. The method of claim 7, further comprising, before the step of forming the second conductive layer, the steps of forming a back fan-out line by:

forming at least one blind hole in the dielectric layer to expose a portion of the backside of the sensing chip to the second surface; and

and electroplating a conductive blind hole column in the blind hole to form the back fan-out circuit so as to connect the back and the second conductor layer.

9. The method of manufacturing of claim 7, wherein the method of forming the front side fan-out line further comprises the steps of:

forming at least one blind via in the dielectric layer to expose the metal pad in the metal pad region to the first surface; and

and electroplating a conductive blind hole column in the blind hole to form the front fan-out circuit so as to connect the metal pad and the first conductor layer.

10. The method of manufacturing according to claim 7, wherein the method of forming the conductive post further comprises:

forming at least one through hole in the dielectric layer to communicate the first surface and the second surface; and

and electroplating the conductive post in the through hole to connect the first conductive wire layer and the second conductive wire layer.

11. The method of claim 7, further comprising, after the step of removing the adhesion layer:

a protective layer is formed on the first conductive layer to cover the first conductive layer and the first surface of the dielectric layer and expose the sensing area of the sensing chip.

12. The method of claim 7, wherein the attachment layer further covers the metal pad of the sensing chip and the metal pad region between the inner side of the metal pad and the sensing region, and is removed before the step of forming the first conductive line layer to expose the sensing region of the sensing chip, the metal pad and the metal pad region between the inner side of the metal pad and the sensing region, and wherein the method of forming the front fan-out line further comprises the steps of:

and electroplating the exposed metal pad to form the conductive column so as to connect the metal pad and the first conducting wire layer.

13. The method of manufacturing of claim 12, wherein before the step of forming the second conductive line layer, further comprising the step of forming the back fan-out line by:

forming at least one blind hole in the dielectric layer to expose a portion of the backside of the sensing chip to the second surface; and

and electroplating a conductive blind hole column in the blind hole to form the back fan-out circuit so as to connect the back and the second conductor layer.

14. The method of claim 12, further comprising, after the step of forming the first conductive layer:

forming a protective layer on the first conductive layer to cover the first conductive layer, the front fan-out line, the first surface of the dielectric layer, and the metal pad region between the inner side of the metal pad and the sensing region, and exposing the sensing region of the sensing chip.

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a package structure of a sensing device and a method for manufacturing the same.

Background

With the technology changing day by day, various sensing technologies have been widely used in daily life, such as: the sensing device of the mobile phone can be used for face recognition or three-dimensional sensing. The sensing device usually utilizes a sensing chip ("die" or "die") to perform the sensing function of the core; also, in order to minimize the overall volume or overall thickness of the sensing device, the sensing chip may be integrated or embedded in the circuit substrate of the sensing device.

When the sensing chip is integrated or embedded in the circuit substrate, a sensing area (sensor region or sensor area) of the sensing chip must be exposed to facilitate the sensing area to sense an external object. In other words, the conductive layer or the dielectric layer around the sensing chip may not completely cover the sensing chip, and an opening (opening) must be reserved at a corresponding position above the sensing region of the sensing chip to expose at least the sensing region.

Fig. 1-1 is a cross-sectional view of a package structure of a sensing device 1 in the prior art. As shown in fig. 1-1, the sensing device 1 includes a sensing chip 10 having a positive region 11 and a negative region 12, wherein the positive region 11 further includes a sensing region 111 and a connecting pad 112; the sensing region 111 is adjacent to the active surface 101 of the sensing chip 10, and the upper surface of the connecting pad 112 is flush with or recessed in the active surface 101 of the sensing chip 10.

The sensing chip 10 is embedded in the dielectric layer 13 of the circuit substrate, so that only the entire body and the bottom surface of the sensing chip 10 are covered by the dielectric layer 13, and the first surface 131 of the dielectric layer 13 is flush (coplanar) with the active surface 101 of the sensing chip 10, so that the active surface 101 of the sensing chip 10 is not covered by the dielectric layer 13, and the sensing region 111 thereof can be exposed, and thus a junction 133 is formed between the entire body of the sensing chip 10 and the dielectric layer 13.

In addition, the conductive layer 14 is disposed or formed on the first surface 131 (i.e., the upper surface) and the second surface 132 (i.e., the lower surface) of the dielectric layer 13; the conductive layer 14 has an opening 141 at a corresponding position above the sensing region 111 of the sensing chip 10, so as to expose the sensing region 111; thus, one of the conductive layers 14 spans the first surface 131 of the dielectric layer 13 and the active surface 101 of the sensing chip 10, and directly contacts the junction 133 between the dielectric layer 13 and the sensing chip 10.

Fig. 1-2 is a partial enlarged view of the package structure shown in fig. 1-1. Furthermore, as shown in fig. 1-2, since the first surface 131 of the dielectric layer 13 is flush with the active surface 101 of the sensing chip 10, the bonding surface 133 of the dielectric layer 13 and the sensing chip 10 is easily cracked or separated to generate a crack or slit 134 under the effect of stress or thermal expansion and contraction of the dielectric material. Alternatively, during the etching process, the etching solution may penetrate into the joint 133 to erode and form the gap 134.

When there is a gap 134 between the dielectric layer 13 and the sensing chip 10 due to stress or thermal expansion and contraction of the dielectric material or erosion of the etching solution, in the subsequent step of forming the conductive layer 14, the conductive layer 14 directly presses against the gap 134 of the bonding surface 133, so that the conductive material will penetrate into the gap 134 during the process of forming the conductive layer 14 to form an electrical connection path 142. Unfortunately, since the thickness h1 of the positive region 11 of the sensing chip 10 is small (much smaller than the thickness h2 of the negative region 12), the electrical connection path 142 has a small length (larger than h 1) to connect the positive region 11 to the negative region 12, which causes short circuit (leakage), and thus causes malfunction or damage of the sensing chip 10.

In addition, when the joint 133 between the dielectric layer 13 and the sensing chip 10 is cracked or separated by stress or thermal expansion and contraction of the dielectric material, the entire structure of the sensing device 1 is also deformed.

In view of the above-mentioned technical problems in the prior art, it is desirable to provide an improved package structure, which enables a dielectric layer of a sensing device and a sensing chip to be tightly combined, so as to reduce the undesirable defects of short circuit between positive and negative electrode regions of the sensing chip or bending deformation of the sensing device structure.

Disclosure of Invention

In view of the technical problem in the prior art that the joint surface between the sensing chip and the dielectric layer is easily separated or cracked, a primary object of the present invention is to provide a package structure of a sensing device and a method for manufacturing the same.

The technical scheme for solving the problems is realized as follows:

a packaging structure of a sensing device comprises a sensing chip, a dielectric layer, a first conducting wire layer, a second conducting wire layer, at least one conducting post, at least one front fan-out line and at least one back fan-out line. The sensing chip is provided with an action surface and a back surface which are oppositely arranged, and the action surface of the sensing chip is provided with a sensing area and a metal pad area provided with at least one metal pad. The dielectric layer covers the whole body, the back surface and the metal pad region (local action surface) of the sensing chip, and is provided with a first surface and a second surface which are oppositely arranged, and the first surface is higher than the action surface of the sensing chip and exposes the sensing region of the sensing chip. The first and second conductive layers are disposed on the first and second surfaces of the dielectric layer, respectively. The conductive column is arranged in the dielectric layer and connected with the first conducting wire layer and the second conducting wire layer. The fan-out circuit on the front surface is connected with the first lead layer and the metal pad of the sensing chip. The back fan-out line is connected with the second lead layer and the back of the sensing chip.

The metal pad and the metal pad region between the inner side of the metal pad and the sensing region are exposed on the first surface of the dielectric layer, and the metal pad region between the outer side of the metal pad and the edge of the active surface is covered by the dielectric layer.

Wherein, the dielectric layer is also provided with at least one back fan-out line for connecting the back of the sensing chip and the second conductor layer.

Wherein, the first surface of the dielectric layer is further provided with a protective layer to cover the first conducting wire layer and expose the sensing area.

The front fan-out circuit is at least one conductive blind hole column.

The front fan-out circuit is at least one conductive column.

The invention also provides a manufacturing method of the packaging structure of the sensing device, which comprises the following steps: providing a sensing chip having an active surface and a back surface opposite to each other, wherein the active surface is provided with a sensing region and a metal pad region provided with at least one metal pad (wherein the upper surface of the metal pad is flush with or recessed or protruded from the upper surface of the active surface). An adhesive layer is disposed on the active surface of the sensing chip to cover at least the sensing region. The sensing chip is arranged on a carrier plate at the side of the attaching layer, wherein an upper surface of the attaching layer is connected with the carrier plate. A dielectric layer is formed on the carrier plate to cover the whole body, the back surface and a part of the action surface of the sensing chip, wherein the dielectric layer is provided with a first surface and a second surface which are oppositely arranged, and the first surface of the dielectric layer is jointed with the carrier plate and is coplanar with the upper surface of the attaching layer. Removing the carrier plate to expose the first surface of the dielectric layer and the upper surface of the attaching layer. A first conductive line layer is formed on the first surface of the dielectric layer. At least one front fan-out circuit is formed between the first wire layer and the metal pad of the sensing chip to connect the first wire layer and the metal pad. Forming a second conductive line layer on the second surface of the dielectric layer. At least one back fan-out line is formed between the second conductor layer and the back of the sensing chip to connect the second conductor layer and the back of the sensing chip. At least one conductive column is formed between the first conductive layer and the second conductive layer to connect the first conductive layer and the second conductive layer. And removing the adhesive layer to expose at least the sensing region of the sensing chip, wherein the first surface of the dielectric layer is higher than the active surface of the sensing chip.

Before the step of forming the second conductor layer, the method further comprises the following steps of forming a back fan-out circuit: forming at least one blind hole in the dielectric layer to expose a portion of the backside of the sensing chip to the second surface; and electroplating a conductive blind hole column in the blind hole to form the back fan-out circuit so as to connect the back and the second conductor layer.

The method for forming the front fan-out circuit further comprises the following steps: forming at least one blind via in the dielectric layer to expose the metal pad in the metal pad region to the first surface; and electroplating a conductive blind hole column in the blind hole to form the front fan-out circuit so as to connect the metal pad and the first conductor layer.

The method for forming the conductive post further comprises the following steps: forming at least one through hole in the dielectric layer to communicate the first surface and the second surface; and electroplating the conductive post in the through hole to connect the first conductive wire layer and the second conductive wire layer.

Wherein, after the step of removing the attaching layer, the method further comprises the following steps: a protective layer is formed on the first conductive layer to cover the first conductive layer and the first surface of the dielectric layer and expose the sensing area of the sensing chip.

Wherein the attachment layer further covers the metal pad of the sensing chip and the metal pad region between the inner side of the metal pad and the sensing region, and is removed before the step of forming the first conductive line layer to expose the sensing region of the sensing chip, the metal pad and the metal pad region between the inner side of the metal pad and the sensing region, and wherein the method of forming the front fan-out line further comprises the steps of: and electroplating the exposed metal pad to form the conductive column so as to connect the metal pad and the first conducting wire layer.

Before the step of forming the second conductor layer, the method further comprises the following steps of forming the back fan-out line: forming at least one blind hole in the dielectric layer to expose a portion of the backside of the sensing chip to the second surface; and electroplating a conductive blind hole column in the blind hole to form the back fan-out circuit so as to connect the back and the second conductor layer.

Wherein, after the step of forming the first conductive line layer, the method further comprises the following steps: forming a protective layer on the first conductive layer to cover the first conductive layer, the front fan-out line, the first surface of the dielectric layer, and the metal pad region between the inner side of the metal pad and the sensing region, and exposing the sensing region of the sensing chip.

Through the technical scheme, the invention can achieve the main technical effect that the dielectric layer and the sensing chip can be tightly combined, and can overcome the technical problems in the prior art.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

FIG. 1-1: a cross-sectional view of a package structure of a prior art sensing device 1;

FIGS. 1-2: FIG. 1-1 is an enlarged view of a portion of the package structure;

FIGS. 2A to 2J are schematic cross-sectional views illustrating a method for manufacturing a sensing device 2 according to a first embodiment of the invention;

FIGS. 3A to 3H are schematic cross-sectional views illustrating a method for manufacturing a sensing device 4 according to a second embodiment of the invention;

FIG. 4-1: a cross-sectional view of a package structure of a sensing device 2 according to a first embodiment of the invention;

FIG. 4-2: 4-1, a partial enlarged view of the package structure shown in FIG. 1;

FIG. 5-1: a cross-sectional view of a package structure of a sensing device 4 according to a second embodiment of the present invention;

FIG. 5-2: 5-1A partial enlarged view of the package structure shown in FIG. 1.

Description of the reference numerals

1. 2, 4 … sensing device

10. 20 … sensing chip

101. 201 … action surface

11. 21 … positive electrode region

111. 211 … sensing region

112 … connecting pad

12. 22 … negative electrode region

13. 25 … dielectric layer

131. 254 … first surface

132. 255 … second surface

133. 256 … engagement surface

134 … slit

14 … conductive layer

141. 281 … opening

142 … electric connection path

20E … Metal pad

212 … Metal pad area

212a … taping region

212b … molding area

23. 31 … adhesive layer

231 … upper surface

24 … carrier plate

241 … release layer

25 … dielectric layer

251. 253 … blind hole

252 … perforation

257 … side wall

25a, 41 … stacking structure

25c … dielectric layer extension

26 … first conductor layer

261. 262 … part of a first conductor layer

264. 273 … conductive blind hole column

263. 263A … conductive post

27 … second conductor layer

271. 272 … portions of a second wire layer

28 … protective layer

28c … protection layer extensions

h1 … thickness

h2 … thickness

h3 … thickness.

Detailed Description

The technical solution in the embodiments of the present invention is clearly and completely described below with reference to the drawings in the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

Referring to fig. 2A to 2J, cross-sectional views of a manufacturing method of a sensing device 2 according to a first embodiment of the invention are shown. First, as shown in fig. 2A, a sensing chip 20 having a positive region 21 and a negative region 22 is provided. The active surface (upper surface) 201 of the positive electrode region 21 has a sensing region 211 and a metal pad region 212 (or "metal pad region", "metal electrode pad region", or "electrode pad region"). The metal pad area 212 has at least one metal pad 20E, and the upper surface of the metal pad 20E can be flush with or recessed or protruded from the upper surface of the active surface 201.

Next, an adhesive layer 23 (adhesive layer) is attached or disposed on the active surface 201 of the sensor chip 20. The adhesive layer 23 has a thickness h3, which is, for example, in the range from 5 μm to 15 μm. In the first embodiment, the adhesion layer 23 only covers the sensing region 211 of the sensing chip 20, but does not cover the metal pad region 212.

Next, as shown in fig. 2B, the sensing chip 20 together with the attaching layer 23 is flipped in a vertical direction and disposed, placed or attached on the carrier 24 ("carrier"). In other words, the sensing chip 20 is disposed on the carrier 24 with the adhesion layer 23 side, wherein the upper surface 231 of the adhesion layer 23 is bonded to the carrier 24.

The carrier 24 may be made of metal or ceramic, and has a release film or layer 241 on its upper surface. After the sensing chip 20 is disposed on the carrier 24, the adhesive layer 23 is interposed between the sensing chip 20 and the carrier 24, and the upper surface 231 of the adhesive layer 23 is bonded to the carrier 24 (bonded to the release layer 241 of the carrier 24).

Next, as shown in fig. 2C, a molding process (or "filling" or "molding") is performed to form a dielectric layer 25 on the carrier 24. The dielectric layer 25 is made of a molding compound (molding compound), which may be, for example, a phenolic-Based Resin (Novolac-Based Resin), an Epoxy-Based Resin (Epoxy-Based Resin), or a Silicone-Based Resin (Silicone-Based Resin).

The molded and cured dielectric layer 25 has a first surface 254 and a second surface 255 disposed opposite each other; the first surface 254 of the dielectric layer 25 is bonded to the carrier 24, such that the first surface 254 of the dielectric layer 25 is coplanar with the upper surface 231 of the attachment layer 23. The dielectric layer 25 covers the carrier 24 and covers the entire periphery (the adjacent portion is formed as a bonding surface 256), the back surface and the metal pad region 212 of the sensing chip 20, and forms a dielectric layer extension portion 25c to cover the metal pad region 212 of the sensing chip 20, so that the bonding surface 256 is not cracked by the covering effect of the extension portion 25c, and the structural strength can be ensured.

Then, a grinding process (grinding) may be optionally performed to grind the second surface 255 of the dielectric layer 25 flat.

Next, as shown in fig. 2D, laser drilling (laser drill) or other etching processes (e.g., dry etch) are performed to form at least one blind via 251 and at least one through hole 252 in the dielectric layer 25 (fig. 2D illustrates two blind vias 251 and one through hole 252, for example, in other embodiments, other numbers of blind vias 251 and through holes 252 may be formed). The blind hole 251 extends downward to the cathode region 22 of the sensing chip 20 to expose a portion of the second surface 255 of the dielectric layer 25 on the backside of the sensing chip 20. The through hole 252 penetrates through the entire dielectric layer 25 to communicate the first surface 254 and the second surface 255 of the dielectric layer 25 and extend to the release layer 241 of the carrier 24.

Next, as shown in fig. 2E, the carrier plate 24 is removed to separate the carrier plate 24 from the sensing chip 20 and the dielectric layer 25, and the first surface 254 of the dielectric layer 25 is exposed (and the upper surface 231 of the attachment layer 23 is also exposed). For convenience of description, the sensing chip 20, the attaching layer 23 and the dielectric layer 25 after the carrier 24 is removed are collectively referred to as a stacking structure 25 a.

Next, as shown in fig. 2F, the stacked structure 25a is turned over in the vertical direction. In the stacked structure 25a, the upper surface 231 of the attachment layer 23 is coplanar with the first surface 254 of the dielectric layer 25.

Next, as shown in fig. 2G, a laser drilling process is performed on the dielectric layer 25 to form at least one blind via 253 at a corresponding position above the metal pad region 212 of the sensor chip 20. In other words, the blind via 253 is formed on the dielectric layer extension 25c of the metal pad region 212 covered by the dielectric layer 25; the blind via 253 extends down to the metal pad region 212 to expose the metal pad 20E of the metal pad region 212 on the first surface 254 of the dielectric layer 25.

Next, as shown in fig. 2H, an electroplating process is performed on the first surface 254 and the second surface 255 of the dielectric layer 25 to form a first conductive line layer 26 and a second conductive line layer 27, respectively; both of which are patterned conductive layers with pre-programmed circuit patterns. In the cross-sectional position shown in fig. 2H, the first conductive line layer 26 includes at least two separated portions 261 and 262, and the second conductive line layer 27 includes at least two separated portions 271 and 272 (in other implementations, or in other cross-sectional positions, the first conductive line layer 26 and the second conductive line layer 27 may include other numbers of separated portions). In addition, neither of the portions 261 and 262 of the first conductive trace 26 covers the adhesive layer 23.

At the same time, at least one front fan-out ("fan-out") line is formed between the first conductive line layer 26 and the metal pad 20E of the sensing chip 20, and at least one back fan-out line is formed between the second conductive line layer 27 and the back of the sensing chip 20.

Further, an electroplating process is performed in the blind via 253 to form the conductive blind via pillar 264. The conductive blind via post 264 is used as a fan-out circuit on the front surface of the positive region 21 of the sensing chip 20, which connects the metal pad 20E and the first conductive trace layer 26, so that a portion 261 of the first conductive trace layer 26 will not contact the bonding surface 256 of the dielectric layer 25 and the sensing chip 20 by the support and isolation of the extension portion 25c of the dielectric layer 25, and thus, the problems of diffusion plating and electrical short circuit will not occur. On the other hand, a plating process is also performed in the blind via 251 to form a conductive blind via stud 273. The conductive blind via posts 273 serve as the back fan-out lines of the negative region 22 of the sensing chip 20, connecting the back of the sensing chip 20 and the second conductive line layer 27. In addition, the dielectric layer extension portion 25c only exposes a portion of the metal pad 20E, in other words, the junction surface of the metal pad 20E and the boundary of the positive electrode region 21 is also covered by the dielectric layer 25, so that the problems of diffusion and electrical short circuit do not occur.

In addition, an electroplating process is performed in the through hole 252 to form a conductive pillar 263. The conductive posts 263 serve as a connecting line between the upper and lower conductive layers to connect the second conductive layer 27 and the first conductive layer 26.

Next, as shown in fig. 2I, a protection layer 28 is formed on the first conductive line layer 26; the protective layer 28 also covers a portion of the first surface 254 of the dielectric layer 25. The material of the passivation layer 28 may be, for example, a polymer material or a phosphorus-containing material; the above materials are soft materials, so the protection layer 28 has a larger toughness and is not easy to break. In addition, the passivation layer 28 has an opening 281 at a corresponding position above the attachment layer 23 to expose the attachment layer 23, thereby facilitating the removal of the attachment layer 23 in the subsequent steps.

Next, as shown in fig. 2J, the adhesive layer 23 is removed, so that the sensing region 211 of the sensing chip 20 is exposed through the opening 281 of the protection layer 28. After the adhesive layer 23 is removed, the package structure of the sensing device 2 of the first embodiment is obtained.

Before removing the adhesion layer 23, the upper surface 231 of the adhesion layer 23 is flush with the first surface 254 of the dielectric layer 25 (as shown in fig. 2I); also, the adhesive layer 23 has a thickness h 3. Therefore, after removing the attaching layer 23, the first surface 254 of the dielectric layer 25 is higher than the active surface 201 of the sensor chip 20 by a height difference equal to the thickness h3 of the attaching layer 23 (as shown in fig. 2J).

The manufacturing method of the sensing device of the present invention is not limited to the first embodiment; the manufacturing method of the second embodiment will be described below.

Fig. 3A to 3H are schematic cross-sectional views illustrating a manufacturing method of a sensing device 4 according to a second embodiment of the invention. The manufacturing method of this embodiment is substantially similar to that of the first embodiment, and the main differences are: the fan-out lines on the front side of the metal pads 20E electrically connected to the sensing chip 20 are formed.

First, the steps shown in fig. 3A to 3C are similar to the corresponding steps shown in fig. 2A to 2C of the first embodiment, and the difference lies in: as shown in fig. 3A, the attachment layer 31 of the present embodiment covers not only the sensing region 211 of the sensing chip 20, but also a part of the metal pad region 212. That is, the adhesion layer 31 covers the metal pad 20E and a portion of the metal pad region 212 between the inner side of the metal pad 20E and the sensing region (hereinafter referred to as the molding region 212 b), and exposes a portion between the outer side of the metal pad 20E and the edge of the upper surface of the active surface 201 (hereinafter referred to as the edge-covering region 212 a).

Specifically, as shown in fig. 3A, the width of the adhesion layer 31 of the present embodiment is slightly smaller than that of the sensing chip 20, so that the edge-covered region 212a of the metal pad region 212 (i.e., the portion between the outer side of the metal pad 20E and the edge of the upper surface of the active surface 201) can still be exposed at one end of the adhesion layer 31. Therefore, as shown in fig. 3C, after the dielectric layer 25 is formed, the extension portion 25C of the dielectric layer 25 can still cover the edge-covered region 212a of the metal pad region 212 of the sensing chip 20, so that the bonding surface 256 of the dielectric layer 25 and the sensing chip 20 can be prevented from generating cracks by the covering effect of the extension portion 25C, and the structural strength can be ensured.

Next, the steps shown in fig. 3D to 3F are similar to the corresponding steps shown in fig. 2D to 2F of the first embodiment, with the difference that: as shown in fig. 3E, in the embodiment, the attaching layer 31 is removed at the same time (or immediately after) the carrier plate 24 is removed, so that the sensing region 211 and the metal pad region 212 of the sensing chip 20 are exposed (for convenience of description, the sensing chip 20 and the dielectric layer 25 after the carrier plate 24 is removed are collectively referred to as a stacked structure 41). Therefore, as shown in fig. 3F, in the vertically flipped stacked structure 41, the sensing region 211, the metal pad 20E and the molding region 212b (i.e. a portion of the metal pad region 212 between the metal pad 20E and the sensing region 211) are exposed, so that in the subsequent step, a front fan-out circuit is formed to electrically connect to the exposed metal pad 20E.

Next, the steps shown in fig. 3G to 3H are similar to the corresponding steps shown in fig. 2H to 2I of the first embodiment, with the difference that: as shown in fig. 3G, in the present embodiment, the conductive posts 263A are formed by extending from the metal pad 20E to a portion 261 of the first conductive line layer 26 along the sidewall 257 of the extension portion 25c of the dielectric layer 25 directly upward to serve as a front fan-out line of the sensing chip 20, so that the portion 261 of the first conductive line layer 26 does not contact the bonding surface 256 by the supporting and blocking effects of the extension portion 25c, and therefore, the problems of plating bleeding and electrical short circuit do not occur. In addition, as shown in fig. 3H, while the protection layer 28 is formed, the extending portion 28c thereof also extends downward along the conductive pillar 263A to the molding region 212b of the metal pad region 212, and exposes the sensing region 211 of the sensing chip 20. After the protective layer 28 is formed, the package structure of the sensing device 4 of the second embodiment is obtained.

What has been described above are the manufacturing methods of the sensing devices 2, 4 of the first and second embodiments of the present invention; the structural features of the package structure of each of the sensing devices 2 and 4 will be described below.

Fig. 4-1 is a cross-sectional view of a package structure of a sensing device 2 according to a first embodiment of the invention. As shown in fig. 4-1, the sensing device 2 includes a sensing chip 20, a dielectric layer 25, a first conductive layer 26, a second conductive layer 27, at least one conductive pillar 263, a plurality of conductive blind via pillars 264 and 273, and a protection layer 28.

The positive region 21 of the sensing chip 20 is located above the negative region 22, and the active surface 201 of the positive region 21 has a sensing region 211 and a metal pad region 212. The sensing region 211 is used for sensing an external object, and the metal pad 20E disposed in the metal pad region 212 is used as a signal transmission interface of the sensing chip 20, and the upper surface of the metal pad 20E can be flush with or recessed into or protruded from the upper surface of the active surface 201.

The dielectric layer 25 is disposed or formed around the sensing chip 20, and completely covers the entire body and the back surface of the sensing chip 20 and a portion of the active surface 201 of the sensing chip 20. More specifically, the first surface 254 of the dielectric layer 25 is higher than the active surface 201 of the sensing chip 20 by a height difference h3 (h 3 is, for example, in the range of 5 μm to 15 μm). As shown in the enlarged partial view of fig. 4-2, the dielectric layer 25 has an extended portion 25c which is higher than the active surface 201 of the sensing chip 20; the extension portion 25c of the dielectric layer 25 extends to cover the metal pad region 212 of the sensing chip 20 and covers the conductive via pillar 264.

Since the extension portion 25c of the dielectric layer 25 is higher than the active surface 201 of the sensing chip 20 and covers the metal pad region 212, the dielectric layer 25 and the sensing chip 20 can be tightly bonded by the covering effect of the extension portion 25c, and the whole packaging structure of the sensing device 2 is not subjected to bending deformation except that the bonding surface 256 of the two is not separated due to stress or thermal expansion and contraction of the dielectric material.

In addition, since the bonding surface 256 does not have cracks due to stress or thermal expansion and contraction of the dielectric material, and the supporting and blocking effects of the extension portion 25c of the dielectric layer 25 can prevent the first conductive line layer 26 from contacting the bonding surface 256, the conductive material of the first conductive line layer 26 does not penetrate into the bonding surface 256 during the formation of the first conductive line layer, thereby preventing the risk of short circuit between the positive electrode region 21 and the negative electrode region 22 of the sensor chip 20. The above is one of the main technical effects of the present invention.

The first conductive line layer 26 of the sensing device 2 is disposed or formed on the first surface 254 of the dielectric layer 25, which is a patterned conductive layer having a pre-programmed circuit pattern and includes at least two portions 261 and 262 separated from each other. Functionally, the first conductive layer 26 serves as a front circuit of the sensing device 2 for transmitting signals of the positive region 21 of the sensing chip 20. In addition, neither of the two portions 261 and 262 of the first conductive line layer 26 covers the sensing region 211 of the sensing chip 20.

Similarly, the second conductive line layer 27 is disposed or formed on the second surface 255 of the dielectric layer 25, which is also a patterned conductive layer, and includes at least two portions 271 and 272 separated from each other. Functionally, the second conductive layer 27 serves as a backside circuit of the sensing device 2 for transmitting signals of the negative region 22 of the sensing chip 20.

The conductive blind via pillar 264 is disposed or formed between a portion 261 of the first wire layer 26 and the metal pad 20E of the sensing chip 20. Therefore, the conductive blind via posts 264 serve as fan-out lines on the front surface of the positive region 21 of the sensing chip 20 to transmit signals of the positive region 21 of the sensing chip 20 to the front surface lines (i.e., the first conductive traces 26). In the present embodiment, as shown in the enlarged view of fig. 4-2, the conductive via pillar 264 is covered by the extension portion 25c of the dielectric layer 25.

On the other hand, the conductive blind via pillar 273 is disposed or formed between a portion 272 of the second conductive trace layer 27 and the negative electrode region 22 on the back surface of the sensor chip 20. Therefore, the conductive blind via posts 273 serve as a back fan-out circuit for the negative electrode region 22 of the sensing chip 20 to transmit the signal of the negative electrode region 22 of the sensing chip 20 to the back circuit (i.e., the second conductive trace 27).

The conductive pillar 263 is disposed or formed between the first conductive wire layer 26 and the second conductive wire layer 27, and serves as a signal transmission path between the front circuit and the back circuit of the sensing device 2, so as to transmit signals of the first conductive wire layer 26 and the second conductive wire layer 27.

Furthermore, the passivation layer 28 is disposed or formed on the first conductive line layer 26 and the portion of the first surface 254 of the dielectric layer 25, which completely covers the portions 261 and 262 of the first conductive line layer 26 and also covers the extended portion 25c of the dielectric layer adjacent to the sensing region 211 (as shown in the enlarged view of fig. 4-2). The passivation layer 28 has an opening 281 at a corresponding position above the sensing region 211 of the sensing chip 20, so as to expose the sensing region 211. The protection layer 28 is made of a soft material and has high toughness; therefore, the sensor device 2 is not easily broken by stress even in the case of an ultra-thin thickness.

Fig. 5-1 is a cross-sectional view of a package structure of a sensing device 4 according to a second embodiment of the invention. As shown in fig. 5-1, the arrangement position, material and function of each material layer or element of the sensing device 4 are completely the same as or similar to those of the corresponding material layer or corresponding element of the sensing device 2 of the first embodiment. The conductive posts 263A correspond to the conductive blind via posts 264 of the first embodiment.

The difference between the sensing device 2 of the present embodiment and the first embodiment is: as shown in the enlarged view of fig. 5-2, the extension portion 25c of the dielectric layer 25 covers the edge-covered region 212a of the metal pad region 212 (i.e., the portion between the outer side of the metal pad 20E and the edge of the active surface 201), and the extension portion 28c of the protection layer 28 covers the metal pad region 212 and the molding region 212b (i.e., the portion between the inner side of the metal pad 20E and the sensing region 211).

Since the extension portion 25c of the dielectric layer 25 and the extension portion 28c of the protection layer 28 are both higher than the active surface 201 of the sensing chip 20, and both (the extension portion 25c and the extension portion 28 c) cover the metal pad region 212, so that the dielectric layer 25 and the protection layer 28 provide a more complete covering for the sensing chip 20, and by the supporting and blocking effect of the extension portion 25c of the dielectric layer 25, the first conductive wire layer 26 is prevented from contacting the bonding surface 256, so that the dielectric layer 25 and the sensing chip 20 can be tightly bonded, the bonding surface 256 of the dielectric layer 25 and the sensing chip 20 is prevented from being separated or cracked due to stress or thermal expansion and contraction of the dielectric material, and the conductive material of the first conductive wire layer 26 can not penetrate into the bonding surface 256 during the formation of the first conductive wire layer 26, thereby preventing the risk of short circuit between the positive electrode region 21 and the negative electrode region 22 of the sensing chip 20.

Another difference between the sensing device 2 of the present embodiment and the first embodiment is that: by the supporting and blocking effect of the extension portion 25c of the dielectric layer 25, the conductive pillar 263A is formed by extending vertically and upwardly from the metal pad 20E along the sidewall 257 of the extension portion 25c, and is connected to the first conductive line layer 26, so that the cross-sectional shape of the conductive pillar 263A is a straight column; which is different from the tapered shape of the conductive blind via pillar 264 formed by filling the blind via 253 in the first embodiment.

Yet another difference is that: one side (right side) of the conductive pillar 263A of the present embodiment is directly covered by the extending portion 28c of the passivation layer 28, except that (referring to fig. 4-2), both sides of the conductive via pillar 264 of the first embodiment are directly covered by the extending portion 25c of the dielectric layer 25, but are not directly covered by the passivation layer 28.

The foregoing description is only of the preferred embodiments of the present invention, and it should be understood that the described embodiments are only a few, and not all, of the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.