阅读说明：本技术 具有自由浮动封装概念的功率半导体装置 (Power semiconductor device with free floating package concept ) 是由 J·多布辛斯卡 J·伏贝基 D·吉隆 T·M·O·威克斯特罗姆 于 2019-10-10 设计创作，主要内容包括：提供了一种功率半导体装置(100),其包括半导体晶片(1),该半导体晶片具有在横向上围绕至少一个结(15)的结终端。保护层(18)至少在结终端的区域(TR)中覆盖半导体晶片(1)的横向侧(13)和覆盖第二主侧(12)。第一金属盘(2)被布置并覆盖半导体晶片(1)的第一主侧(11)上,其中,第一主侧(11)与第二主侧(12)相反。第一金属盘(2)具有与半导体晶片(1)的横向尺寸(d-W)相同或更大的横向尺寸(d-2),以覆盖半导体晶片(1)的第一主侧(11)。第一金属盘(11)与半导体晶片(1)之间的界面是自由浮置界面。(A power semiconductor device (100) is provided that includes a semiconductor wafer (1) having a junction termination laterally surrounding at least one junction (15). The protective layer (18) covers the semiconductor at least in The Region (TR) of the junction terminationA lateral side (13) of the wafer (1) and an overlying second main side (12). The first metal disc (2) is arranged and covers a first main side (11) of the semiconductor wafer (1), wherein the first main side (11) is opposite to the second main side (12). The first metal plate (2) has a lateral dimension (d) corresponding to the semiconductor wafer (1) W ) Same or larger transverse dimension (d) 2 ) For covering the first main side (11) of the semiconductor wafer (1). The interface between the first metal plate (11) and the semiconductor wafer (1) is a free floating interface.)

1. A power semiconductor device, comprising:

a semiconductor wafer (1) having a first main side (11), a second main side (12) opposite to the first main side (11), a lateral side (13) connecting the first main side (11) and the second main side (12), at least one junction (15) and a junction termination laterally surrounding the at least one junction (15),

a protective layer (18; 28; 38; 48; 58) covering a lateral side (13) of the semiconductor wafer (1) and covering the second main side (12) at least in The Region (TR) of the junction termination,

a first metal disc (2; 22; 32) having a transverse dimension (d)₂；d₂'；d₂") having a lateral dimension equal to or greater than a lateral dimension (d) of the semiconductor wafer (1)_w) Wherein the first metal disc (2; 22; 32) arranged on the first main side (11) to cover the first main side (11) of the semiconductor wafer (1),

wherein the first metal disc (2; 22; 32) is a molybdenum disc or a tungsten disc,

wherein the interface between the first metal plate (2; 22; 32) and the semiconductor wafer (1) is a free floating interface, and

wherein a metal layer (30) is sandwiched between the first metal disc (2; 22; 32) and the semiconductor wafer (1), the metal layer (30) having a melting point below 150 ℃, such as below 100 ℃.

2. The power semiconductor device according to claim 1, wherein the material of the protective layer (18; 28; 38; 48; 58) is a thermosetting polymer material.

3. The power semiconductor device according to claim 1 or 2, wherein the material of the protective layer (18; 28; 38; 48; 58) is an epoxy resin or a hybrid epoxy imide composite polymer.

4. Power semiconductor device according to claim 1, wherein the protective layer (18; 28; 38; 48; 58) is made of rubber, for example silicone rubber.

5. Power semiconductor device according to any of the preceding claims, comprising a passivation layer (17) covering the second main side (12) at least in the region of the junction termination, wherein the protection layer (18; 28; 38; 48; 58) hermetically seals the passivation layer (17).

6. Power semiconductor device according to any of the preceding claims, wherein the first metal disc (2) is fixed to the semiconductor wafer (1) by the protective layer (18; 28; 38; 48; 58) which is fixed to the semiconductor wafer (1) and to the first metal disc (2; 22; 32).

7. Power semiconductor device according to any of the preceding claims, wherein the protective layer (18; 28; 38; 48; 58) seals the interface between the semiconductor wafer (1) and the first metal pad (2; 22; 32) with respect to the atmosphere surrounding the power semiconductor device.

8. The power semiconductor device according to any one of the preceding claims, comprising a second metal pad (3) arranged on a second main side (12) of the semiconductor die (1), wherein an interface between the second metal pad (3) and the semiconductor die (1) is a free floating interface.

9. The power semiconductor device according to claim 8, wherein the second metal disc (3) is a molybdenum disc, a tungsten disc or a silver disc.

10. A power semiconductor device according to claim 8 or 9, wherein a second metal layer is sandwiched between the second metal disc (3) and the semiconductor wafer (1), the second metal layer having a melting point below 150 ℃, e.g. below 100 ℃.

11. The power semiconductor device according to any one of the preceding claims, wherein the metal layer (30) is a layer made of any one of gallium (Ga), indium (In), cesium (Cs), rubidium (Rb) and their alloys, a layer made of an alloy of tin (Sn), bismuth (Bi), lead (Pb) and cadmium (Cd), or a layer made of any alloy of aluminum (Al), gallium (Ga), indium (In), thallium (Tl), or a layer made of a eutectic alloy based on gallium (Ga), which remains liquid at room temperature, such as a eutectic alloy of GaIn, GaInSn and GaInSn, or mixtures and alloys thereof.

12. Power semiconductor device according to any of the preceding claims, wherein the thickness of the metal layer (30) is in the range of 0.1 to 500 μ ι η or in the range of 1 to 100 μ ι η.

13. Method for manufacturing a power semiconductor device according to any of the preceding claims, wherein the protective layer (18; 28; 38; 48; 58) is formed by transfer molding.

Technical Field

The invention relates to a power semiconductor device comprising a semiconductor wafer and a first metal disk arranged on a first main side of the semiconductor wafer, wherein an interface between the first metal disk and the semiconductor wafer is free floating, and to a method for manufacturing such a power semiconductor device.

Background

Known high power semiconductor devices have junctions (junctions) arranged in the active region of the semiconductor wafer. These power semiconductor devices require an efficient junction termination in order to avoid electric fields collecting at the edges of the main contacts, which may cause the device to break down at a relatively low breakdown voltage VBR. For silicon-based power semiconductor devices, known junction termination techniques include single-sided single negative bevel, single positive bevel, double positive bevel, a combination of positive and negative bevels, or planar junction termination (e.g., Junction Termination Extension (JTE)), Variations of Lateral Doping (VLD) with and without field plate extension, and floating field ring termination (FFR). A passivation layer made of an insulating material such as silicon oxide, silicon nitride, or diamond-like carbon (DLC) is formed in the peripheral edge on the semiconductor wafer for surface passivation and electrical insulation of the junction termination. In addition to a relatively thin passivation layer made of silicon oxide, silicon nitride or diamond-like carbon (DLC) or any other suitable inorganic material, a silicone rubber is arranged to cover the edge of the semiconductor wafer and to cover the main contacts, so that the distance between the top and bottom electrodes (creepage distance) is extended and ionization (sparking) of the atmosphere or surface materials inside the housing is avoided.

A common packaging technique for high power semiconductor devices is press-fit packaging, in which a semiconductor wafer is clamped under pressure between two copper pole pieces to obtain proper thermal and electrical contact between the semiconductor wafer and the copper pole pieces which serve as external electrodes. Typically, the applied pressure is at 10N/mm²And 20N/mm²In the meantime. Heat will be generated during operation of the high power semiconductor device resulting in operating temperatures of up to 180 c or even higher in a short period of time. The copper pole piece cannot be directly attached to the semiconductor wafer due to the difference between the coefficients of thermal expansion of the semiconductor wafer and the copper pole piece. Molybdenum has a coefficient of thermal expansion close to that of silicon and has a high hardness. Thus, molybdenum disks sandwiched between two copper pole pieces and the semiconductor wafer, respectively, are used to compensate for the difference between the thermal expansion coefficient of the semiconductor wafer and the thermal expansion coefficient of the copper pole pieces, respectively. In use, a press-pack comprising a semiconductor wafer, molybdenum disk and copper pole pieces is inserted between the coolers to remove heat generated by the semiconductor wafer during operation.

To obtain good thermal and electrical contact between the semiconductor wafer and the molybdenum disk, it is common practice to bond the semiconductor wafer to the molybdenum disk by soldering, using nano-silver or nano-copper decals or foils, by Low Temperature Bonding (LTB) and nano-LTB, or by brazing. Similarly, the molybdenum disks are firmly bonded to the semiconductor wafer by the LTB process, minimizing bowing of the semiconductor wafer when uneven pressure is applied to both sides of the semiconductor wafer in a press-fit, such as is the case when different sized molybdenum disks are used for the top and bottom sides of the device. If the molybdenum disks were not bonded to the semiconductor wafer, the semiconductor wafer would be susceptible to cracking when sandwiched between molybdenum disks of different sizes under pressure in a press fit. On the other hand, any bonding, brazing or soldering process poses the risk of the wafer bending or deforming.

In the publications "Reduction of thermo-mechanical Stress by using Low Temperature Joining Technique" of silicon wafers to molybdenum disks by using Low Temperature Joining Technique, the publication of s.klaka and r.sittig at davos, switzerland, held, 5-6 months, 1994, a Low Temperature Joining Technique, a silicon wafer is discussed, which reduces thermo-mechanical Stress between joined materials. The LTJ technique is based on pressure sintering of silver powder.

A publication, "Housing leas High Voltage Fast Recovery Diode" (IP.com proportional Technical Disclosure, IP.com Number: IPCOM000247713D, published 29/9/2016) from Jan Vobecky et al, is a non-quick Recovery Diode Housing (HL-FRD) in which the rubber protection of the junction termination is replaced with a molded composite polymer that serves as a hermetic protection for the surface passivation of diamond-like carbon (DLC). In this prior art, a semiconductor wafer is sandwiched between two molybdenum disks having different diameters. A larger molybdenum disk is bonded to the back side of the semiconductor wafer. However, bonding the molybdenum pads to the semiconductor wafer involves the risk of generating conductive particles on the wafer in the junction termination region and increases the manufacturing cost.

DE 2039806 a1 discloses a semiconductor power device in which a semiconductor wafer is clamped between two molybdenum disks, wherein the molybdenum disks are not bonded to the wafer. It is pointed out in this prior art document that the two molybdenum discs must have the same dimensions in order to avoid cracking of the semiconductor wafer due to uneven pressure application. In DE 2039806 a1, the diameter of both molybdenum disks is smaller than the diameter of the semiconductor wafer. This results in a relatively poor removal of heat generated in the circumferential edge region of the wafer which is not in contact with the molybdenum disk.

A thyristor is known from DE 19627426 a1, which thyristor comprises a semiconductor wafer arranged in a hermetically sealed housing, wherein the housing comprises two parallel disk-shaped electrodes. The semiconductor wafer was disposed between two molybdenum disks without bonding the molybdenum disks to the semiconductor wafer. The stack of molybdenum disks and wafers is held between the electrodes by pressure. The two molybdenum discs have the same diameter and are both smaller than the diameter of the wafer. With the prior art described above, this results in a relatively poor removal of heat generated during operation of the device, in particular in the circumferential edge region of the wafer which is not in contact with the molybdenum disk.

A press fit is known from US 5,489,802 a, in which a molybdenum disc is glued to a semiconductor wafer by means of silicone rubber. To prevent silicone rubber from entering the gap between the molybdenum disk and the wafer, an O-ring is disposed between the wafer and the molybdenum disk along the circumferential edge of the wafer. Therefore, in this conventional technique, since heat cannot be efficiently removed from the peripheral edge region of the semiconductor wafer, heat dissipation is also poor.

From US 2008/296774 a1 a thyristor device is known, which comprises: a semiconductor element having opposing first and second contact surfaces, compensation elements 40a and 40b, and a silicon passivation layer covering the edges of the semiconductor element and the sides of the compensation elements.

From US 2018/090401 a1 a semiconductor device is known, which comprises a wafer sandwiched between two electrodes. The molybdenum layer is interposed between the lower electrode and the wafer. The molybdenum layer is sandwiched between the wafer and the lower electrode. The rubber ring covers the edge of the wafer and the side of the wafer.

According to US 4129881 a, a power device includes a wafer, a molybdenum or tungsten reinforcing disk, a lower electrode and an upper electrode. The wafer is sandwiched between a lower electrode and an upper electrode. A molybdenum or tungsten stiffener is brazed to the lower surface of the wafer and disposed between the lower terminal electrode and the wafer. A metal layer, which is liquid during operation of the device, is interposed between the lower terminal electrode and the reinforcing disc.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a power semiconductor device in which heat dissipation is effective while wafer breakage can be avoided and the risk of device failure due to conductive particles on the junction terminals of the semiconductor wafer can be reduced.

This object is achieved by a power semiconductor device according to claim 1. Further developments of the invention are given in the dependent claims.

In the present invention, the lateral dimension of the first metal pad arranged on the first main side of the semiconductor wafer is equal to or larger than the lateral dimension of the semiconductor wafer to cover the first main side of the semiconductor wafer. Due to the relatively large lateral dimension of the first metal disk (the lateral dimension of the first metal plate being equal to or greater than the lateral dimension of the semiconductor wafer), wafer breakage during pressure application in press-fitting can be unexpectedly avoided even if the semiconductor wafer is sandwiched under pressure between the first metal disk and the second metal disk, which have lateral dimensions smaller than the lateral dimensions of the semiconductor wafer. Furthermore, the lateral dimension of the first metal disc is equal to or greater than the lateral dimension of the semiconductor wafer, so that an effective removal of heat from the semiconductor wafer, in particular in the peripheral edge region of the semiconductor wafer, is ensured.

In the power semiconductor device of the invention, the interface between the first metal disc and the semiconductor die is a free floating interface, i.e. the first metal disc is neither bonded nor brazed or soldered onto the first main side of the semiconductor die, so that the metal disc can slide along the first main side when expanding laterally due to thermal rise during operation of the power semiconductor device. This can reduce the compressive or tensile stress generated in the first metal plate and the semiconductor wafer during temperature changes. Wafer bowing or deformation may be avoided by avoiding any bonding, brazing or soldering processes. Furthermore, the risk of particle generation on the semiconductor wafer in the junction termination region can be avoided by avoiding any bonding, brazing or soldering process. Thus, the risk of device failure due to conductive particles on the junction terminals of the semiconductor wafer can be reduced.

In the present invention, the first metal disk is a molybdenum disk or a tungsten disk. The coefficients of thermal expansion of molybdenum and tungsten are close to those of common semiconductor materials such as silicon or silicon carbide.

In the present invention, a metal layer is sandwiched between the first metal plate and the semiconductor wafer, the metal layer having a melting point below 150 ℃, illustratively below 125 ℃, illustratively below 100 ℃. Such a metal layer improves the thermal and electrical coupling between the semiconductor wafer and the first metal pad (i.e., it improves the interface conductivity), thereby reducing conduction losses and improving heat removal during device operation.

In an exemplary embodiment, the material of the protective layer is a thermoset polymer material. Thermosetting polymers can be shaped by transfer molding. An advantage of transfer molding compared to other molding techniques is that the viscosity of the thermosetting polymer is relatively high during transfer molding, so that the thermosetting polymer does not easily enter into the gap between the first main side of the semiconductor wafer and the first metal disc. Other advantages of transfer molding are the relatively low cost of the molding equipment, the relatively short cycle time, and the relatively low cost of tool maintenance compared to other molding techniques such as injection molding.

In an exemplary embodiment, the material of the protective layer is an epoxy resin or a hybrid epoxy imide composite polymer. This material has low shrinkage, low water absorption, good adhesion to diamond-like carbon (DLC), nickel (Ni), ruthenium (Ru), silicon (Si) surfaces, low elastic modulus, low coefficient of thermal expansion, which is close to that of silicon and molybdenum, resulting in low built-in stress after the manufacturing process. These characteristics enable the protective layer to hermetically seal and protect the wafer surface at the termination.

In another exemplary embodiment, the protective layer is made of rubber, such as silicone rubber. Rubbers, in particular silicone rubbers, have a good electrical insulation effect and are resistant to high operating temperatures.

In an exemplary embodiment, the power semiconductor device includes a passivation layer formed on the second main side to cover the junction terminal, wherein the protection layer hermetically seals the passivation layer.

In an exemplary embodiment, the first metal disk is secured to the semiconductor wafer by a protective layer secured to the semiconductor wafer and the first metal disk. The first metal plate is secured to the semiconductor wafer by a protective layer which is secured to the semiconductor wafer and the first metal plate. In an exemplary embodiment, the protective layer seals an interface between the semiconductor wafer and the first metal pad with respect to an atmosphere surrounding the power semiconductor device. Illustratively, the protective layer is fixed or glued to a side surface of the first metal disc and/or a circumferential edge portion of an upper surface of the first metal disc, wherein the upper surface of the first metal disc faces the semiconductor wafer.

In an exemplary embodiment, the power semiconductor device comprises a second metal disc arranged on the second main side of the semiconductor die, wherein the interface between the second metal disc and the semiconductor die is a free floating interface, i.e. the second metal disc is not bonded, nor brazed or soldered to the second main side of the semiconductor die, such that the second metal disc can slide along the second main side when expanding laterally due to heating during operation of the device. As discussed above with respect to the free floating interface between the first metal disk and the semiconductor wafer, the free floating interface between the second metal disk and the semiconductor wafer may also reduce compressive or tensile stresses generated in the second metal disk and the semiconductor wafer during temperature changes. By avoiding any bonding, brazing or soldering processes, wafer bowing or wafer deformation may be avoided. In addition, by avoiding any bonding, brazing or soldering process, the risk of particle generation on the semiconductor wafer in the junction termination region can be avoided and manufacturing costs reduced. Therefore, the risk of device failure due to conductive particles on the junction terminals of the semiconductor wafer can be further reduced.

In an exemplary embodiment, the second metal disk is a molybdenum disk or a tungsten disk or a silver disk. The coefficients of thermal expansion of molybdenum and tungsten are close to those of conventional semiconductor materials, such as silicon or silicon carbide, while silver has a relatively high electrical conductivity.

In an exemplary embodiment, the metal layer may be a eutectic alloy layer based on gallium (Ga) that remains in a liquid state at room temperature (e.g., 20 ℃) and during device operation, such as a eutectic alloy of GaIn, GaInSn, and GaInZn. The metal layer may also be a layer of any of gallium (Ga), indium (In), cesium (Cs), rubidium (Rb) and alloys thereof, and similarly, the metal layer may be any alloy layer of tin (Sn), bismuth (Bi), lead (Pb) and cadmium (Cd) or may be any alloy layer of aluminum (Al), gallium (Ga), indium (In), thallium (Tl) or mixtures of these and alloys thereof.

In an exemplary embodiment, the thickness of the metal layer is in the range of 0.1 μm to 500 μm, for example, in the range of 1 μm to 100 μm.

In an exemplary embodiment of the method for manufacturing a power semiconductor device according to the present invention, the protective layer may be formed, for example, by transfer molding.

Drawings

The detailed embodiments will be explained below with reference to the accompanying drawings, in which:

fig. 1 shows a cross-sectional view of a power semiconductor device according to a first embodiment;

fig. 2 shows a cross-sectional view of a power semiconductor device according to a second embodiment;

fig. 3 shows a cross-sectional view of a power semiconductor device according to a third embodiment;

fig. 4 shows a cross-sectional view of a power semiconductor device according to a fourth embodiment;

fig. 5 shows a cross-sectional view of a power semiconductor device according to a fifth embodiment; and

fig. 6 shows a cross section of a power semiconductor device according to a sixth embodiment.

The reference symbols used in the drawings and their meanings are summarized in the list of reference symbols. Generally, similar elements have the same reference numerals throughout the specification. The described embodiments are to be considered in all respects only as illustrative and not restrictive. It is noted that only the second embodiment is described as having all the features of the claimed invention, while other embodiments do not describe all the features of the invention, but only describe various aspects of the claimed invention. In particular, the first, third to sixth embodiments describe the case where the metal layer 30 is not present.

Detailed Description

Hereinafter, a power semiconductor device 100 according to a first embodiment is described with reference to fig. 1. The power semiconductor device 100 according to the first embodiment is a press-fitting type device including a semiconductor wafer 1, a first metal disk 2, a second metal disk 3, a first pole piece 4, a second pole piece 5, and a case 6. The semiconductor wafer 1 has a first main side 11, a second main side 12 opposite the first main side 11, and a lateral side 13 connecting the first main side 11 and the second main side 12.

In an orthogonal projection of a plane parallel to the first main side 11, the semiconductor wafer 1 has an active region AR located in a central region of the semiconductor wafer 1 and a junction termination region TR extending along a circumferential edge of the semiconductor wafer 1 to laterally surround the active region AR. Wherein any direction parallel to the first main side is a lateral direction. At least one junction 15 is formed in the active region AR of the semiconductor wafer 1. Depending on the type of power device implemented by the semiconductor wafer, the at least one junction 15 may comprise a pn-junction and/or a schottky-junction. In the termination region TR, a junction termination is formed at the second main side 12 of the semiconductor wafer 1. The semiconductor wafer may be made of any semiconductor material suitable for a power semiconductor device, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like.

In the first embodiment shown in FIG. 1, the junction termination is illustratively shown as a single sided single negative bevel. A passivation layer 17 is formed in the circumferential edge on the semiconductor wafer 1 for surface passivation of the junction termination region of the semiconductor wafer, said passivation layer 17 being exemplarily made of an insulating material, such as silicon oxide, silicon nitride, aluminum oxide, polyimide or a semi-insulating material like diamond-like carbon (DLC). In addition to a relatively thin passivation layer made of silicon oxide, silicon nitride or diamond-like carbon (DLC), a protective layer 18, for example made of a molding material, is arranged covering at least the terminal region TR of the semiconductor wafer 1 at the lateral side 13 and the second main side 12. The protective layer 18 is arranged to overlap a metallization layer (not shown) serving as a first main contact, which is arranged in the active region AR on the second main side 12 of the semiconductor wafer 1, so that the junction termination including the passivation layer 17 is hermetically sealed with respect to the surrounding atmosphere.

The material of the protective layer 18 may illustratively be a thermosetting polymer, an epoxy resin or hybrid epoxy imide polymer, or a rubber such as silicone rubber. Epoxy molding compound materials can be made from multifunctional resins such as polyaromatic ring resins (MAR) and biphenyl aralkyl structures, naphthalene and fluorene structures, or alternative resin and copolymer systems such as bismaleimides, cyanate esters, polyimides, or silicones.

In the first embodiment, the first metal disc 2 is fixed or glued to the semiconductor wafer 1 by means of a protective layer 18, which protective layer 18 is fixed or glued to the lateral side 13 of the semiconductor wafer 1, to the second main side 12 of the semiconductor wafer 1 in the termination region TR of the semiconductor wafer 1, and to the lateral side surface 23 of the first metal disc 2. Similarly, the second metal plate 3 is fixed or glued to the semiconductor wafer 1 by means of a protective layer 18, which is fixed or glued to a lateral side surface 33 of the second metal plate 3. By the protective layer 18 being fixed or glued on the semiconductor wafer 1 and on the lateral side surface 23 of the first metal disc 2, the protective layer 18 effectively seals the interface between the semiconductor wafer 1 and the first metal disc 2 with respect to the atmosphere surrounding the power semiconductor device 100.

The first metal disk 2 and the second metal disk 3 are illustratively molybdenum (Mo) disks or tungsten (W) disks, which have a coefficient of thermal expansion close to that of conventional semiconductor materials such as silicon (Si) or silicon carbide (SiC). The first metal disc 2 made of Mo and the second metal disc 3 made of silver (Ag) having the highest electrical conductivity may be finally combined. The semiconductor wafer 1, the first metal disc 2 and the second metal disc 3 have a circular shape in orthogonal projection on a plane parallel to the first main side 11. The first and second metal disks may be covered by an oxidation resistant protective layer, such as a ruthenium (Ru) layer. In the first embodiment, the first metal disc 2 has a diameter d₂Said diameter d₂Is the lateral dimension of the first metal disc 2, which is the same as the diameter d of the semiconductor wafer 1_wSame, the diameter d_wIs the lateral dimension of the semiconductor wafer 1. The first metal disc 2 is arranged on the first main side 11 to cover the first main side 11 of the semiconductor wafer 1, i.e. to have an orthogonal projection on a plane parallel to the first main side 11 overlapping the entire first main side 11 of the semiconductor wafer 1.

The interface between the first metal disc 2 and the semiconductor wafer 1 is a free floating interface, i.e. the first metal disc 2 is neither bonded, nor brazed or soldered to the first main side 11 of the semiconductor wafer 1, so that the first metal disc 2 can slide along the second main side 11 when expanding laterally due to heat rise during operation of the power semiconductor device 100. In the first embodiment, the first metal pad 2 (which may comprise an oxide protection layer as discussed above) may be in direct electrical and physical contact with a metallization layer on the first main side 11 of the semiconductor wafer 1, which serves as a second main contact.

The power semiconductor device 100 according to the first embodiment includes a case 6 including a ceramic case portion 6 a.

Next, a power semiconductor device 200 according to a second embodiment is described with reference to fig. 2. Due to the many similarities between the first and second embodiments, only the differences between the two embodiments will be described. Reference is made to the discussion of the first embodiment above with respect to all other features. In particular, elements having the same reference numerals shall refer to elements having the same characteristics and features as described above for the first embodiment. The power semiconductor device 200 according to the second embodiment differs from the power semiconductor device according to the first embodiment in that a metal layer 30 is sandwiched between the first metal disc 2 and the semiconductor wafer 1, the metal layer 30 having a melting point below 150 deg.c, such as below 125 deg.c, and also such as below 100 deg.c. The metal layer 30 may include any of Liquid Metal Thermal Interfaces (LMTI). It may be a eutectic alloy based on gallium (Ga), such as GaIn, GaInSn and GaInSnZn. Gallium (Ga), indium (In), cesium (Cs), rubidium (Rb) and their alloys, such as alloys of tin (Sn), bismuth (Bi), lead (Pb) and cadmium (Cd), or alloys of aluminum (Al), gallium (Ga), indium (In), thallium (Tl), or mixtures and alloys thereof, are also possible. The thickness of the metal layer 30 is in the range of 0.1 μm to 500 μm, for example, in the range of 1 μm to 100 μm. The metal layer 30 improves the thermal and electrical contact between the first metal disc 2 and the semiconductor wafer 1 resulting in a more efficient heat removal and lower on-state losses of the power semiconductor device 200, whereas the metal layer 30 may be in a liquid state during operation to reduce compressive or tensile stresses in the semiconductor wafer 1 and the first metal disc 2 due to the different coefficients of thermal expansion of the semiconductor wafer 1 and the first metal disc 2. In the case where the protective layer 18 is fixed or glued to the lateral side surfaces 23 of the semiconductor wafer 1 and the first metal pad 2, the protective layer 18 effectively encapsulates the metal layer 30 and prevents any leakage of the material of the metal layer 30 in a liquid state.

Next, a power semiconductor device 300 according to a third embodiment is described with reference to fig. 3. Due to the many similarities between the first and third embodiments, only the differences between the two embodiments are described below. Reference is made to the discussion of the first embodiment above with respect to all other features. The power semiconductor device 300 differs from the power semiconductor device 200 in that the first metal pad 2 is not fixed or glued to the semiconductor chip 1 by the protective layer 28. The protective layer 28 therefore differs from the protective layer 18 in that the protective layer 28 is not fixed or glued to the lateral side surface 23 of the first metal disc 2. In fig. 3, this difference is reflected by the gap 28a between the lateral side surface 23 of the first metal disc 2 and the protective layer 28. Similarly, in contrast to the power semiconductor device 100, the protective layer 28 is also not fixed or glued to the lateral side surface 33 of the second metal pad 3, the lateral side surface 33 of the second metal pad 3 being separated from the protective layer 28 by the gap 28b in fig. 3. The protective layer 28 may be the same as the protective layer 18 described above in the first embodiment for all other characteristics or features. The power semiconductor 300 is most suitable for a power device requiring ion and/or electron irradiation after completing device processing including formation of a protective layer.

Next, a power semiconductor device 400 according to a fourth embodiment is explained with reference to fig. 4. In view of the many similarities between the first and fourth embodiments, only the differences between the two embodiments are described below. Reference may be made to the discussion above for the first embodiment with respect to all other features. The power semiconductor device 400 differs from the power semiconductor device 100 described above in that, as shown in fig. 4, the protective layer 38 is fixed or glued to only a portion 23a of the lateral side surface 23 of the first metal pad 2. The lower portion 23b of the lateral side surface 23 of the first metal disc 2 is not fixed or glued to the protective layer 23. In all other respects, the protective layer 38 is the same as the protective layer 18 of the power semiconductor device 100 shown in fig. 1.

Next, a power semiconductor device 500 according to a fifth embodiment is explained with reference to fig. 5. Due to the many similarities between the first and fifth embodiments, only the differences between the two embodiments are described below. Reference is made to the discussion of the first embodiment above with respect to all other features. The power semiconductor device 500 differs from the power semiconductor device 100 described above in that the first metal disc 22 has a diameter d₂', the diameter d₂' is the lateral dimension of the first metal disc 2, which is greater than the diameter d of the semiconductor wafer 1_wSaid diameter d_wIs the lateral dimension of the semiconductor wafer 1. Similarly, the diameter of the first pole piece 24 in the fifth embodiment is also larger than the diameter of the first pole piece 4 in the first embodiment. Due to the diameter d of the first metal disc 22₂' larger than the diameter of the semiconductor wafer 1, the protective layer 48 is fixed or glued not only to the lateral side surfaces 223 of the first metal disc 22 but also to the circumferential edge portion of the upper side 224 of the first metal disc 22. Larger diameter d₂'>d_wThe heat removal of the power semiconductor device 500 during operation is improved. Other characteristics and features of the first metal disc 22, the first pole piece 24 and the protective layer 48 are the same as those of the first metal disc 2, the first pole piece 4 and the protective layer 18 in the first embodiment, respectively.

Next, a power semiconductor device 600 according to a sixth embodiment is explained with reference to fig. 6. Due to the many similarities between the fifth and sixth embodiments, only the differences between the two embodiments will be described below. Reference is made to the above discussion of the fifth embodiment with respect to all other features. Similar to the power semiconductor device 500 discussed above, the power semiconductor device 600 has a first metal disc 32, the first metal disc 32 having a diameter d₂", the diameter d₂"is the lateral dimension of the first metal disc 2, which is greater than the diameter d of the semiconductor wafer 1_wThe diameter d_wIs the lateral dimension of the semiconductor wafer 1. Similarly, the diameter of the first pole piece 34 in the sixth embodiment is also larger than the diameter of the first pole piece 4 in the first embodiment. With respect to the fifth embodimentIn contrast to the protective layer 48 in the example, the protective layer 58 in the sixth embodiment is fixed or glued only to the circumferential edge portion of the upper side 324 of the first metal disc 32, and is not fixed or glued to the lateral side surface 323 of the first metal disc 32. Relatively large diameter d₂”>d_wThe heat removal of the power semiconductor device 600 during operation is improved. Other characteristics and features of the first metal disc 32, the first pole piece 34, and the protective layer 58 are the same as those of the first metal disc 22, the first pole piece 24, and the protective layer 48, respectively, in the fifth embodiment.

In a comparative example not covered by the appended claims, a power semiconductor device is provided which is identical to the power semiconductor device according to the sixth embodiment, except that the first metal pad 32 is bonded to the semiconductor wafer 1 by bonding or brazing.

In an exemplary method for manufacturing the power semiconductor device 100, 200, 300, 400, 500, 600 according to any of the above-described embodiments, the protective layer 18, 28, 38, 48, 58 may be formed by transfer molding. In this case, the protective layers 18, 28, 38, 48, 58 may be made of a thermosetting polymer. An advantage of transfer molding over other molding techniques is that the viscosity of the thermosetting polymer is relatively high during transfer molding.

Therefore, the use of transfer molding is particularly advantageous for the manufacture of power semiconductor devices 100, 200, 400, 500, 600 in which the first metal pad 2, 22, 32 and/or the second metal pad 3 is fixed or glued to the protective layer 18, 38, 48, 58 in the above-described embodiments as shown in fig. 1, 2 and 4 to 6. The high viscosity of the thermosetting polymer results in that the polymer does not easily enter the gap between the first metal disc 2, 22 and the semiconductor wafer 1 and/or the gap between the second metal disc 3 and the semiconductor wafer 1 during the molding process. Other advantages of transfer molding are the relatively low cost of the molding equipment, the relatively short cycle time, and the relatively low cost of tool maintenance compared to other molding techniques such as injection molding.

It will be apparent to those skilled in the art that modifications may be made to the embodiments described above without departing from the inventive concept as defined by the appended claims.

In the above-described embodiments, either (as in the third embodiment shown in fig. 3) the protective layer 28 is neither fixed nor glued to the first metal disc 2 and the second metal disc 3, or (as in the remaining embodiments shown in fig. 1, 2 and 4 to 6) the protective layer 18, 38, 48, 58 is fixed or glued to the first metal disc 2 and the second metal disc 3. However, the protective layer may also be glued or fixed to only one of the first and second metal discs.

In the above embodiments, the power semiconductor devices 100, 200, 300, 400, 500, 600 include the case 6. However, the power semiconductor device may not include a housing. The power semiconductor may be, for example, a power semiconductor device without a housing.

In the above embodiments, the power semiconductor device includes the first and second pole pieces and the second metal disk. However, each of these elements is an optional feature, and the power semiconductor device may not include these elements.

In the above embodiment, the semiconductor wafer 1, the first metal disks 2, 22, 32, and the second metal disk 3 are described as having circular shapes (orthogonal projections on a plane parallel to the first main side), respectively. Thus, a single diameter is used to characterize the lateral dimensions of the first metal disc 2, the second metal disc 3 and the semiconductor wafer 1, respectively. However, the present invention is not limited to this particular shape of the semiconductor wafer 1, the first metal plate 2 and the second metal plate 3. In general, the shape of the first metal disc 2, the second metal disc 3 and the semiconductor wafer 1 may be any shape, and the lateral dimensions of the first metal disc 2, the second metal disc 3 and the semiconductor wafer 1 may depend on the lateral direction, respectively, i.e. may be different for two different lateral directions. In this general case, the lateral dimension of the first metal disc 2 is the same or larger in any lateral direction. For example, the shape of the semiconductor wafer and the shape of the first metal plate may be rectangular with a short side and a long side, respectively, wherein the short side of the semiconductor wafer is parallel to the short side of the first metal plate and the long side of the semiconductor wafer is parallel to the long side of the first metal plate. In this exemplary case, the length of the short side of the first metal plate should be equal to or greater than the length of the semiconductor wafer, and the length of the long side of the first metal plate should be equal to or greater than the length of the semiconductor wafer.

In the above embodiments shown in fig. 1-6, the junction termination is illustratively shown as a single-sided, single positive bevel. However, the present invention is not limited to any particular type of junction termination as long as the junction termination is disposed along the circumferential edge of the semiconductor wafer. The junction termination may, for example, include a single-sided single negative bevel, a single positive bevel, a double positive bevel, a combination of positive and negative bevel, or a planar junction termination, such as Junction Termination Extension (JTE), lateral doping (VLD), and variations of floating field ring termination (FFR) with and without field plate extension.

In the above-described second embodiment shown in fig. 2, the metal layer 30 is sandwiched between the first metal disc 2 and the semiconductor wafer 1. A metal layer having the same characteristics as the metal layer 30 may also be sandwiched between the second metal plate 3 and each semiconductor wafer 1 in the above-described embodiments. Such a metal layer sandwiched between the second metal plate 3 and the semiconductor wafer 1 can be effectively encapsulated by fixing or gluing the protective layer 18 to the semiconductor wafer 1 and to the lateral side surface 33 of the second metal plate 3, so that leakage of the material of such a metal layer in a liquid state can be prevented.

It should be noted that the term "comprising" does not exclude other elements or steps and the indefinite article "a" or "an" does not exclude a plurality. Furthermore, various elements described may be combined in different embodiments.

List of reference numerals

1 semiconductor wafer

2. 22, 32 first metal disc

3 second Metal plate

4. 24, 34 first pole piece

5 second pole piece

6 casing

6a ceramic housing part

11 first main side

12 second main side

13 lateral side of the semiconductor wafer

15 knot

17 passivation layer

18. 28, 38, 48 protective layer

224. 324 edge portion of upper side surface of first metal disk

23. Lateral side surfaces of 223, 323 first metal plate

23a first portion of a lateral side surface of a first metal disc

23b second part of the lateral side surface of the first metal disc

28a first gap

28b second gap

23 lateral side surfaces of the first metal disc

30 metal layer

33 lateral side surface of the second metal disc

100 power semiconductor device according to a first embodiment

200 power semiconductor device according to the second embodiment

300 power semiconductor device according to the third embodiment

400 power semiconductor device according to the fourth embodiment

500 Power semiconductor device according to a fifth embodiment

600 power semiconductor device according to a sixth embodiment

AR active region

d₁Diameter of the second metal disk

d₂、d₂'、d₂Diameter of first Metal disk

d_wDiameter of semiconductor wafer

A TR junction termination region.