阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 何柏宽 陈欣苹 吴佳典 于 2020-10-29 设计创作，主要内容包括：本公开提供一种半导体装置,其包括第一导电结构、第一介电结构、第二导电结构、蚀刻停止层、第一间隔物结构及第二介电结构。第一介电结构位在第一导电结构的第一表面和第二导电结构的表面之间。蚀刻停止层覆盖第一导电结构。第一间隔物结构覆盖第一介电结构。第二介电结构覆盖第一间隔物结构和蚀刻停止层。(The present disclosure provides a semiconductor device including a first conductive structure, a first dielectric structure, a second conductive structure, an etch stop layer, a first spacer structure, and a second dielectric structure. The first dielectric structure is located between the first surface of the first conductive structure and the surface of the second conductive structure. The etch stop layer covers the first conductive structure. The first spacer structure covers the first dielectric structure. A second dielectric structure covers the first spacer structure and the etch stop layer.)

1. A semiconductor device, comprising:

a first conductive structure;

a first dielectric structure;

a second conductive structure, wherein the first dielectric structure is between a first surface of the first conductive structure and a surface of the second conductive structure;

an etch stop layer covering the first conductive structure;

a first spacer structure covering the first dielectric structure; and

a second dielectric structure covering the first spacer structure and the etch stop layer.

Technical Field

The present disclosure relates to semiconductor devices and, more particularly, to semiconductor devices that help control the alignment of conductive structures relative to underlying conductive structures.

Background

Semiconductor devices include conductive structures (e.g., vias and metal lines) that connect together components of the semiconductor device (e.g., transistors, capacitors, etc. of the semiconductor device). Due to inaccuracies in the process, such as overlay shift (overlay shift), the two conductive structures may be misaligned such that the first conductive structure may not fully contact the second conductive structure. Misalignment can cause the conductive structure to come too close to an adjacent conductive structure, resulting in leakage current. Furthermore, misalignment may result in increased resistance being introduced into the semiconductor device. As a result, misalignment can reduce the yield and reliability of semiconductor devices.

Disclosure of Invention

An object of the present disclosure is to provide a semiconductor device to solve at least one of the problems described above.

The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive structure, a first dielectric structure, a second conductive structure, an etch stop layer, a first spacer structure, and a second dielectric structure. The first dielectric structure is between the first surface of the first conductive structure and the surface of the second conductive structure. The etch stop layer covers the first conductive structure. The first spacer structure covers the first dielectric structure. A second dielectric structure covers the first spacer structure and the etch stop layer.

The present disclosure provides a method of forming a semiconductor device. A method of forming a semiconductor device includes forming a first dielectric structure and a second dielectric structure, wherein a conductive structure and a sacrificial material structure are disposed between the first dielectric structure and the second dielectric structure; removing a portion of the first dielectric structure to define a first recess; forming a spacer structure in the first recess; removing at least some of the sacrificial material structures to define second recesses; and forming a dielectric layer over the spacer structure and in the second recess.

The present disclosure provides a semiconductor device. The semiconductor device comprises a conductive structure, a first dielectric structure, a second dielectric structure, an etching stop layer, a spacer structure and a third dielectric structure. The conductive structure is between the sidewalls of the first dielectric structure and the sidewalls of the second dielectric structure. The etch stop layer covers the conductive structure and is between sidewalls of the first dielectric structure and sidewalls of the second dielectric structure. The spacer structure covers the first dielectric structure. A third dielectric structure covers the spacer structure and the etch stop layer.

Drawings

Aspects of the disclosure can be better understood from the following examples and drawings. It should be understood that the schematic drawings are exemplary and that various features are not illustrated herein. The dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1, 2, 3A, 3B, 3C, 3D, 4, 5, 6, 7, 8, 9A, and 9B are cross-sectional views of semiconductor devices at various stations of a process according to some embodiments.

Fig. 9C and 9D are top views of semiconductor devices according to some embodiments.

Fig. 10 and 11 are cross-sectional views of semiconductor devices at various stations of a process according to some embodiments.

Fig. 12 is a cross-sectional view of a semiconductor device according to some embodiments.

Fig. 13 is a cross-sectional view of a semiconductor device according to some embodiments.

Fig. 14 is a cross-sectional view of a semiconductor device according to some embodiments.

Detailed Description

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific embodiments of various components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosure recites a first feature formed on or above a second feature, that embodiment may include that the first feature is in direct contact with the second feature, embodiments may also include that additional features are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the same reference numbers and/or designations may be reused in various embodiments of the disclosure below. These iterations are for simplicity and clarity and are not intended to limit the particular relationship between the various embodiments and/or configurations discussed.

Furthermore, it is used in terms of spatial correlation. Such as "below" …, below "," lower "," over "," upper "and the like, to facilitate description of the relationship of one element or feature to another element(s) or feature(s) in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, the device may be turned to a different orientation (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

In some embodiments, a semiconductor device is provided that includes a plurality of spacer structures for aligning a conductive structure (e.g., a via) with another conductive structure below. In some embodiments, spacer structures are formed on both sides of the underlying conductive structure. In some embodiments, a dielectric layer is formed over the spacer structures and over the first recess, the first recess being defined by sidewalls of the spacer structures and a top surface of the underlying conductive structure. In some embodiments, when etching the dielectric layer to form the second recess in which the conductive structure is to be formed, the etching of the spacer structure and the layers below the spacer structure is mitigated due to the etch selectivity of the spacer structure relative to the dielectric layer. As such, in some embodiments, the second recess is aligned with the underlying conductive structure disposed between the spacer structures. Thus, in some embodiments, the spacer structure limits the area in which the second recess is formed and thereby provides or helps control the alignment of the conductive structure formed in the second recess relative to the underlying conductive structure. In some embodiments, the spacer structure is used to provide a restriction for forming a self-aligned via integrated with a line damascene process. The methods and subsequent formation disclosed herein may be used to form conductive structures or vias to contact contacts disposed in the first metal layer (M1 layer) to Mx of the semiconductor device, where x is an integer greater than 1.

Fig. 1, 2, 3A-3D, 4-8, 9A, 9B, 10, and 11 are cross-sectional views of a semiconductor device 100 formed with spacer structures 500 a-500 g, and fig. 9C and 9D are top views of the semiconductor device 100 formed with spacer structures 500 a-500 g, according to some embodiments.

Referring to fig. 1, a first conductive layer 102 is formed, according to some embodiments. In some embodiments, the first conductive layer 102 is formed by a deposition process, such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Low Pressure CVD (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer CVD (ALCVD), Atomic Layer Deposition (ALD), spin-on coating, or other suitable deposition process. In some embodiments, first conductive layer 102 is a metal layer from which metal contacts (metal contacts) are to be formed. In some embodiments, the first conductive layer 102 includes copper (Cu), ruthenium (Ru), tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), molybdenum (Mo), iridium (Ir), rhodium (Rh), or other suitable materials. Although not shown, in some embodiments, one or more layers or elements of a semiconductor device, such as a semiconductor substrate, a source/drain region of a transistor, a gate structure of a transistor, a capacitor, a resistive element, etc., may be provided below the first conductive layer 102.

In some embodiments, the etch stop layer 104 is formed over the first conductive layer 102. In some embodiments, the etch stop layer 104 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the etch stop layer 104 covers the first conductive layer 102. In some embodiments, the etch stop layer 104 contacts the first conductive layer 102. In some embodiments, the etch stop layer 104 comprises silicon carbide nitride (SiCN), silicon dioxide (SiO)₂) Silicon nitride (SiN)_x) Aluminum oxynitride (AlO)_xN_y) Ruthenium (Ru), tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), cobalt tungsten phosphide (CoWP), metal oxides (e.g., aluminum oxide (AlO)_x) X and y are integers greater than or equal to 1) or other suitable material. In some embodiments, etch stop layer 104 has a height between about 1 and about 200 angstroms. In some embodiments, the etch stop layer 104 comprises a single layer of material. In some embodiments, the etch stop layer 104 comprises multiple layers of materials. For example, the etch stop layer 104 may include a silicon carbide nitride (SiCN) layer, silicon dioxide (SiO)₂) Layer(s)And a titanium (Ti) layer. In some embodiments, each layer is between about 3 angstroms and about 200 angstroms thick.

In some embodiments, a layer of sacrificial material 106 is formed over the etch stop layer 104. In some embodiments, the sacrificial material layer 106 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the layer of sacrificial material 106 covers the etch stop layer 104. In some embodiments, the layer of sacrificial material 106 contacts the etch stop layer 104. In some embodiments, the sacrificial material layer 106 comprises silicon carbide nitride (SiCN), silicon dioxide (SiO)₂) Silicon nitride (SiN)_x) Aluminum oxynitride (AlO)_xN_y) Titanium nitride (TiN), metal oxides (e.g. aluminum oxide (AlO)_x) X and y are integers greater than or equal to 1) or other suitable material. In some embodiments, the sacrificial material layer 106 comprises a hard mask material, such as a nitride, an oxide, silicon, or other suitable material.

In some embodiments, a hard mask 108 is formed over the layer of sacrificial material 106. In some embodiments, the hard mask 108 comprises at least one of an oxide, a nitride, silicon, or other suitable material. In some embodiments, the hard mask 108 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the hard mask 108 covers the layer of sacrificial material 106. In some embodiments, the hard mask 108 contacts the layer of sacrificial material 106. In some embodiments, the sacrificial material layer 106 is omitted and the hard mask 108 is used in place of the sacrificial material layer 106. Thus, in some embodiments, the hard mask 108 may contact the etch stop layer 104. In some embodiments, where the sacrificial material layer 106 comprises a hard mask material, the material of the hard mask 108 is selected to have a different etch selectivity than the hard mask material of the sacrificial material layer 106 to enable etching of the sacrificial material layer 106 at a different time than the hard mask 108, as described with reference to fig. 4 and 7.

In some embodiments, the hard mask 108 is formed by forming a layer of hard mask material over the layer of sacrificial material 106 or over the etch stop layer 104, and patterning the layer of hard mask material to define the hard mask 108, the hard mask 108 covering portions of the layer of sacrificial material 106, the etch stop layer 104, and the first conductive layer 102, while other portions of the layer of sacrificial material 106, the etch stop layer 104, and the first conductive layer 102 are uncovered or exposed. In some embodiments, the hard mask 108 defines an opening through which a subsequent etching process is performed to create a recess through at least one of the sacrificial material layer 106, the etch stop layer 104, or the first conductive layer 102.

Referring to fig. 2, portions of the sacrificial material layer 106, the etch stop layer 104, and the first conductive layer 102 are removed, according to some embodiments. In some embodiments, removing the sacrificial material layer 106, the etch stop layer 104, and the portions of the first conductive layer 102 results in the formation of the first conductive structures 102 a-102 g, the etch stop layer structures 104 a-104 g, and the sacrificial material structures 106 a-106 g, respectively. In some embodiments, the portions of the sacrificial material layer 106, the etch stop layer 104, and the first conductive layer 102 are removed by an etching process to define the recesses 202a-202 f. In some embodiments, the etching process does not remove the sacrificial material layer 106, the etch stop layer 104, and the first conductive layer 102 forming the first conductive structures 102 a-102 g, the etch stop layer structures 104 a-104 g, and the sacrificial material structures 106 a-106 g because the hard mask 108 protects these materials from being etched away or removed by the etching process. In some embodiments, the etching process comprises a single damascene etching process. In some embodiments, the etching process comprises a dual damascene etching process. In some embodiments, the etching process comprises a metal etching process. In some embodiments, depending on the material composition and etch selectivity of the sacrificial material layer 106, the etch stop layer 104, and the first conductive layer 102, an etch process may be performed in a single station or multiple stations using at least one of different etch chemistries or different etch methods to remove the sacrificial material layer 106, the etch stop layer 104, and the multiple portions of the first conductive layer 102.

In some embodiments, the sacrificial material layer 106, the etch stop layer 104, and the portions of the first conductive layer 102 are selectively removed to maintain a spacing of about 14nm to about 42nm or greater between the first conductive structures 102 a-102 g. For example, the spacing 203 between the conductive structures 102a and 102b of the first conductive structures 102 a-102 g may be between about 14nm and about 42 nm. In some embodiments, after removing the sacrificial material layer 106, the etch stop layer 104, and the plurality of portions of the first conductive layer 102, a ratio of a height of the first conductive structures 102 a-102 g (e.g., a height 205 of the conductive structure 102 b) to a spacing between the first conductive structures 102 a-102 g (e.g., a spacing 203 between the conductive structure 102a and the conductive structure 102 b) is between about 1-4.

Referring to fig. 3A, a dielectric layer 300 is formed over the hard mask 108 and within the recesses 202a-202f, according to some embodiments. In some embodiments, the dielectric layer 300 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, dielectric layer 300 comprises a low-k dielectric material, such as silicon oxycarbide (SiO)_xC_yH_z) Silicon oxide (SiO)_x) Silicon carbide nitride (SiCN), oxygen-doped silicon carbide (SiC) (oxygenated SiC; ODC), nitrogen-doped silicon carbide (SiC) (nitrogen bonded SiC; NDC), tetraethoxysilane (tetraethoxysilane; TEOS), or other suitable material, where x, y, and z are integers greater than or equal to 1. As used herein, a low-k dielectric material refers to a material having a k value (dielectric constant) of less than about 3.9. Some low-k dielectric materials have k values below about 3.5, and may have k values below about 2.5. In some embodiments, the dielectric layer 300 comprises a single layer of material, as shown in fig. 3A.

In some embodiments, the dielectric layer 300 covers the hard mask 108 and is disposed laterally adjacent to the first conductive structures 102 a-102 g, the etch stop layer structures 104 a-104 g, and the sacrificial material structures 106 a-106 g. In some embodiments, the dielectric layer 300 contacts at least one of the hard mask 108, the first conductive structures 102 a-102 g, the etch stop layer structures 104 a-104 g, or the sacrificial material structures 106 a-106 g. In some embodiments, the dielectric layer 300 contacts the top surface of the hard mask 108 and sidewalls of the hard mask 108, sidewalls of the first conductive structures 102 a-102 g, sidewalls of the etch stop layer structures 104 a-104 g, and sidewalls of the sacrificial material structures 106 a-106 g.

In some embodiments, as shown in fig. 3B-3D, a plurality of dielectric layers are formed over the hard mask 108 and within the recesses 202a-202 f. Referring to fig. 3B, a first embodiment of forming a plurality of dielectric layers is shown. In some embodiments, a second dielectric layer 304 is formed over the hard mask 108 and in the recesses 202a-202f along sidewalls of the first conductive structures 102 a-102 g, sidewalls of the etch stop layer structures 104 a-104 g, and sidewalls of the sacrificial material structures 106 a-106 g. In some embodiments, the second dielectric layer 304 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the second dielectric layer 304 is formed to be compliant (conformal) such that the second dielectric layer 304 has a substantially uniform thickness. In some embodiments, the dielectric layer 300 is formed over the second dielectric layer 304. In some embodiments, the dielectric layer 300 is formed to be non-compliant (non-conformal), such that the thickness of the dielectric layer 300 varies.

In some embodiments, dielectric layer 300 comprises a first dielectric material and second dielectric layer 304 comprises a second dielectric material. In some embodiments, the first dielectric material is different from the second dielectric material. For example, in some embodiments, air gaps 302 a-302 f are formed within and defined by the dielectric layer 300 as the dielectric layer 300 pinches off near the bottom of the recesses 202a-202f, wherein the recesses 202a-202f may have a smaller width, such as the width 301 between the conductive structure 102a and the conductive structure 102b, due to the tapering of the recesses 202a-202 f. In some embodiments, air gaps 302 a-302 f are formed between the first conductive structures 102 a-102 g. In some embodiments, the air gaps 302 a-302 f occupy about 20% to about 90% of the volume of the portion of the dielectric layer 300 between the first conductive structures 102 a-102 g.

In some embodiments, the second dielectric layer 304 is formed across the bottom of the recesses 202a-202f from one of the first conductive structures 102 a-102 g to an adjacent other of the first conductive structures 102 a-102 g such that the dielectric layer 300 is separated from the layers below the first conductive structures 102 a-102 g and the recesses 202a-202f by the second dielectric layer 304. In some embodiments, after forming the second dielectric layer 304, and prior to forming the dielectric layer 300, an anisotropic or other etching process is performed to remove horizontal portions of the second dielectric layer 304 prior to forming the dielectric layer 300. For example, in some such embodiments, the dielectric layer 300 may thus contact the layers below the first conductive structures 102 a-102 g and the recesses 202a-202 f.

Although the air gaps 302 a-302 f are shown in embodiments where multiple dielectric layers 300, 304 are formed, the air gaps 302 a-302 f may also be present in embodiments where only a single dielectric layer 300 is formed over the hard mask 108 and within the recesses 202a-202f (as shown in FIG. 3A).

Referring to fig. 3C, a second embodiment of forming a plurality of dielectric layers is shown. In some embodiments, a second dielectric layer 304 is formed over the hard mask 108 and in the recesses 202a-202f along sidewalls of the first conductive structures 102 a-102 g, the etch stop layer structures 104 a-104 g, and the sacrificial material structures 106 a-106 g. In some embodiments, a third dielectric layer 306 is formed over the second dielectric layer 304. In some embodiments, dielectric layer 300 is formed over third dielectric layer 306. In some embodiments, the third dielectric layer 306 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the second dielectric layer 304 and the third dielectric layer 306 are formed to be compliant such that the second dielectric layer 304 has a substantially uniform thickness and the third dielectric layer 306 has a substantially uniform thickness. In some embodiments, the dielectric layer 300 is formed to be non-compliant such that the thickness of the dielectric layer 300 varies.

In some embodiments, dielectric layer 300 comprises a first dielectric material, second dielectric layer 304 comprises a second dielectric material, and third dielectric layer 306 comprises a third dielectric material. In some embodiments, the first dielectric material is different from at least one of the second dielectric material or the third dielectric material. In some embodiments, the second dielectric material is different from at least one of the first dielectric material or the third dielectric material.

In some embodiments, the second dielectric layer 304 and the third dielectric layer 306 are formed across the bottom of the recesses 202a-202f from one of the first conductive structures 102 a-102 g to an adjacent other of the first conductive structures 102 a-102 g such that the dielectric layer 300 is separated from the layers below the first conductive structures 102 a-102 g and the recesses 202a-202f by the second dielectric layer 304 and the third dielectric layer 306. In some embodiments, after forming the second and third dielectric layers 304, 306, and prior to forming the dielectric layer 300, an anisotropic or other etching process is performed to remove horizontal portions of the second and third dielectric layers 304, 306 prior to forming the dielectric layer 300. In some embodiments, after forming the second dielectric layer 304 and before forming the third dielectric layer 306, a first anisotropic etch process or other etch process is performed to remove horizontal portions of the second dielectric layer 304, and after forming the third dielectric layer 306 and before forming the dielectric layer 300, a second anisotropic etch process or other etch process is performed to remove horizontal portions of the third dielectric layer 306. In some such embodiments, in which horizontal portions of the second dielectric layer 304 and the third dielectric layer 306 are removed, the dielectric layer 300 may thus contact the layers below the first conductive structures 102 a-102 g and the recesses 202a-202 f.

In some embodiments, an anisotropic or other etching process is performed to remove horizontal portions of only one of the second dielectric layer 304 or the third dielectric layer 306. For example, in some embodiments, an anisotropic or other etching process is performed to remove horizontal portions of the second dielectric layer 304, form the third dielectric layer 306, and adhere to form the dielectric layer 300 on the third dielectric layer 306, without performing another etching process between the formation of the third dielectric layer 306 and the dielectric layer 300. In some such embodiments, the dielectric layer 300 may thus be separated from the layers below the first conductive structures 102 a-102 g and the recesses 202a-202f by the third dielectric layer 306. As another example, in some embodiments, the second dielectric layer 304 is formed, the third dielectric layer 306 is formed over the second dielectric layer 304, an anisotropic or other etching process is performed to remove only horizontal portions of the third dielectric layer 306, and the dielectric layer 300 is formed after the vertical etching process. In some such embodiments, the dielectric layer 300 may thus be separated from the layers below the first conductive structures 102 a-102 g and the recesses 202a-202f by the second dielectric layer 304.

Referring to fig. 3D, a third embodiment of forming a plurality of dielectric layers is shown. In some embodiments, the second dielectric layer 304 and the third dielectric layer 306 are formed across the bottom of the recesses 202a-202f from one of the first conductive structures 102 a-102 g to an adjacent other of the first conductive structures 102 a-102 g. In some embodiments, no etching process is performed after forming the second dielectric layer 304 and the third dielectric layer 306, and the dielectric layer 300 is formed over the second dielectric layer 304 and the third dielectric layer 306 such that the dielectric layer 300 is separated from the layers under the first conductive structures 102 a-102 g and the recesses 202a-202f by the second dielectric layer 304 and the third dielectric layer 306.

Referring to fig. 4, a portion of the dielectric layer 300 is removed, according to some embodiments. In some embodiments, an etching process is performed to remove a portion of the dielectric layer 300. In some embodiments, the etching process includes a dry etching process, such as Reactive Ion Etching (RIE), Plasma Enhanced (PE) etching, Inductively Coupled Plasma (ICP) etching, or other dry etching process that etches back the dielectric layer 300 to define the recesses 401 a-401 f. In some embodiments, the removal of the portion of the dielectric layer 300 results in the dielectric structures 300 a-300 f being disposed between surfaces of two adjacent first conductive structures 102 a-102 g, such as between a sidewall of one of the first conductive structures 102 a-102 g and a sidewall of an adjacent other of the first conductive structures 102 a-102 g. In some embodiments, dielectric structures 300 a-300 f are formed between etch stop layer structures 104 a-104 g. In some embodiments, dielectric structures 300 a-300 f are formed between the sacrificial material structures 106 a-106 g. In some embodiments, the top surface of the dielectric structures 300 a-300 f is between about 0 and 200 angstroms above the top surface of the first conductive structures 102 a-102 g. Accordingly, in some embodiments, the height of the dielectric structures 300 a-300 f (e.g., height 402 of dielectric structure 300 d) is between about 0 and 200 angstroms greater than the height of the first conductive structures 102 a-102 g (e.g., height 205 of conductive structure 102 b).

In some embodiments, a chemical-mechanical planarization (CMP) process is performed prior to the dry etch to remove some of the dielectric layer 300 before the etch process etches back the dielectric layer 300 to define the recesses 401 a-401 f. In some embodiments, the CMP process exposes the hard mask 108. In some embodiments, after the etch process etches back the dielectric layer to define the recesses 401a to 401f, a second CMP process or a second etch process is performed to remove the hard mask 108. In some embodiments, the second CMP process or the second etch process that removes the hard mask 108 exposes the top surfaces of the sacrificial material structures 106 a-106 g.

In some embodiments, in the case where a plurality of dielectric layers (e.g., the dielectric layer 300, the second dielectric layer 304, and the third dielectric layer 306) are formed in the recesses 202a to 202f, each of the plurality of dielectric layers may be subjected to a CMP process or to an etching process to etch back the plurality of dielectric layers. In some embodiments, each of the plurality of dielectric layers may be etched back using the same etch back process. In some embodiments, an etch-back process for etching back one or more of the plurality of dielectric layers may be different from an etch-back process for etching back another one or more of the plurality of dielectric layers.

Referring to fig. 5, a spacer layer 500 is formed over the dielectric structures 300 a-300 f and the sacrificial material structures 106 a-106 g, according to some embodiments. In some embodiments, the spacer layer 500 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the spacer layer 500 covers the sacrificial material structures 106 a-106 g and is disposed laterally adjacent to the sacrificial material structures 106 a-106 g. In some embodiments, the spacer layer 500 contacts the sacrificial material structures 106 a-106 g. In some embodiments, the spacer layer 500 contacts the top surfaces of the sacrificial material structures 106 a-106 g and the sidewalls of the sacrificial material structures 106 a-106 g.

In some embodiments, the spacer layer 500 comprises silicon carbide nitride (SiCN), silicon dioxide (SiO)₂) Silicon nitride (SiN)_x) Aluminum oxynitride (AlO)_xN_y) Aluminum oxide (AlO)_x) Titanium nitride (TiN), titanium oxide (TiO), zirconium oxide (ZrO)_x) Hafnium oxide (HfO)_x) Or other suitable metallic material, wherein x and y are integers greater than or equal to 1. In some embodiments, the spacer layer 500 comprises a high-k dielectric material. The high-k dielectric material has a k value (dielectric constant) greater than or equal to about 3.9, which is silicon dioxide (SiO)₂) K value of). In some embodiments, the material of the spacer layer 500 is selected to have a different etch selectivity than the material of the sacrificial material structures 106 a-106 g and the etch stop layer structures 104 a-104 g.

In some embodiments, a recess (e.g., recess 502) is defined by the spacer layer 500 in the event that the width of the dielectric structures 300 a-300 f (e.g., width 504 of dielectric structure 300 f) exceeds a particular threshold. In other embodiments, the spacer layer 500 is formed to have a substantially flat top surface regardless of the width of the dielectric structures 300 a-300 f.

Referring to fig. 6, according to some embodiments, a portion of the spacer layer 500 is removed. In some embodiments, an etching process is performed to remove the portion of the spacer layer 500. In some embodiments, the etching process comprises a dry etching process, such as a Reactive Ion Etching (RIE), plasma assisted (PE) etching, Inductively Coupled Plasma (ICP) etching, or other dry etching process that etches back the spacer layer 500. In some embodiments, the removal of the portion of the spacer layer 500 results in the spacer structures 500 a-500 g being formed between the sacrificial material structures 106 a-106 g and over the dielectric structures 300 a-300 f and results in the top surfaces of the sacrificial material structures 106 a-106 g being exposed. In some embodiments, the top surfaces of the spacer structures 500 a-500 g are below the top surfaces of the sacrificial material structures 106 a-106 g. In some embodiments, the spacer structures 500 a-500 g have a height between about 30 angstroms and 100 angstroms. For example, the spacer structure 500a may have a height 601 between about 30 and 100 angstroms. In some embodiments, the top surfaces of the etch stop layer structures 104 a-104 g are vertically spaced from the top surfaces of the spacer structures 500 a-500 g by the dielectric structures 300 a-300 f.

In some embodiments, when the width of the dielectric structures 300 a-300 f exceeds a certain threshold, the recess is defined by the spacer layer 500, for example, when the width 504 of the dielectric structure 300f exceeds a certain threshold, the recess 502 is defined by the spacer layer 500, and the etching process results in the top surface of the dielectric structure (e.g., the top surface of the dielectric structure 300 f) exceeding the certain threshold being exposed. For example, referring to fig. 6, the spacer structure 500g does not extend from a sidewall of one sacrificial material structure 106g to an adjacent other sacrificial material structure 106f because the width 504 of the underlying dielectric structure 300f is greater than a particular threshold. Thus, two different spacer structures 500f and 500g are formed overlying the dielectric structure 300f, and an opening 602 is defined between the two different spacer structures 500f and 500 g. Conversely, the five left-most spacer structures 500 a-500 e extend from a sidewall of one of the sacrificial material structures to a sidewall of an adjacent other of the sacrificial material structures, e.g., the spacer structure 500a extends from a sidewall of the sacrificial material structure 106a to a sidewall of an adjacent other sacrificial material structure 106b, because the width of the underlying dielectric structures 300 a-300 e is less than or equal to a particular threshold. In some embodiments, where the spacer layer 500 is formed to have a substantially planar top surface regardless of the width of the dielectric structures 300 a-300 f, the top surface of the underlying dielectric structures 300 a-300 f remains hidden by the spacer structures 500 a-500 g even if the width of the dielectric structures 300 a-300 f exceeds a certain threshold.

Referring to fig. 7, according to some embodiments, the sacrificial material structures 106 a-106 g are removed to create recesses 701 a-701 g. In some embodiments, an etching process is performed to remove the sacrificial material structures 106 a-106 g. In some embodiments, the etching process comprises a wet etching process, such as chemical etching using a hot phosphoric acid solution or other etchant. In some embodiments, the etching process exposes sidewalls of at least one of the spacer structures 500 a-500 g or the dielectric structures 300 a-300 f. In some embodiments, the etching process exposes the top surfaces of the etch stop layer structures 104 a-104 g. In some embodiments, the etching process does not remove the spacer structures 500 a-500 g because the sacrificial material structures 106 a-106 g have a different etch selectivity than the spacer structures 500 a-500 g.

Referring to fig. 8, a second dielectric layer 800 is formed over the spacer structures 500 a-500 g and the etch stop layer structures 104 a-104 g, according to some embodiments. In some embodiments, a second dielectric layer 800 is formed within the recesses 701 a-701 g. In some embodiments, the second dielectric layer 800 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, second dielectric layer 800 comprises silicon oxycarbide (SiO)_xC_yH_z) Silicon oxide (SiO)_x) Silicon carbide on nitrogen (SiCN), silicon carbide on oxygen (SiC) (ODC), silicon carbide on nitrogen (SiC) (NDC), Tetraethoxysilane (TEOS), or other suitable material, wherein x, y, and z are integers greater than or equal to 1. In some embodiments, a CMP process is performed to planarize the second dielectric layer 800 after forming the second dielectric layer 800.

Referring to fig. 9A-9D, according to some embodiments, a portion of the second dielectric layer 800 is removed. In some embodiments, the second hard mask 902 is formed on some portions of the second dielectric layer 800, and a "via-first" patterning method or a "trench-first" patterning method is used to etch portions of the second dielectric layer 800 that are not hidden by the second hard mask 902 using a dual damascene etch process, such as a back end of line (dual damascene) etch process. Referring to fig. 9A, in some embodiments of the "pre-trench" patterning method, the first etch of the dual damascene process etches an upper portion of the second dielectric layer 800 that is not hidden by the second hard mask 902 to define a first opening 901. In some embodiments, the first etch may stop when the remaining portion of the second dielectric layer 800 has a height 905 of between about 100 and 500 angstroms. Referring to fig. 9B, in some embodiments, the second etch of the dual damascene process etches a lower portion of the second dielectric layer 800 to define a plurality of different openings 903 a-903 c over the first conductive structures 102 a-102 g and form second dielectric structures 800 a-800 d from the second dielectric layer 800. In some embodiments, at least some of the spacer structures 500 a-500 g (e.g., spacer structure 500e and spacer structure 500g) are held in place by the dielectric structures 300 a-300 f and the second dielectric structures 800 a-800 d after the dual damascene process. Fig. 9C shows a top view of the semiconductor device 100 after performing a second etch of the dual damascene process, and fig. 9D shows a similar top view except that the second hard mask 902 and the second dielectric layer 800 have been hidden to expose the spacer structures 500 a-500 g and the etch stop layer structures 104 a-104 g.

Referring to fig. 9B-9D, where fig. 9B is a cross-sectional view of line 9-9 in fig. 9C and 9D, in some embodiments, the spacer structures 500 a-500 g are configured to self-align the openings 903 a-903C with the first conductive structures 102 a-102 g such that the openings 903 a-903C are over the first conductive structures 102 a-102 g. For example, the materials of the spacer structures 500 a-500 g may be selected such that the spacer structures 500 a-500 g are etched at a slower etch rate than the second dielectric layer 800. For example, when the overlying structure (overlay structure) used during the second portion of the dual damascene process is placed over the second hard mask 902, the windows 904, 906, 908 in the overlying structure are intended to be aligned with the first conductive structures 102 a-102 g to enable the formation of openings 903 a-903 c in the second dielectric layer 800 that overlie the first conductive structures 102 a-102 g. However, due to machine tolerances, for example, the windows 904, 906, 908 may not be perfectly aligned with the first conductive structures 102 a-102 g. Instead, windows 904, 906, 908 can move in one or more directions, as shown by windows 906 and 908 in fig. 9C and 9D, which move in the x-direction (extending from left to right across the page) and move in the y-direction (extending from top to bottom across the page). In some embodiments, the openings 903 a-903 c formed in the second dielectric layer 800 during the second etch of the dual damascene process may be aligned with the first conductive structures 102 a-102 g even if the windows 906, 908 are not aligned with the first conductive structures 102 a-102 g because the etch rate of the spacer structures 500 a-500 g relative to the second dielectric layer 800 is slow. In some embodiments, the spacer structures 500 a-500 g also protect the dielectric structures 300 a-300 f from being etched during the dual damascene process.

In some embodiments, at least some portions of the spacer structures 500 a-500 g may be removed in an etching process, although the etch selectivity of the spacer structures 500 a-500 g may mitigate the etching of the spacer structures 500 a-500 g during the etching process to remove a portion of the second dielectric layer 800. For example, in some embodiments, corners of at least one of the spacer structures 500 a-500 g (e.g., one or more corners of the spacer structures 500a, 500b, 500c, 500d, and 500 f) exposed by the windows 904, 906, 908 may be etched during the etching process, resulting in the spacer structures 500a, 500b, 500c, 500d, and 500f having rounded or curved surfaces. Although the illustrated embodiment describes a "pre-trench" patterning method in which the first opening 901 is formed before the openings 903-903 c, in some embodiments, the dual damascene process uses a "pre-via" patterning method in which the openings 903 a-903 c are formed before the first opening 901.

Referring to fig. 10, portions of the etch stop layer structures 104 a-104 g exposed through the openings 903 a-903 c are removed, according to some embodiments. In some embodiments, one or more of the etch stop layer structures 104 a-104 g (e.g., portions of the etch stop layer structures 104b, 104d and 104 f) are removed using an etch process that is selective to the material of the etch stop layer structures 104 a-104 g. Accordingly, in some embodiments, portions of the etch stop layer structures 104 a-104 g that are hidden by at least one of the second dielectric structures 800 a-800 d are protected from being etched during the etching process.

Referring to fig. 11, a second conductive layer 1000 is formed, according to some embodiments. In some embodiments, second conductive layer 1000 is formed by a deposition process, such as CVD, PVD, LPCVD, PECVD, ALCVD, ALD, spin-on techniques, or other suitable deposition process. In some embodiments, the second conductive layer 1000 includes a conductive material, such as copper (Cu), ruthenium (Ru), tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), molybdenum (Mo), iridium (Ir), rhodium (Rh), or other suitable metallic materials. In some embodiments, the second conductive layer 1000 forms vias 1102 a-1102 c in the openings 903 a-903 c over and in contact with the first conductive structures 102 a-102 g, and also forms a second conductive structure 1104 covering the vias 1102 a-1102 c and electrically coupled to the plurality of vias 1102 a-1102 c. In some embodiments, a chemical mechanical polishing process is performed after the second conductive layer 1000 to planarize the top surface of the second conductive layer 1000 and remove the second hard mask 902.

Fig. 12 is a cross-sectional view of forming a semiconductor device 1200 having spacer structures 500 a-500 g according to some embodiments. The semiconductor device 1200 differs from the semiconductor device 100 of fig. 1-11 in that prior to forming the second conductive layer 1000, vias 1202 a-1202 c are formed in the openings 903 a-903 c over and in contact with the first conductive structures 102 a-102 g, and the second conductive layer 1000 is formed over the vias 1202 a-1202 c to define a second conductive structure 1204 covering the vias 1202 a-1202 c and electrically coupled to the plurality of vias 1202 a-1202 c. In some embodiments, the vias 1202 a-1202 c are formed using a growth process, and the second conductive layer 1000 is formed by depositing a metallic material over the vias 1202 a-1202 c. In some embodiments, the vias 1202 a-1202 c are formed by a pre-fill process (pre-fill process) that fills the openings 903 a-903 c over the first conductive structures 102 a-102 g with a metal material, and then the second conductive layer 1000 is formed over the vias 1202 a-1202 c to define the second conductive structure 1204. In some embodiments, the spacer structures 500 a-500 g limit the formation of the vias 1202 a-1202 c to contact and align with the first conductive structures 102 a-102 g. In some embodiments, vias 1202 a-1202 c include a conductive material. Examples of the conductive material include, but are not limited to, cobalt (Co), molybdenum (Mo), tungsten (W), cobalt tungsten phosphide (CoWP), copper (Cu), ruthenium (Ru), aluminum (Al), titanium (Ti), or other suitable conductive material. In some embodiments, vias 1202 a-1202 c include different material compositions and second conductive layer 1000. In some embodiments, vias 1202 a-1202 c comprise a different material composition than second conductive layer 1000.

Fig. 13 is a cross-sectional view of forming a semiconductor device 1300 having spacer structures 500 a-500 g, according to some embodiments. The semiconductor device 1300 differs from the semiconductor device 100 of fig. 1 to 11 in that an etch stop layer 1306 is formed between a first portion of the second dielectric layer 800 and a second portion of the second dielectric layer 800. The first portion of the second dielectric layer 800 and the second portion of the second dielectric layer 800 may have the same material composition, or the material composition of the first portion of the second dielectric layer 800 may be different from the material composition of the second portion of the second dielectric layer 800. In some embodiments, the etch stop layer 1306 serves as a stop for a first etch process of the dual damascene etch process during the dual damascene etch process described with reference to fig. 9A-9C.

The semiconductor device 1300 also differs from the semiconductor device 100 of fig. 1-11 in that a barrier layer 1308 is formed between the vias 1302 a-1302 c and the second conductive layer 1000, which defines a second conductive structure 1304. In some embodiments, the vias 1302 a-1302 c are formed in the openings 903 a-903 c by a deposition process or a growth process. Next, a blocking layer 1308 is formed over the vias 1302 a-1302 c. In some embodiments, the barrier layer 1308 is formed by a compliant deposition process. In some embodiments, after forming the blocking layer 1308, the second conductive layer 1000 is formed to define the second conductive structure 1304. In some embodiments, the second conductive structure 1304 is electrically coupled to the plurality of vias 1302 a-1302 c through the blocking layer 1308. In some embodiments, the barrier layer 1308 includes tantalum (Ta), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), Self-Assembled monolayers (SAM), manganese nitride (MnN)_x) Or other suitable barrier material.

Fig. 14 is a cross-sectional view of a semiconductor device 1400 formed with spacer structures 500 a-500 g. The semiconductor device 1400 differs from the semiconductor device 1300 of fig. 13 in that the etch stop layer 1306 is not present and the barrier layer 1308 does not extend along the sidewalls of the second dielectric structures 800 a-800 d to the top surfaces of the second dielectric structures 800 a-800 d. In some embodiments, barrier layer 1308 is formed in a manner similar to that described with reference to fig. 13. Prior to forming the second conductive layer 1000, however, in some embodiments, an etching process is performed to remove the barrier layer 1308 adjacent to the sidewalls of the second dielectric structures 800 a-800 d and expose the sidewalls of the second dielectric structures 800 a-800 d. When the second conductive layer 1000 is formed later, in some embodiments, the second conductive layer 1000 contacts the sidewalls of the exposed second dielectric structures 800 a-800 d.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is between the first surface of the first conductive structure and the surface of the second conductive structure. The semiconductor device includes an etch stop layer overlying the first conductive structure. The semiconductor device includes a first spacer structure overlying a first dielectric structure. The semiconductor device includes a second dielectric structure overlying the first spacer structure and the etch stop layer.

In some embodiments, the first dielectric structure and the second dielectric structure encapsulate the first spacer structure.

In some embodiments, the semiconductor device includes a third conductive structure in contact with the first conductive structure, the etch stop layer, and the second dielectric structure.

In some embodiments, the etch stop layer covers the second conductive structure.

In some embodiments, the etch stop layer is spaced apart from the first spacer structure by the first dielectric structure.

In some embodiments, the first dielectric structure defines an air gap.

In some embodiments, the semiconductor device includes a barrier layer overlying the second dielectric structure.

In some embodiments, the semiconductor device includes a third dielectric structure. The semiconductor device includes a third conductive structure. The third dielectric structure is between the second surface of the first conductive structure and the surface of the third conductive structure. The semiconductor device includes a second spacer structure overlying the third dielectric structure. The second dielectric structure covers the second spacer structure.

In some embodiments, the third dielectric structure contacts the first conductive structure and the etch stop layer.

In some embodiments, the semiconductor device includes a fourth conductive structure, wherein the fourth conductive structure overlies the second spacer structure and contacts the third conductive structure.

In some embodiments, a semiconductor device includes a barrier structure overlying a fourth conductive structure and a second dielectric structure.

According to some embodiments, a method of forming a semiconductor device is provided. A method of forming a semiconductor device includes forming a first dielectric structure and a second dielectric structure. The conductive structure and the sacrificial material structure are disposed between the first dielectric structure and the second dielectric structure. The method of forming a semiconductor device includes removing a portion of a first dielectric structure to define a first recess. Methods of forming semiconductor devices include forming a spacer structure in a first recess and removing at least some of the sacrificial material structure to define a second recess. A method of forming a semiconductor device includes forming a dielectric layer over the spacer structure and in the second recess.

In some embodiments, a method of forming a semiconductor device includes forming a conductive layer and a sacrificial material layer. A method of forming a semiconductor device includes etching a layer of sacrificial material to define a sacrificial material structure. The method of forming a semiconductor device includes etching a conductive layer to define a conductive structure.

In some embodiments, the step of forming the spacer structure includes forming a spacer layer over the sacrificial material structure and in the first recess. The step of forming the spacer structure comprises etching the spacer layer to define the spacer structure.

In some embodiments, the step of etching the spacer layer includes etching the spacer layer to expose sidewalls of the sacrificial material structure.

In some embodiments, the method of forming a semiconductor device includes removing some of the dielectric layer to define a third recess and expose the spacer structure. The method of forming a semiconductor device includes forming a metal layer in the third recess.

In some embodiments, the step of removing some of the dielectric layer to define the third recess includes exposing a top surface of the conductive structure.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second dielectric structure. The conductive structure is between the sidewalls of the first dielectric structure and the sidewalls of the second dielectric structure. The semiconductor device includes an etch stop layer overlying the conductive structure. The etch stop layer is between a sidewall of the first dielectric structure and a sidewall of the second dielectric structure. The semiconductor device includes a spacer structure overlying the first dielectric structure. The semiconductor device includes a third dielectric structure overlying the spacer structure and the etch stop layer.

In some embodiments, the semiconductor device includes a second conductive structure overlying the spacer structure and the conductive structure.

In some embodiments, a semiconductor device includes a second conductive structure, wherein the spacer structure, the first dielectric structure, and the third dielectric structure contact the second conductive structure.

The foregoing has outlined features of many embodiments so that those skilled in the art may better understand the disclosure from a variety of aspects. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. Various changes, substitutions, or alterations to the disclosure may be made without departing from the spirit and scope of the disclosure.

Various operations of embodiments are provided herein. The order of some or all of the operations described should not be construed as to imply that these operations are dependent on a particular order. Alternative sequences will be appreciated with the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. In addition, it will be understood that not all operations are necessary.

It will be appreciated that in one or more embodiments, the layers, features, elements, etc. depicted herein are shown with particular dimensions relative to each other for purposes of simplicity and ease of understanding, and their actual dimensions are substantially different from those shown herein. In addition, there are various techniques for forming the layer features, elements, etc. mentioned herein, such as etching techniques, implantation techniques, doping techniques, spin-on techniques, sputtering techniques (e.g., magnetron sputtering or ion beam sputtering), growth techniques (e.g., thermal growth), or deposition techniques (e.g., CVD, PVD, PECVD, or ALD).

Moreover, "exemplary" is used herein to mean serving as an example, instance, illustration, or the like, and is not necessarily advantageous. As used in this disclosure, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, the use of "a" and "an" in this disclosure and the appended claims is generally to be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. In addition, at least one of A and B, etc. generally refers to A or B or both A and B. Furthermore, to the extent that the terms "includes," has, "" exists, "or variations thereof are used, such terms are intended to be inclusive in a manner similar to the term" comprising. In addition, "first," "second," etc. are not intended to imply temporal aspects, spatial aspects, order, etc., unless stated otherwise. Rather, such terms are used merely as identifications, names, etc. of features, elements, items, etc. For example, a first element and a second element typically correspond to element a and element B or two different or two identical elements or the same element.

Further, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations, and is limited only by the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.