阅读说明：本技术 一种具有屏蔽缓冲结构的mosfet管 (MOSFET (Metal-oxide-semiconductor field Effect transistor) tube with shielding buffer structure ) 是由 尹海军 于 2021-02-26 设计创作，主要内容包括：本发明系提供一种具有屏蔽缓冲结构的MOSFET管,包括衬底,衬底上层叠有外延层和钝化层,外延层中设有间隔设置的漏极层和源极层,漏极层与源极层之间位置的下方设有嵌入调节层,钝化层上设有栅极金属层,漏极层上连接有贯穿钝化层的漏极金属层,源极层上连接有贯穿钝化层的源极金属层；栅极金属层的上方设有屏蔽盖,屏蔽盖外包围有位于钝化层上的绝缘填充层,屏蔽盖包括盖板和侧包围板,盖板与栅极金属层之间连接有绝缘缓冲柱,栅极金属层、漏极金属层和源极金属层均位于侧包围板的包围中。本发明开启电压小,形成的导电沟道宽度大,导通电流大；MOSFET管工作时的抗干扰性能好,绝缘缓冲柱能够有效提高抗震性能。(The invention provides a MOSFET (metal-oxide-semiconductor field effect transistor) tube with a shielding buffer structure, which comprises a substrate, wherein an epitaxial layer and a passivation layer are stacked on the substrate, a drain electrode layer and a source electrode layer which are arranged at intervals are arranged in the epitaxial layer, an embedded adjusting layer is arranged below the position between the drain electrode layer and the source electrode layer, a grid metal layer is arranged on the passivation layer, a drain electrode metal layer penetrating through the passivation layer is connected onto the drain electrode layer, and a source electrode metal layer penetrating through the passivation layer is connected onto the; the top of grid metal level is equipped with the shielding lid, and the shielding lid surrounds outward to have the insulating filling layer that is located on the passivation layer, and the shielding lid is connected with insulating buffering post including apron and side envelope board between apron and the grid metal level, and grid metal level, drain electrode metal level and source electrode metal level all are arranged in the surrounding of side envelope board. The invention has small starting voltage, large width of the formed conductive channel and large conduction current; the anti-interference performance of MOSFET pipe during operation is good, and insulating buffer column can effectively improve anti-seismic performance.)

1. The MOSFET tube with the shielding buffer structure is characterized by comprising a substrate (10), wherein an epitaxial layer (11) and a passivation layer (12) are stacked on the substrate (10), a drain layer (20) and a source layer (30) are arranged in the epitaxial layer (11) at intervals, an embedded adjusting layer (40) wrapped in the epitaxial layer (11) is arranged below the position between the drain layer (20) and the source layer (30), a gate metal layer (50) is arranged on the passivation layer (12), the gate metal layer (50) is arranged above the position between the drain layer (20) and the source layer (30), a drain metal layer (21) penetrating through the passivation layer (12) is connected onto the drain layer (20), and a source metal layer (31) penetrating through the passivation layer (12) is connected onto the source layer (30);

a shielding cover (60) is arranged above the gate metal layer (50), an insulating filling layer (70) located on the passivation layer (12) is surrounded outside the shielding cover (60), the shielding cover (60) comprises a cover plate (61) and a side surrounding plate (62), the cover plate (61) is located right above the gate metal layer (50), the drain metal layer (21) and the source metal layer (31), an insulating buffer column (71) is connected between the cover plate (61) and the gate metal layer (50), the side surrounding plate (62) is connected to the periphery of the shielding cover (60), and the gate metal layer (50), the drain metal layer (21) and the source metal layer (31) are all located in the surrounding of the side surrounding plate (62);

the substrate (10) and the epitaxial layer (11) are both semiconductor material layers doped with ions of a first conductivity type, and the drain layer (20), the source layer (30) and the insulating buffer layer (72) are all semiconductor material layers doped with ions of a second conductivity type, wherein the polarities of the first conductivity type and the second conductivity type are opposite.

2. MOSFET-tube with a shielding buffer structure according to claim 1, characterized in that a buried insulating layer (111) is further provided between the substrate (10) and the epitaxial layer (11).

3. The MOSFET tube with a shielding buffer structure of claim 1, wherein the drain metal layer (21), the source metal layer (31) and the gate metal layer (50) are all tungsten metal layers or cobalt metal layers.

4. The MOSFET tube of claim 1, wherein the shield cap (60) is an aluminum metal cap.

5. The MOSFET tube with a shielding buffer structure of claim 1, wherein a conducting plate (63) is connected between the side surrounding plate (62) and the source metal layer (31).

6. The MOSFET tube with a shielding buffer structure of claim 1, wherein an anti-tamper spacer (64) is fixed under the cap plate (61), the anti-tamper spacer (64) is located between the gate metal layer (50) and the drain metal layer (21), and a bottom of the anti-tamper spacer (64) is located on the passivation layer (12).

7. The MOSFET tube with a shielding buffer structure of claim 1, wherein the passivation layer (12) is a silicon dioxide layer or a silicon nitride layer.

8. The MOSFET tube with a shielding buffer structure of claim 1, wherein the insulating fill layer (70) is a polyimide layer or a silicon nitride layer.

9. The MOSFET tube with a shielding buffer structure of claim 1, wherein the top surface of the insulating fill layer (70) is covered with a buffer layer.

Technical Field

The invention relates to a MOSFET (metal oxide semiconductor field effect transistor) tube, and particularly discloses a MOSFET tube with a shielding buffer structure.

Background

The MOSFET is a metal-oxide semiconductor field effect transistor, can be used for an amplifying circuit, can also be used as a variable resistor or an electronic switch, can be used for exchanging a source electrode and a drain electrode, can be used for positive and negative grid voltage, and has good flexibility and convenient use.

The MOSFET is divided into an enhancement type and a depletion type, when no voltage is applied to the enhancement type MOSFET, the drain electrode and the source electrode are clamped off, when a certain voltage is applied to the grid electrode, most current carriers in the substrate are repelled to move away from the grid electrode, and therefore a conductive channel for communicating the drain electrode and the source electrode is formed on the top of the substrate.

Disclosure of Invention

Therefore, it is necessary to provide a MOSFET having a shielding buffer structure, which has a small turn-on voltage, a large on-current, and a small influence from external electromagnetic radiation, in view of the problems in the prior art.

In order to solve the prior art problem, the invention discloses a MOSFET tube with a shielding buffer structure, which comprises a substrate, wherein an epitaxial layer and a passivation layer are stacked on the substrate, a drain layer and a source layer which are arranged at intervals are arranged in the epitaxial layer, an embedded adjusting layer wrapped in the epitaxial layer is arranged below the position between the drain layer and the source layer, a grid metal layer is arranged on the passivation layer and is positioned above the position between the drain layer and the source layer, the drain layer is connected with the drain metal layer penetrating through the passivation layer, and the source layer is connected with the source metal layer penetrating through the passivation layer;

a shielding cover is arranged above the grid metal layer, an insulating filling layer positioned on the passivation layer is surrounded outside the shielding cover, the shielding cover comprises a cover plate and a side surrounding plate, the cover plate is positioned right above the grid metal layer, the drain metal layer and the source metal layer, an insulating buffer column is connected between the cover plate and the grid metal layer, the side surrounding plate is connected to the periphery of the shielding cover, and the grid metal layer, the drain metal layer and the source metal layer are all positioned in the surrounding of the side surrounding plate;

the substrate and the epitaxial layer are all semiconductor material layers doped with first conduction type ions, the drain electrode layer, the source electrode layer and the insulating buffer layer are all semiconductor material layers doped with second conduction type ions, and the polarities of the first conduction type and the second conduction type are opposite.

Furthermore, a buried insulating layer is arranged between the substrate and the epitaxial layer.

Furthermore, the drain metal layer, the source metal layer and the gate metal layer are all tungsten metal layers or cobalt metal layers.

Further, the shielding cover is an aluminum metal cover.

Furthermore, a conduction plate is connected between the side wrapping plate and the source electrode metal layer.

Furthermore, an anti-interference partition plate is fixed below the cover plate and located between the grid metal layer and the drain metal layer, and the bottom of the anti-interference partition plate is located on the passivation layer.

Further, the passivation layer is a silicon dioxide layer or a silicon nitride layer.

Further, the insulating filling layer is a polyimide layer or a silicon nitride layer.

Further, the top surface of the insulating filling layer is covered with a buffer layer.

The invention has the beneficial effects that: the invention discloses a MOSFET tube with a shielding buffer structure.A special embedded adjusting layer is arranged in an epitaxial layer, partial current carriers positioned below a drain electrode layer and a source electrode layer can be consumed, the starting voltage is small, and after corresponding voltage is applied to a grid electrode, the formed conducting channel has large width, large conducting current and good working performance; in addition, the shielding cover structure is arranged at the top, electromagnetic radiation reaching the interior of the MOSFET can be effectively weakened, the anti-interference performance of the MOSFET during working is good, and the anti-seismic performance of the whole structure can be effectively improved through the insulating buffer column between the shielding cover and the grid metal layer.

Drawings

FIG. 1 is a schematic structural diagram of the present invention.

Reference numerals: the semiconductor device includes a substrate 10, an epitaxial layer 11, a buried insulating layer 111, a passivation layer 12, a drain layer 20, a drain metal layer 21, a source layer 30, a source metal layer 31, an embedding adjustment layer 40, a gate metal layer 50, a shielding cover 60, a cover plate 61, a side surrounding plate 62, a conducting plate 63, an anti-interference spacer 64, an insulating filling layer 70, an insulating buffer pillar 71, and a buffer layer 72.

Detailed Description

For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

Refer to fig. 1.

The embodiment of the invention discloses a MOSFET tube with a shielding buffer structure, which comprises a substrate 10, wherein an epitaxial layer 11 and a passivation layer 12 are stacked on the substrate 10, a drain layer 20 and a source layer 30 which extend towards the inside of the epitaxial layer 11 and are arranged at intervals are arranged in the epitaxial layer 11, an embedded adjusting layer 40 which is completely wrapped in the epitaxial layer 11 is arranged below the position between the drain layer 20 and the source layer 30, preferably, the whole structure of a depletion layer formed between the embedded adjusting layer 40 and the epitaxial layer 11 is positioned right below the drain layer 20 and the source layer 30, the reliable pinch-off state of the MOSFET tube can be effectively ensured, a gate metal layer 50 is arranged on the passivation layer 12, the gate metal layer 50 is positioned above the position between the drain layer 20 and the source layer 30, a drain metal layer 21 which penetrates through the passivation layer 12 is connected on the drain layer 20, and a source metal layer 31 which penetrates through the passivation layer 12 is, the gate metal layer 50 is not in contact with either the source metal layer 31 or the drain metal layer 21;

a shielding cover 60 is arranged above the gate metal layer 50, an insulating filling layer 70 positioned on the passivation layer 12 is surrounded outside the shielding cover 60, the insulating filling layer 70 further covers the gate metal layer 50, the drain layer 20 and the gate metal layer 50, the shielding cover 60 comprises a cover plate 61 and a side surrounding plate 62, the cover plate 61 is positioned right above the gate metal layer 50, the drain metal layer 21 and the source metal layer 31, an insulating buffer column 71 positioned in the insulating filling layer 70 is connected between the cover plate 61 and the gate metal layer 50, the stability of the position between the shielding cover 60 and a lower interlayer structure thereof can be effectively improved through the insulating buffer column 71, and the anti-seismic performance of the MOSFET tube can be effectively improved when the MOSFET tube is impacted by the outside, preferably, the insulating buffer column 71 is a rubber column, the side surrounding plate 62 is connected around the shielding cover 60, and the gate metal layer 50, the drain metal layer 21 and the source metal layer 31 are all positioned in the surrounding of the side surrounding plate, and the gate metal layer 50, the drain metal layer 21 and the source metal layer 31 are not in contact with the side surrounding plate 62; the substrate 10 and the epitaxial layer 11 are both semiconductor material layers doped with first conductivity type ions, the drain layer 20, the source layer 30 and the insulating buffer layer 72 are semiconductor material layers doped with second conductivity type ions, the polarities of the first conductivity type and the second conductivity type are opposite, that is, when the first conductivity type and the second conductivity type are p-type and n-type respectively, or the first conductivity type and the second conductivity type are n-type and p-type respectively, the n-type ions generally adopt phosphorus ions, arsenic ions or antimony ions, the p-type ions generally adopt boron ions, and the semiconductor material generally adopts monocrystalline silicon or silicon carbide.

According to the MOSFET, a conducting channel can be formed between the drain electrode layer 20 and the source electrode layer 30, when corresponding forward voltage or reverse voltage is applied to the grid metal layer 50 of the MOSFET according to the conducting types of the epitaxial layer 11, the drain electrode layer 20 and the source electrode layer 30, electrons or holes in the top area of the epitaxial layer 11 are repelled by an electric field in a grid, and the electrons or holes in the area move downwards, so that the conducting channel is formed to communicate the drain electrode layer 20 and the source electrode layer 30, when the first conducting type is p-type and the second conducting type is n-type, the voltage applied to the grid of the MOSFET is forward voltage, and an electric field from top to bottom is formed at the grid; there is depletion layer structure between embedding regulation layer 40 and epitaxial layer 11, when exerting corresponding voltage in order to form the conduction channel to the MOSFET pipe, be formed with the activity space of stepping down for corresponding charged particle on the embedding regulation layer 40, can effectively hold the first conductivity type ion between drain layer 20 and source layer 30, under the effect of grid metal layer 50, the first conductivity type ion between drain layer 20 and source layer 30 can transfer to embedding regulation layer 40 on more rapidly and efficiently, and can effectively improve the width of conduction channel, thereby effectively improve the conduction current of MOSFET pipe, the turn-on voltage is little, more can adapt to the application demand of microelectronic product. When the MOSFET transistor is pinched off, since the embedded adjustment layer 40 is located below the position between the drain layer 20 and the source layer 30, the acting force on the first conductivity type ions at the top position of the epitaxial layer 11 is extremely small, and when the embedded adjustment layer is not affected by the gate metal layer 50, the position of the first conductivity type ions above the position between the drain layer 20 and the source layer 30 is stable, and the pinch-off effect is reliable. The shielding cover 60 is effective in attenuating electromagnetic radiation reaching the interior of the MOSFET tube, thereby effectively ensuring reliable operation of the interior structure of the MOSFET tube.

In the present embodiment, a buried insulating layer 111 is further disposed between the substrate 10 and the epitaxial layer 11, and the buried insulating layer 111 is a buried oxide layer.

In this embodiment, the drain metal layer 21, the source metal layer 31, and the gate metal layer 50 are all tungsten metal layers or cobalt metal layers, and may also be aluminum metal layers.

In the present embodiment, the shielding cover 60 is an aluminum metal cover, and aluminum has a good shielding function and heat dissipation performance.

In the present embodiment, the conducting plate 63 is connected between the side surrounding plate 62 and the source metal layer 31, and the shielding effect of the shielding cover 60 on electromagnetic radiation can be effectively improved by connecting the side surrounding plate 62 and the source metal layer 31 through the conducting plate 63.

In this embodiment, an anti-interference partition plate 64 is fixed below the cover plate 61, the anti-interference partition plate 64 is located between the gate metal layer 50 and the drain metal layer 21, the anti-interference partition plate 64 is not in contact with the gate metal layer 50 and the drain metal layer 21, the bottom of the anti-interference partition plate 64 is located on the passivation layer 12, the electric field in the drain metal layer 21 region can be effectively prevented from affecting the gate region through the anti-interference partition plate 64, and the reliability of the gate in adjusting the conductive channel is ensured.

In the present embodiment, the passivation layer 12 is a silicon dioxide layer or a silicon nitride layer.

In the present embodiment, the insulating filling layer 70 is a polyimide layer or a silicon nitride layer.

In this embodiment, the top surface of the insulating filling layer 70 is covered with the buffer layer 72, the top surface of the cover plate 61 is coplanar with the top surface of the insulating filling layer 70, the buffer layer 72 is further covered on the cover plate 61, so that the shock-proof and buffering performance of the overall MOSFET transistor structure can be effectively improved, and preferably, the buffer layer 72 is a silica gel buffer layer.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.