阅读说明：本技术 一种半导体对准结构、制造方法及其掩膜版组 (Semiconductor alignment structure, manufacturing method and mask set thereof ) 是由 陈宏� 于 2021-01-22 设计创作，主要内容包括：本发明提供的一种半导体对准结构、制造方法及其掩膜版组,其制造方法通过在第一介质层中的第一通孔中形成第一插塞,第一插塞覆盖第一通孔的内壁,且第一插塞的厚度小于所述第一通孔的深度；在第一介质层和第一插塞上形成第一金属层,第一金属层的厚度以及第一插塞的厚度之和小于第一通孔的深度,使得所述第二插塞的底部是与介质层刻蚀选择比高的第一金属层,不易在第二插塞的边缘下陷而形成沟槽,避免了平坦度差的问题,且由于形成了第二插塞,提高了对位标记的准确度。(The invention provides a semiconductor alignment structure, a manufacturing method and a mask set thereof, wherein the manufacturing method comprises the steps of forming a first plug in a first through hole in a first dielectric layer, covering the inner wall of the first through hole by the first plug, and enabling the thickness of the first plug to be smaller than the depth of the first through hole; and forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole, so that the bottom of the second plug is the first metal layer with a high etching selection ratio with the dielectric layer, and a groove is not easy to sink at the edge of the second plug to form, thereby avoiding the problem of poor flatness.)

1. A method for manufacturing a semiconductor alignment structure is characterized by comprising the following steps:

providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;

etching the first dielectric layer to form a first through hole, wherein the bottom of the first through hole is exposed out of the surface of the semiconductor substrate;

forming a first plug in the first through hole, wherein the first plug covers the inner wall of the first through hole, and the thickness of the first plug is smaller than the depth of the first through hole;

forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole;

forming a second dielectric layer on the first metal layer, and forming a second through hole in the second dielectric layer, wherein the second through hole exposes the surface of the first metal layer above the first through hole; and

and forming a second plug in the second through hole, wherein the second plug covers the inner wall of the second through hole, and the thickness of the second plug is smaller than the depth of the second through hole.

2. The method of claim 1, wherein the first via has an aperture of 4 μm to 8 μm.

3. The method of claim 2, wherein the first plug has a thickness of

4. The method of claim 3, wherein the first plug is made of tungsten and the second plug is made of tungsten.

5. The method of fabricating the semiconductor alignment structure of any of claims 1 to 4, wherein the first metal layer has a thickness of

6. The method of manufacturing a semiconductor alignment structure of any of claims 1 to 4, wherein the first dielectric layer has a thickness ofThe thickness of the second dielectric layer is

7. The method of fabricating a semiconductor alignment structure according to any of claims 1 to 4, wherein the second via hole has a diameter of 1 μm to 3 μm.

8. The method of fabricating the semiconductor alignment structure of any of claims 1 to 4, wherein the second plug has a thickness of

9. A semiconductor alignment structure manufactured by the method for manufacturing a semiconductor alignment structure according to any one of claims 1 to 8, comprising a semiconductor substrate, a first dielectric layer, a first plug, a first metal layer, a second dielectric layer and a second plug, wherein the first dielectric layer and the first plug are formed on the semiconductor substrate; the first metal layer is positioned on the first dielectric layer and covers the inner wall of the first plug; the second plug is positioned on the surface of the first metal layer above the first plug, the projection of the second plug on the semiconductor substrate is positioned inside the projection of the first plug on the semiconductor substrate, and the bottom of the second plug is in contact with the surface of the first metal layer.

10. A mask set used in the method for manufacturing the semiconductor alignment structure according to any one of claims 1 to 8, comprising:

the first dielectric mask is provided with a first window and is used for defining a region for forming a first through hole when the first dielectric layer is etched;

the second medium mask is provided with a second window and is used for defining a region for forming a second through hole when the second medium layer is etched; and

wherein the aperture of the second window is not larger than the aperture of the first window.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor alignment structure, a manufacturing method and a mask set thereof.

Background

At present, in the process of manufacturing an integrated circuit, a complete chip usually needs to be subjected to more than tens of times of photoetching, and the photoetching of the rest layers except the first photoetching is performed by aligning the patterns left by the previous layer. In the prior art, the Alignment mark is usually identified by using EGA (enhanced Global Alignment), and the Alignment mark is required to have better signal contrast.

Generally, the formed steps, trenches, etc. can be used as alignment marks in the photolithography process. There are two important criteria for evaluating the quality of the alignment marks: firstly, the alignment mark has stable and good mark morphology in the process; secondly, a stronger signal can be detected when alignment is carried out by utilizing the alignment mark. The signal contrast of the alignment marks may also be different for integrated circuit processes at different process nodes.

Taking EF90(90 nm embedded flash process platform) as an example, as shown in fig. 1, a first metal layer 11 and an interlayer dielectric layer (ILD)12 are sequentially formed on a substrate 10, a conductive plug (CT)13 is formed in the ILD 12, and then a patterned second metal layer 14 is formed by using a groove at the plug 13 as an alignment mark. Due to the load effect, the thickness of the interlayer dielectric layer 12 at the alignment mark for EGA recognition is small, so that when the via hole in the interlayer dielectric layer 12 is filled with a metal material to form the plug 13, the via hole is easily filled, which causes a weak alignment signal of the alignment mark, and further causes a deviation when the second metal layer 14 and the plug 13 are aligned.

To solve the above problem, the inventors studied a new EGA layout, as shown in fig. 2, by removing the first metal layer 11 and thickening the thickness of the dielectric layer 12, a plug 13 is directly formed on the substrate 10. Since the dielectric layer 12 is made of silicon dioxide, a micro-channel effect exists during etching, and therefore in the chip manufactured in the manner, although the through hole is not filled with a metal material to form the plug 13, the through hole has a certain recess depth, and thus an alignment signal of the alignment mark is improved. However, after the second metal layer 14 is formed on the formed plug 13, the bottom side of the plug 13 is deeper than the depth of the recess in the middle, i.e. a small trench is formed at the bottom of the plug 13, so that the flatness of the bottom of the plug 13 is inferior to that of the bottom of a plug formed at the same position on other chip fabrication process platforms.

Disclosure of Invention

The invention aims to provide a semiconductor alignment structure, a manufacturing method and a mask set thereof, which are used for solving the problem of how to improve the flatness of the bottom of a plug under the condition of ensuring the accuracy of a plug alignment mark.

In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor alignment structure, including the steps of:

providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;

etching the first dielectric layer to form a first through hole, wherein the bottom of the first through hole is exposed out of the surface of the semiconductor substrate;

forming a first plug in the first through hole, wherein the first plug covers the inner wall of the first through hole, and the thickness of the first plug is smaller than the depth of the first through hole;

forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole;

forming a second dielectric layer on the first metal layer, and forming a second through hole in the second dielectric layer, wherein the second through hole exposes the surface of the first metal layer above the first through hole; and

and forming a second plug in the second through hole, wherein the second plug covers the inner wall of the second through hole, and the thickness of the second plug is smaller than the depth of the second through hole.

Optionally, the aperture of the first through hole is 4 μm to 8 μm.

Optionally, the thickness of the first plug is

Optionally, the first plug is made of tungsten, and the second plug is made of tungsten.

Optionally, the thickness of the first metal layer is

Optionally, the thickness of the first dielectric layer isThe thickness of the second dielectric layer is

Optionally, the aperture of the second through hole is 1 μm to 3 μm.

Optionally, the second plug has a thickness of

On the other hand, the invention also provides a semiconductor alignment structure which is manufactured by the manufacturing method of the semiconductor alignment structure and comprises a semiconductor substrate, a first dielectric layer, a first plug, a first metal layer, a second dielectric layer and a second plug, wherein the first dielectric layer and the first plug are formed on the semiconductor substrate; the first metal layer is positioned on the first dielectric layer and covers the inner wall of the first plug; the second plug is positioned on the surface of the first metal layer above the first plug, the projection of the second plug on the semiconductor substrate is positioned inside the projection of the first plug on the semiconductor substrate, and the bottom of the second plug is in contact with the surface of the first metal layer.

In another aspect, the present invention further provides a mask set applied in the method for manufacturing the semiconductor alignment structure, including:

the first dielectric mask is provided with a first window and is used for defining a region for forming a first through hole when the first dielectric layer is etched;

the second medium mask is provided with a second window and is used for defining a region for forming a second through hole when the second medium layer is etched; and

wherein the aperture of the second window is not larger than the aperture of the first window.

Compared with the prior art, the method has the following beneficial effects:

the invention provides a semiconductor alignment structure, a manufacturing method and a mask set thereof, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate; etching the first dielectric layer to form a first through hole, wherein the bottom of the first through hole is exposed out of the surface of the semiconductor substrate; forming a first plug in the first through hole, wherein the first plug covers the inner wall of the first through hole, and the thickness of the first plug is smaller than the depth of the first through hole; forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole; forming a second dielectric layer on the first metal layer, and forming a second through hole in the second dielectric layer, wherein the second through hole exposes the surface of the first metal layer above the first through hole; and forming a second plug in the second through hole, wherein the second plug covers the inner wall of the second through hole, and the thickness of the second plug is smaller than the depth of the second through hole. According to the invention, the first metal layer is formed under the second plug, so that in subsequent etching, the bottom of the second plug is the first metal layer with high etching selectivity with the dielectric layer, a groove is not easy to sink at the edge of the second plug, the problem of poor flatness is avoided, and the accuracy of alignment marking is improved due to the formation of the second plug.

Drawings

FIG. 1 is a schematic structural diagram of an EGA layout in the prior art;

FIG. 2 is a schematic structural diagram of an EGA layout with a first metal layer removed;

FIG. 3 is a flow chart of a method for fabricating a semiconductor alignment structure according to an embodiment of the present invention;

fig. 4a to 4f are schematic structural diagrams of the semiconductor alignment structure corresponding to each step in the method for manufacturing the semiconductor alignment structure according to an embodiment of the invention.

The reference numerals are explained below:

in fig. 1 and 2:

10-a substrate; 11-a first metal layer; 12-an interlayer dielectric layer; 13-a plug; 14-a second metal layer;

in FIGS. 4a-4 f:

100-a semiconductor substrate;

210-a first dielectric layer; 211 — a first via; 220-a second dielectric layer; 221-a second via;

310-a first plug; 320-a first metal layer; 330-second plug.

Detailed Description

A semiconductor alignment structure, a method of manufacturing the same, and a reticle set thereof according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.

Fig. 3 is a flowchart of a method for manufacturing a semiconductor alignment structure according to this embodiment. As shown in fig. 3, the present embodiment provides a method for manufacturing a semiconductor alignment structure, which includes the following steps:

step S10: providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate;

step S20: etching the first dielectric layer to form a first through hole, wherein the bottom of the first through hole is exposed out of the surface of the semiconductor substrate;

step S30: forming a first plug in the first through hole, wherein the first plug covers the inner wall of the first through hole, and the thickness of the first plug is smaller than the depth of the first through hole;

step S40: forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole;

step S50: forming a second dielectric layer on the first metal layer, and forming a second through hole in the second dielectric layer, wherein the second through hole exposes the surface of the first metal layer above the first through hole; and

step S60: and forming a second plug in the second through hole, wherein the second plug covers the inner wall of the second through hole, and the thickness of the second plug is smaller than the depth of the second through hole.

A method for fabricating a semiconductor alignment structure disclosed in this embodiment is described in more detail below with reference to fig. 3-4 f.

As shown in fig. 4a, step S10 is performed to provide a semiconductor substrate 100, and a first dielectric layer 210 is formed on the semiconductor substrate 100.

In the present embodiment, the semiconductor substrate 100 may provide an operation platform for a subsequent process, and may be any substrate known to those skilled in the art for carrying components of a semiconductor integrated circuit, such as a bare die, or a wafer processed by an epitaxial growth process, and in detail, the semiconductor substrate 100 may be, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon (bulk silicon) substrate, a germanium substrate, a silicon-germanium substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator (ge) substrate.

The first dielectric layer 210 covers the surface of the semiconductor substrate 100, andthe first dielectric layer 210 may be silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, or a porous dielectric layer formed by using a liquid colloidal silicon oxide-based material. In this embodiment, the first dielectric layer 210 is a silicon dioxide layer. The method for forming the first dielectric layer 210 may be chemical vapor deposition or plasma enhanced chemical vapor deposition. The first dielectric layer 210 is formed to a thickness ofFor example, can beOrAnd the like.

As shown in fig. 4b, next, in step S20, the first dielectric layer 210 is etched to form a first through hole 211, and the bottom of the first through hole 211 exposes the surface of the semiconductor substrate 100. Specifically, a first dielectric mask is used to define a region where the first through hole 211 is formed. The aperture of the first through hole 211 is 4 to 8 μm.

As shown in fig. 4c, next, step S30 is performed to form a first plug 310 in the first through hole 211, where the first plug 310 covers the inner wall (bottom wall and side wall) of the first through hole 211, and the thickness of the first plug 310 is smaller than the depth of the first through hole 211. The material of the first plug 310 may be metal, and specifically may be tungsten. The thickness of the first plug is, for example, such that For example, can beOr

As shown in fig. 4d, step S40 is performed to form a first metal layer 320 on the first dielectric layer 210 and the first plug 310, wherein the sum of the thickness of the first metal layer 320 in the first via 211 and the thickness of the first plug 310 is less than the depth of the first via 211.

Wherein the thickness of the first metal layer 320 is, for exampleFor example, can beOr

The first metal layer 320 is located above the first plug 310 and below the second plug 330, so that in the subsequent etching process, the etching selectivity of the dielectric layer to the first metal layer 320 is high, and the etching stops on the surface of the first metal layer 320, thereby avoiding the problem of poor flatness.

As shown in fig. 4e, step S50 is performed to form a second dielectric layer 220 on the first metal layer 320, and form a second via hole 221 in the second dielectric layer 220, wherein the second via hole 221 exposes the surface of the first metal layer 320 above the first via hole 211.

In particular, the method comprises the following steps of,

first, a second dielectric layer 220 is formed on the first metal layer 320 by chemical vapor deposition or plasma enhanced chemical vapor deposition. The second dielectric layer 220 may be made of silicon oxide, fluorine-doped silicon oxide, carbon-doped silicon oxide, or a porous dielectric layer formed by using a liquid colloidal silicon oxide-based material. In this embodiment, the material of the second dielectric layer 220 is the same as that of the first dielectric layer 210. The second dielectric layer is formed with a thickness ofFor example, can beOr

Then, a second dielectric mask is used to define an area for forming the second via hole 221, and the second dielectric layer 220 is etched to form the second via hole 221. Wherein the aperture of the second through hole 221 is 1 μm to 3 μm. The projection of the second via hole 221 on the semiconductor substrate 100 is located inside the projection of the first via hole 211 on the semiconductor substrate 100, that is, the second via hole 221 exposes the surface of the first metal layer 320 above the first via hole 211, preferably, the first via hole 211 and the second via hole 221 have the same shape, the second via hole 221 is located at the center of the first via hole 211, and the opening of the second via hole 221 is located above the opening of the first via hole 211 (that is, a partial depth of the second via hole 221 is located in the first via hole 211), so that at least a part of the second plug 330 to be formed later is exposed above the first via hole 211.

As shown in fig. 4f, next, step S60 is performed to form a second plug 330 in the second through hole 221, where the second plug 330 covers an inner wall of the second through hole 221, and a thickness of the second plug 330 is smaller than a depth of the second through hole 221.

Specifically, the second via hole 221 is filled with a metal material to form a second plug 330, and the second plug 330 covers a sidewall and a bottom wall of the second via hole 221 and forms a cavity in the second via hole 221. In this embodiment, the second plug 260 is also a tungsten plug. The thickness of the second plug 260 is, for exampleFor example, can beOr

The semiconductor alignment structure manufactured in the above manner includes a semiconductor substrate 100, a first dielectric layer 210, a first plug 310, a first metal layer 320, a second dielectric layer 220, and a second plug 330, wherein the first dielectric layer 210 and the first plug 310 are formed on the semiconductor substrate 100; the first metal layer 320 is located on the first dielectric layer 210 and covers the inner wall of the first plug 310; the second plug 330 is located on the surface of the first metal layer 320 above the first plug 310, the projection of the second plug 330 on the semiconductor substrate 100 is located inside the projection of the first plug 310 on the semiconductor substrate 100, and the bottom of the second plug 330 is in contact with the surface of the first metal layer 320. In the semiconductor alignment structure provided by this embodiment, since the first metal layer 320 is located at the bottom of the second plug 330, the edge of the second plug 330 does not sag to form a trench, thereby avoiding the problem of poor flatness and improving the accuracy of alignment marks.

In the manufacturing method of the semiconductor alignment structure provided by the embodiment, the etching process in each step is realized by using different masks, and the masks form a mask group. Specifically, the mask set includes:

the first dielectric mask is provided with a first window and is used for defining a region for forming a first through hole when the first dielectric layer is etched;

the second medium mask is provided with a second window and is used for defining a region for forming a second through hole when the second medium layer is etched;

wherein the aperture of the second window is not larger than the aperture of the first window. The manufacturing method of the semiconductor alignment structure of the embodiment is realized by adopting fewer masks, and the process cost is reduced.

In summary, the semiconductor alignment structure, the manufacturing method and the mask set thereof provided by the present invention include the following steps: providing a semiconductor substrate, and forming a first dielectric layer on the semiconductor substrate; etching the first dielectric layer to form a first through hole, wherein the bottom of the first through hole is exposed out of the surface of the semiconductor substrate; forming a first plug in the first through hole, wherein the first plug covers the inner wall of the first through hole, and the thickness of the first plug is smaller than the depth of the first through hole; forming a first metal layer on the first dielectric layer and the first plug, wherein the sum of the thickness of the first metal layer and the thickness of the first plug is less than the depth of the first through hole; forming a second dielectric layer on the first metal layer, and forming a second through hole in the second dielectric layer, wherein the second through hole exposes the surface of the first metal layer above the first through hole; and forming a second plug in the second through hole, wherein the second plug covers the inner wall of the second through hole, and the thickness of the second plug is smaller than the depth of the second through hole. According to the invention, the second plug is formed on the first metal layer, so that the bottom of the second plug is the first metal layer with high etching selectivity with the dielectric layer, a groove is not easy to sink at the edge of the second plug, the problem of poor flatness is avoided, and the accuracy of alignment marking is improved due to the formation of the second plug.

In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.