阅读说明：本技术 半导体设备封装及其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 陈亭瑞 廖国成 于 2020-04-17 设计创作，主要内容包括：本发明提供一种半导体设备封装,其包含衬底、支撑结构及第一天线。所述衬底具有第一表面及与所述第一表面相对的第二表面。所述支撑结构安置于所述衬底的所述第一表面上。所述第一天线安置于所述支撑结构上。所述第一天线具有面向所述衬底的第一表面、与所述第一表面相对的第二表面,及在所述第一天线的所述第一表面与第二表面之间延伸的侧向表面。所述第一天线的所述侧向表面暴露于所述半导体设备封装的外部。所述第一天线包含介电层及安置于所述介电层内且穿透所述介电层的天线图案。(A semiconductor device package includes a substrate, a support structure, and a first antenna. The substrate has a first surface and a second surface opposite the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the substrate, a second surface opposite the first surface, and a lateral surface extending between the first and second surfaces of the first antenna. The lateral surface of the first antenna is exposed to an exterior of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer.)

1. A semiconductor device package, comprising:

a substrate having a first surface and a second surface opposite the first surface;

a support structure disposed on the first surface of the substrate; and

a first antenna disposed on the support structure, the first antenna having a first surface facing the substrate, a second surface opposite the first surface, and a lateral surface extending between the first and second surfaces of the first antenna,

wherein the lateral surface of the first antenna is exposed to an outside of the semiconductor device package, and

wherein the first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer.

2. The semiconductor device package of claim 1, wherein

The dielectric layer of the first antenna pattern has a first surface facing away from the substrate and a second surface opposite the first surface;

the antenna pattern of the first antenna pattern has a first surface facing away from the substrate and a second surface opposite to the first surface;

the first surface of the dielectric layer is substantially coplanar with the first surface of the antenna pattern; and is

The second surface of the dielectric layer is substantially coplanar with the second surface of the antenna pattern.

3. The semiconductor device package of claim 1, further comprising:

a conductive layer disposed within the dielectric layer of the first antenna; and

a conductive via disposed within the support structure and electrically connecting the conductive layer with the substrate.

4. The semiconductor device package of claim 1, wherein the dielectric layer and the support structure of the first antenna are formed from a molding compound.

5. The semiconductor device package of claim 1, further comprising a second antenna disposed on the first antenna, wherein the second antenna includes:

a support structure disposed on the first antenna;

a dielectric layer disposed on the support structure of the second antenna; and

an antenna pattern disposed within and penetrating the dielectric layer of the second antenna.

6. The semiconductor device package of claim 5, wherein the antenna pattern of the first antenna is substantially aligned with the antenna pattern of the second antenna.

7. The semiconductor device package of claim 1, wherein

The antenna pattern of the first antenna comprises a first portion and a second portion; and is

The width of the first portion is greater than the width of the second portion.

8. The semiconductor device package of claim 1, wherein the support structure has a lateral surface that is substantially coplanar with the lateral surface of the first antenna.

9. A semiconductor device package, comprising:

a substrate having a first surface and a second surface opposite the first surface; and

a first antenna disposed on the first surface of the substrate, the first antenna having a dielectric layer and an antenna pattern, the dielectric layer having a first surface facing away from the substrate, a second surface opposite and spaced apart from the first surface of the substrate, and a third surface in contact with the first surface of the substrate,

wherein the antenna pattern is disposed within the dielectric layer and exposed from the first and second surfaces of the dielectric layer.

10. The semiconductor apparatus package of claim 9, wherein the first surface of the substrate and the first antenna define an air cavity.

11. The semiconductor device package of claim 9, wherein

The antenna pattern of the first antenna pattern has a first surface facing away from the substrate and a second surface opposite to the first surface;

the first surface of the dielectric layer is substantially coplanar with the first surface of the antenna pattern; and is

The second surface of the dielectric layer is substantially coplanar with the second surface of the antenna pattern.

12. The semiconductor device package of claim 9, further comprising a second antenna disposed on the first antenna, the second antenna having a first surface facing away from the first antenna, a second surface facing the first antenna and spaced apart from the first antenna, and a third surface in contact with the first surface of the first antenna, wherein the antenna pattern of the second antenna is disposed within and exposed from the first and second surfaces of the dielectric layer of the second antenna.

13. The semiconductor device package of claim 12, wherein the antenna pattern of the first antenna is substantially aligned with the antenna pattern of the second antenna.

14. A method of manufacturing a semiconductor device package, comprising:

(a) providing a vector;

(b) forming an antenna layer on the carrier;

(c) forming a first dielectric layer on the carrier to cover the antenna layer and expose an upper surface of the antenna layer; and

(d) a second dielectric layer is formed on the first dielectric layer and adjacent to a periphery of the first dielectric layer to expose the antenna layer.

15. The method of claim 14, wherein operation (c) further comprises:

forming the first dielectric layer on the carrier to completely cover the antenna layer; and

thinning the first dielectric layer to expose the upper surface of the antenna layer.

16. The method of claim 14, wherein operation (d) further comprises:

forming a first sacrificial layer on the upper surface of the antenna layer exposed from the first dielectric layer;

forming a second dielectric layer on a portion of the dielectric layer exposed from the first sacrificial layer; and

removing the first sacrificial layer to expose the upper surface of the antenna layer.

17. The method of claim 14, wherein the antenna layer comprises a first antenna pattern and a second antenna pattern.

18. The method of claim 17, wherein a projection of the second dielectric layer on the carrier is spaced apart from a projection of the first antenna pattern on the carrier.

19. The method of claim 17, further comprising:

removing the carrier to expose a lower surface of the first antenna pattern opposite the upper surface of the antenna pattern and a surface of the first dielectric layer that is substantially coplanar with the lower surface of the first antenna pattern;

forming a second sacrificial layer on the lower surface of the first antenna; and

forming a second antenna pattern on the second sacrificial layer,

wherein the second antenna pattern is substantially aligned with the first antenna pattern.

20. The method of claim 19, further comprising:

forming a third dielectric layer on the surface of the first dielectric layer, the third dielectric layer covering a first portion of the lateral surface of the second sacrificial layer and exposing a second portion of the lateral surface of the second sacrificial layer and a surface of the second antenna pattern facing away from the first antenna pattern; and

removing the second sacrificial layer to form an air cavity between the first and second antenna patterns.

Technical Field

The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same.

Background

Wireless communication apparatuses, such as cellular telephones, typically include an antenna for transmitting and receiving Radio Frequency (RF) signals. In recent years, with the continuous development of mobile communication and the urgent need for high data rate and stable communication quality, relatively high frequency wireless transmission (e.g., 28GHz or 60GHz) has become one of the most important subjects in the mobile communication industry. In a comparative approach, an antenna is disposed within or on a dielectric layer, and an RF signal is transmitted or received by the antenna through the dielectric layer. However, signal attenuation or signal loss of the transmitted RF signal in the dielectric layer becomes a critical issue due to the increase in frequency of the transmitted or received RF signal.

Disclosure of Invention

In one or more embodiments, a semiconductor device package includes a substrate, a support structure, and a first antenna. The substrate has a first surface and a second surface opposite the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the substrate, a second surface opposite the first surface, and a lateral surface extending between the first and second surfaces of the first antenna. The lateral surface of the first antenna is exposed to an exterior of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within and penetrating the dielectric layer.

In one or more embodiments, a semiconductor device package includes a substrate and a first antenna. The substrate has a first surface and a second surface opposite the first surface. The first antenna is disposed on the first surface of the substrate. The first antenna has a dielectric layer and an antenna pattern. The dielectric layer has a first surface facing away from the substrate, a second surface opposite the first surface and spaced apart from the first surface of the substrate, and a third surface in contact with the first surface of the substrate. The antenna pattern is disposed within the dielectric layer and exposed from the first and second surfaces of the dielectric layer.

In one or more embodiments, a method of manufacturing a semiconductor device package includes (a) providing a carrier; (b) forming an antenna layer on the carrier; (c) forming a first dielectric layer on the carrier to cover the antenna layer and expose an upper surface of the antenna layer; and (d) forming a second dielectric layer on the first dielectric layer and adjacent to a periphery of the first dielectric layer to expose the antenna layer.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale and that the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1B illustrates a perspective view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1C illustrates a cross-sectional view of an antenna structure, according to some embodiments of the present disclosure.

Fig. 1D illustrates a cross-sectional view of an antenna structure according to some embodiments of the present disclosure.

Fig. 1E illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2C illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L are cross-sectional views of antenna structures fabricated at various stages according to some embodiments of the present disclosure.

Fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K', 4L, 4M, and 4N are cross-sectional views of antenna structures fabricated at various stages according to some embodiments of the present disclosure.

Common reference numbers are used throughout the figures and embodiments to indicate the same or similar elements. The present disclosure will become more apparent from the following embodiments, taken in conjunction with the accompanying drawings.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples and arrangements of components are described below. Of course, these components and arrangements are merely examples and are not intended to be limiting. In the present disclosure, reference in the following description to an embodiment in which a first feature is formed over or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Fig. 1A illustrates a cross-sectional view of a semiconductor device package 1A, according to some embodiments of the present disclosure. Semiconductor device package 1A includes substrate 10, support structure 11, antenna 12, electronic component 14, and electrical contacts 15.

For example, the substrate 10 may be a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer impregnated fiberglass based copper foil laminate. The substrate 10 may include opposing surfaces 101 and 102 (e.g., upper and lower surfaces). The substrate 10 may include an interconnect structure (e.g., an electrical connection), such as a redistribution layer (RDL). The substrate 10 may include metal layers 10c1 and 10c2 on its surfaces 101 and 102, respectively. In some embodiments, metal layer 10c1 is a ground plane.

The support structure 11 is disposed on a surface 101 of the substrate 10. For example, the support structure 11 is connected to the surface 101 of the substrate 10 via a connection element 10 a. In some embodiments, the support structure 11 is formed of or includes a dielectric material. For example, the support structure 11 may comprise a molding compound, pre-impregnated composite fibers (e.g., prepreg), Borophosphosilicate Glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, Undoped Silicate Glass (USG), any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins that include a filler dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials/sheets.

An antenna 12 is disposed on the support structure 11. The antenna 12 is spaced from the surface 101 of the substrate 10. For example, there is a gap between the antenna 12 and the substrate 10. The antenna 12 includes a dielectric layer 12d and an antenna pattern 12 a. The antenna pattern 12p is embedded within the dielectric layer 12d and exposed from the surfaces 12d1 and 12d2 of the dielectric layer 12 d. For example, the surface 12p1 of the antenna pattern 12p is substantially coplanar with the surface 12d1 of the dielectric layer 12d, and the surface 12p2 of the antenna pattern 12p is substantially coplanar with the surface 12d2 of the dielectric layer 12 d. For example, the thickness of the antenna pattern 12p is substantially the same as the thickness of the dielectric layer 12 d. For example, the surfaces 12p1 and 12p2 of the antenna pattern 12a are exposed to the air. For example, the surfaces 12p1 and 12p2 of the antenna pattern 12a directly contact the air. In some embodiments, the semiconductor device package 1A is disposed in a vacuum space or a vacuum chamber, and thus the surfaces 12p1 and 12p2 of the antenna pattern 12a are exposed to a vacuum. In some embodiments, antenna pattern 12p is or includes a conductive material, such as a metal or metal alloy. Examples of the conductive material include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof.

The antenna pattern 12p may be electrically connected to the metal layer 10c1 via a connection structure 12 f. In some embodiments, the connection structure 12f may act as a feed element to provide a signal to the antenna pattern 12 p. In some embodiments, the connection structure 12f connects the antenna pattern 12p to ground by means of the metal layer 10c 1. In some embodiments, the connection structures 12f may include, but are not limited to, solder balls, metal posts, bond wires, or stacked vias. In some embodiments, the connection structure 12f includes Au, Ag, Al, Cu, or alloys thereof. In some embodiments, the connection structure 12f is omitted, and the metal layer 10c1 may be electromagnetically coupled with the antenna pattern 12 p. In some embodiments, metal layer 10c1 and antenna 12 may be referred to as an antenna structure.

In some embodiments, antenna pattern 12p may include a uniform width as shown in fig. 1A. In some embodiments, as shown in fig. 1C and 1D (which illustrate cross-sectional views of the antenna 12 according to some embodiments of the present disclosure), the antenna pattern 12p includes a non-uniform width. For example, as shown in fig. 1C, the width of the surface 12p1 of the antenna pattern 12p is greater than the width of the surface 12p2 of the antenna pattern 12 p. For example, as shown in fig. 1D, the width of the antenna pattern 12p between the surface 12p1 and the surface 12p2 is greater than the width of the surface 12p1 or 12p2 of the antenna pattern 12 p.

A dielectric layer 12d is disposed on the support structure 11. In some embodiments, the dielectric layer 12d is in direct contact with the support structure 11. In some embodiments, the dielectric layer 12d has a lateral surface 12d3 exposed to air. In some embodiments, the lateral surface 12d3 of the dielectric layer 12d is exposed to the outside of the semiconductor device package 1A. In some embodiments, the lateral surface 12d3 of the dielectric layer 12d is substantially coplanar with the lateral surface 113 of the support structure 11. In some embodiments, the dielectric layer 12d may comprise a molding compound, pre-impregnated composite fibers (e.g., prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins that include a filler dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials/sheets. In some embodiments, the dielectric layer 12d and the support structure 11 are formed of or comprise the same material. For example, both the dielectric layer 12d and the support structure 11 are formed from a molding compound. Alternatively, the dielectric layer 12d and the support structure 11 are formed of different materials. In some embodiments, the antenna 12 and the support structure 11 may be collectively referred to as an antenna structure.

In some embodiments, as shown in fig. 1A and 1B (which illustrate perspective views of a semiconductor device package 1A as shown in fig. 1A), the substrate 10, the support structure 11, and the antenna 12 define an air gap. For example, there is no dielectric material between the antenna 12 and the metal plate 10c 1. Thus, the RF signal is transmitted or received by the antenna 12 via the air. Since the Df/Dk of air (i.e., 0/1) is lower than the Df/Dk of any dielectric material, signal attenuation or signal loss of the RF signal may be reduced, which will improve the performance of the antenna 12 (e.g., more preferably by a factor of 1.3 to 2.3). In addition, since the antenna pattern 12p is not required to be connected to the dielectric layer in a direction perpendicular to the surface 12p1 or 12p2 of the antenna pattern 12p, the surfaces 12p1 and 12p2 of the antenna pattern 12p are relatively smooth (for example, roughness is not required on the surfaces 12p1 and 12p2 of the antenna pattern 12 p), which will improve the performance of the antenna 12.

Referring back to fig. 1A, the electronic component 14 is disposed on the surface 102 of the substrate 10 and is electrically connected to the substrate 10 by, for example, flip-chip or wire bonding techniques. The electronic component 14 may be a chip or die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit apparatus may include active devices such as transistors and/or passive devices such as resistors, capacitors, inductors, or combinations thereof.

The electrical contacts 15 are disposed on the surface 102 of the substrate 10 and electrically connected to the metal layer 10c2 exposed from the protective layer 10s (e.g., solder mask or solder resist). In some embodiments, the electrical contacts 15 are solder balls. In other embodiments, the electrical contacts 15 may be copper posts or any other suitable electrical contacts.

Fig. 1E illustrates a cross-sectional view of a semiconductor device package 1E, according to some embodiments of the present disclosure. The semiconductor device package 1E is similar to the semiconductor device package 1A as shown in fig. 1A, and differences therebetween are described below.

The antenna 12 further includes a conductive layer 12p1 disposed within the dielectric layer 12 d. The support structure 11 includes a through hole 11v penetrating the support structure 11 and electrically connecting the conductive layer 12p1 to the substrate 10 (e.g., to the connection element 10 a). In some embodiments, the perforations 11v comprise Au, Ag, Al, Cu, or alloys thereof. The perforations 11v may enhance the strength of the support structure 11.

Fig. 2A illustrates a cross-sectional view of a semiconductor device package 2A, according to some embodiments of the present disclosure. The semiconductor apparatus package 2A is similar to the semiconductor apparatus package 1A as shown in fig. 1A, except that the semiconductor apparatus package 2A further includes an antenna structure (including a support structure 21 and an antenna 22) disposed on the antenna 12.

The support structure 21 is disposed on the surface 12d1 of the dielectric layer 12 d. In some embodiments, the support structure 21 is formed of or includes a dielectric material. For example, the support structure 21 may include a molding compound, pre-impregnated composite fibers (e.g., prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins that include a filler dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials/sheets.

An antenna 22 is disposed on the support structure 21. The antenna 22 is spaced from the antenna 12 via the support structure 21. For example, there is a gap between the antenna 12 and the antenna 22. The antenna 22 includes a dielectric layer 22d and an antenna pattern 22 a. The antenna pattern 22p is embedded within the dielectric layer 22d and exposed from the surfaces 22d1 and 22d2 of the dielectric layer 22 d. For example, the surface 22p1 of the antenna pattern 22p is substantially coplanar with the surface 22d1 of the dielectric layer 22d, and the surface 22p2 of the antenna pattern 22p is substantially coplanar with the surface 22d2 of the dielectric layer 22 d. For example, the thickness of the antenna pattern 22p is substantially the same as the thickness of the dielectric layer 22 d. For example, the surfaces 22p1 and 22p2 of the antenna pattern 22a are exposed to the air. For example, the surfaces 22p1 and 22p2 of the antenna pattern 22a directly contact the air. In some embodiments, semiconductor device package 2A is disposed in a vacuum space or a vacuum cavity, and thus surfaces 22p1 and 22p2 of antenna pattern 22A are exposed to a vacuum. In some embodiments, the antenna pattern 22p is or includes a conductive material, such as a metal or metal alloy. Examples of the conductive material include Au, Ag, Al, Cu, or an alloy thereof.

The antenna pattern 22p is substantially aligned with the antenna pattern 11 p. The antenna pattern 22p is electromagnetically coupled to the antenna pattern 12 p. In some embodiments, the antenna pattern 22p may include a uniform width as shown in fig. 2. In some embodiments, antenna pattern 22p may include a shape as shown in fig. 1C or fig. 1D, depending on different design requirements.

A dielectric layer 22d is disposed on the support structure 21. In some embodiments, the dielectric layer 22d is in direct contact with the support structure 21. In some embodiments, the dielectric layer 22d has a lateral surface 22d3 exposed to air. In some embodiments, the lateral surface 22d3 of the dielectric layer 22d is exposed to the outside of the semiconductor device package 2A. In some embodiments, the lateral surface 22d3 of the dielectric layer 22d is substantially coplanar with the lateral surface 12d3 of the dielectric layer 12d and the lateral surface 213 of the support structure 21. In some embodiments, the dielectric layer 22d may comprise a molding compound, pre-impregnated composite fibers (e.g., prepreg), BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins that include a filler dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepreg materials/sheets. In some embodiments, the dielectric layer 22d and the support structure 21 are formed of or comprise the same material. For example, both the dielectric layer 22d and the support structure 21 are formed from a molding compound. Alternatively, the dielectric layer 22d and the support structure 21 are formed of different materials.

Fig. 2B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure. The semiconductor device package in fig. 2B is similar to the semiconductor device package 2A as shown in fig. 2A, and differences therebetween are described below.

The antenna 22 further includes a conductive layer 22p1 disposed within the dielectric layer 22 d. Support structure 21 includes a through hole 21v penetrating support structure 21 and electrically connecting conductive layer 22p1 to conductive layer 12p 1. In some embodiments, the perforations 21v comprise Au, Ag, Al, Cu, or alloys thereof. The perforations 21v may enhance the strength of the support structure 21.

Fig. 2C illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure. The semiconductor device package in fig. 2C is similar to the semiconductor device package 2A as shown in fig. 2A, except that the antenna 22 in fig. 2C further includes an opening 22h penetrating the dielectric layer 22d of the antenna 22 to expose the antenna 12. In some embodiments, the opening 22h is located adjacent to the perimeter of the antenna 22.

Fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L are cross-sectional views of antenna structures fabricated at various stages according to some embodiments of the present disclosure. The various figures have been simplified for a preferred understanding of aspects of the disclosure. The operations shown in fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L are methods for fabricating an antenna structure including the support structure 11 and the antenna 12. Alternatively, the operations shown in fig. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, and 3L are methods for fabricating other antenna structures.

Referring to fig. 3A, a carrier 39 is provided. The carrier 39 may be a metal plate, such as a copper plate. In some embodiments, carrier 39 has a seed layer 39s disposed on both surfaces thereof. A patterned photoresist 39a (e.g., a mask) is disposed on the carrier 39.

Referring to fig. 3B, an antenna pattern 12p is formed on a carrier 39. In some embodiments, antenna pattern 12p is formed by, for example, sputtering, coating, electroplating, or any other suitable operation. In some embodiments, a portion of the antenna pattern 12p (e.g., the portion circled by the dotted circle 12m 1) may be used as an alignment mark.

Referring to fig. 3C, the photoresist 39a is removed from the carrier 39. A dielectric layer 12D' is then formed on the antenna pattern 12p as shown in fig. 3D to completely cover the antenna pattern 12 p. For example, a dielectric layer 12d' is formed on the outer surface of the antenna pattern 12p and within the gap defined by the antenna pattern 12 p.

Referring to fig. 3E, a portion of the dielectric layer 12d' is removed to form a dielectric layer 12d, thereby exposing an upper surface of the antenna pattern 12 p. In some embodiments, the upper surface of the antenna pattern 12p is substantially coplanar with the upper surface of the dielectric layer 12 d. In some embodiments, the upper surface of the antenna pattern 12p is recessed from the upper surface of the dielectric layer 12 d. In some embodiments, the upper surface of the antenna pattern 12p protrudes beyond the upper surface of the dielectric layer 12 d. In some embodiments, portions of the dielectric layer 12d' are removed by, for example, etching, grinding, laser, or any other suitable operation.

Referring to fig. 3F, a photoresist 39b (e.g., a dry film) is disposed on the antenna pattern 12p and the dielectric layer 12d to cover the antenna pattern 12p and the dielectric layer 12 d. Subsequently, a portion of the photoresist 39 is removed as shown in fig. 3G to form a photoresist 39 b'.

Referring to fig. 3H, a protective layer 11' (e.g., a dielectric layer) is formed to cover the photoresist 39' and a portion of the dielectric layer 12d exposed from the photoresist 39 '. A portion of the protective layer 11' is then removed, for example by grinding, as shown in fig. 3I, to form the support structure 11.

Referring to fig. 3J, the carrier 39 is removed. In some embodiments, the seed layer 39s may remain on the dielectric layer 12d and the antenna pattern 12 p. Subsequently, the seed layer 39s may be removed, for example by etching or any other suitable process, as shown in fig. 3K.

Referring to fig. 3L, the photoresist 39' is removed, such as by development or any other suitable process, to form the antenna structure including the support structure 11 and the antenna 12 as shown in fig. 1A.

Fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M, and 4N are cross-sectional views of antenna structures fabricated at various stages according to some embodiments of the present disclosure. The various figures have been simplified for a preferred understanding of aspects of the disclosure. In some embodiments, the operations shown in fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M, and 4N are methods for fabricating an antenna structure including the support structures 11, 21 and the antennas 12, 22 as shown in fig. 2C. Alternatively, the operations shown in fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, 4L, 4M, and 4N are methods for fabricating other antenna structures.

In some embodiments, the operations in fig. 4A are carried out after the operations of fig. 3I. Referring to fig. 4A, the carrier 39 including the seed layer 39s is removed.

Referring to fig. 4B, a photoresist 39c (e.g., a dry film) is formed on the dielectric layer 12d and the surface of the antenna pattern 12p opposite to the photoresist 39B'.

Referring to fig. 4C, a portion of the photoresist 39C is removed to form a photoresist 39C'. In some embodiments, the photoresist 39c 'is substantially aligned with the photoresist 39 b'.

Referring to fig. 4D, a seed layer 12s is formed on the photoresist 39c' and the exposed portion of the antenna pattern 12p and the dielectric layer 12D. Subsequently, a photoresist 39d is formed on the seed layer 12s as shown in fig. 4E.

Referring to fig. 4F, a portion of the photoresist 39d is removed to form an opening 39dh, thereby exposing the seed layer 12 s. Subsequently, a metal layer 22p' is formed within the opening 39dh to contact the seed layer 12s as shown in fig. 4G.

Referring to fig. 4H and 4I, portions of the photoresist 39d, the seed layer 12s, and the metal layer 22p' are removed as shown in fig. 4I to form the antenna pattern 22 p.

Referring to fig. 4J, a photoresist 39e (e.g., a dry film) is formed to cover the dielectric layer 12d, the antenna pattern 12p, the photoresist 39c', and the antenna pattern 22 p. In some embodiments, the photoresist 39e and the photoresists 39b ', 39c' comprise different types of photoresists. For example, if the resist 39e is a positive resist, the resists 39b 'and 39c' are negative resists, and vice versa.

Referring to fig. 4K, a portion of the photoresist 39e is removed to form a photoresist 39 e'. As shown in fig. 4K and 4K ', the photoresist 39e ' is positioned adjacent to the edge of the photoresist 39c '.

Referring to fig. 4L, a protective layer (e.g., dielectric layer) 22' is formed to cover the dielectric layer 12d, the antenna pattern 12p, the photoresist 39c ', the antenna pattern 22p, and the photoresist 39e '.

Referring to fig. 4M, a portion of the protective layer 22' is removed to form the support structure 22 and expose the antenna pattern 22 p.

Referring to fig. 4N, the photoresist 39b ', 39C ', and 39e ' is removed, such as by development or any other suitable process, to form an antenna structure including the support structures 11, 21 and antennas 12, 22 as shown in fig. 2C.

As used herein, spatially relative terms, such as "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

As used herein, the terms "substantially," "generally," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to the instance in which the event or circumstance occurs specifically as well as the instance in which the event or circumstance occurs in close approximation. As used herein with respect to a defined value or range, the term "about" generally means within ± 10%, ± 5%, ± 1%, or ± 0.5% of the defined value or range. Ranges may be expressed herein as from one end point to the other end point or between the two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces that are within a few micrometers (μm) along the same plane (e.g., within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm along the same plane). Where numerical values or properties are said to be "substantially" identical, the term can refer to the values being within ± 10%, ± 5%, ± 1% or ± 0.5% of the mean of the values.

As used herein, the terms "substantially," "generally," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to the instance in which the event or circumstance occurs specifically as well as the instance in which the event or circumstance occurs in close approximation. For example, when used in conjunction with numerical values, the term can refer to a variation of less than or equal to ± 10% of the numerical value, such as a variation of less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" or "about" the same if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ± 10 ° relative to 0 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, "substantially perpendicular" may refer to a range of ± 10 ° with respect to 90 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

For example, two surfaces may be considered coplanar or substantially coplanar if the shift between the two surfaces is equal to or below 5 μm, equal to or below 2 μm, equal to or below 1 μm, or equal to or below 0.5 μm. A surface may be considered planar or substantially planar if the displacement between any two points on the surface relative to the surface of the plate is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.

As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to carry an electrical current. Conductive materials generally indicate those materials that exhibit little or zero resistance to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the conductive material is of greater than about 10⁴S/m (e.g. at least 10)⁵S/m or at least 10⁶S/m) of electrical conductivityAnd (5) feeding. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intervening components are located between the former and the latter.

Unless otherwise specified, spatial descriptions such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like are directed to the orientation shown in the drawings. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not so arranged.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The description may not be drawn to scale. There may be a distinction between artistic reproduction in the present disclosure and actual equipment due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it may be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present disclosure.