阅读说明：本技术 混合的杂混接合结构及形成混合的杂混接合结构的方法 (Hybrid junction structures and methods of forming hybrid junction structures ) 是由 S.利夫 A.埃尔舍比尼 J.斯万 N.楚诺达 姚计敏 于 2020-06-24 设计创作，主要内容包括：本发明的主题是“混合的杂混接合结构及形成混合的杂混接合结构的方法”。实施例包括混合的杂混接合结构,所述混合的杂混接合结构包括复合介电层,其中复合介电层包括具有多个无机填充材料的有机介电材料。一个或多个导电衬底互连结构在复合介电层内。管芯在复合介电层上,所述管芯在管芯介电材料内具有一个或多个导电管芯互连结构。一个或多个导电管芯互连结构直接接合到一个或多个导电衬底互连结构,并且复合介电层的无机填充材料接合到管芯介电材料。(The subject of the invention is a hybrid junction structure and a method of forming a hybrid junction structure. Embodiments include a hybrid junction structure including a composite dielectric layer, wherein the composite dielectric layer includes an organic dielectric material having a plurality of inorganic filler materials. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are bonded directly to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.)

1. A microelectronic structure, comprising:

a substrate bonding layer comprising:

a composite dielectric layer comprising an organic dielectric material and an inorganic filler material; and

one or more conductive substrate interconnect structures within the composite organic dielectric layer; and

a die comprising a die-bonding layer, the die-bonding layer comprising:

a die dielectric layer; and

one or more conductive die interconnect structures within the die dielectric layer, wherein the die bonding layer is in direct contact with the substrate bonding layer, and wherein at least one of the one or more conductive substrate interconnect structures is in direct contact with at least one of the one or more conductive die interconnect structures.

2. The microelectronic structure of claim 1, wherein at least one of the conductive die interconnect structure or the conductive substrate interconnect structure has a Coefficient of Thermal Expansion (CTE) at least 30% greater than a CTE of the composite organic dielectric layer in a direction perpendicular to a bonding interface between the substrate bonding layer and the die bonding layer.

3. The microelectronic structure of claim 1, further comprising a coating in direct contact with the composite dielectric layer and in direct contact with the die dielectric layer.

4. The microelectronic structure of claim 3, wherein the coating has a thickness between 10nm and 1600 nm.

5. The microelectronic structure of claim 1, wherein the organic dielectric material comprises one or more of an epoxy material or a spin-on-glass material, and wherein the inorganic filler material comprises one or more of silica, a silsesquioxane material, silicon nitride, silicon carbide, alumina, or diamond, and wherein the organic dielectric material comprises between about 70% by weight and about 95% by weight of the inorganic filler material.

6. The microelectronic structure of claim 5, wherein the die dielectric layer comprises an inorganic dielectric material.

7. The microelectronic structure of claim 1, wherein at least a portion of the inorganic filler material is covalently bonded to the inorganic dielectric layer of the die bonding layer.

8. The microelectronic structure of claim 1, wherein the one or more conductive die interconnect structures include a first conductive die interconnect structure adjacent a second conductive die interconnect structure, wherein a pitch between the first conductive die interconnect structure and the second conductive die interconnect structure is less than 50 microns.

9. The microelectronic structure of claim 1, wherein the top surface of the substrate bonding layer, the top surface of the die bonding layer and the top surface of the one or more conductive die interconnect structures and the one or more conductive die interconnect structures are free of solder and free of underfill material.

10. A microelectronic structure, comprising:

a package substrate;

a dielectric layer on the package substrate, wherein at least a portion of the dielectric layer includes an inorganic filler material within an organic dielectric material;

one or more conductive substrate interconnect structures within the organic dielectric layer;

a die comprising a die-bonding layer, the die-bonding layer comprising:

a die dielectric layer; and

one or more conductive die interconnect structures within the die dielectric layer, wherein the die bonding layer is directly on the dielectric layer, wherein the one or more conductive substrate interconnect structures are directly on the one or more conductive die interconnect structures.

11. The microelectronic structure of claim 10, wherein the die dielectric layer comprises a die organic dielectric material, wherein an inorganic filler material is within the die organic dielectric material, and wherein the dielectric layer comprises an organic dielectric material, wherein an inorganic filler material is within the organic dielectric material.

12. The microelectronic structure of claim 10, wherein the dielectric layer comprises: a first portion comprising an organic dielectric material, wherein an inorganic filler material is within the first portion of the organic dielectric material; and a second portion comprising an inorganic dielectric material free of an inorganic filler material, wherein the second portion is covalently bonded to the die dielectric layer, and wherein the inorganic filler material of the first portion is covalently bonded to the die dielectric layer.

13. The microelectronic structure of claim 12, wherein the first portion comprises between 70% by weight and 95% by weight of the inorganic filler material.

14. The microelectronic structure of claim 10, wherein the one or more conductive substrate interconnect structures and the one or more conductive die interconnect structures are free of a seed layer at an interface plane.

15. The microelectronic structure of claim 10, wherein the microelectronic structure is communicatively coupled to one or more of a central processing unit, a field programmable gate array, a system-on-a-chip, or a graphics processing unit, or a combination thereof.

16. A method of forming a microelectronic structure, comprising:

forming a dielectric material on a substrate, wherein at least a portion of the dielectric material comprises an organic dielectric material comprising a plurality of inorganic filler materials;

forming one or more conductive substrate interconnect structures within the dielectric material;

attaching a die to a top surface of the dielectric material, wherein the die includes one or more conductive die interconnect structures within a die dielectric material; and

wherein the attaching comprises directly bonding one or more conductive die interconnect structures to the one or more conductive substrate interconnect structures and directly bonding the die dielectric material to at least the inorganic fill material.

17. The method of forming the microelectronic structure of claim 16, wherein forming the dielectric material further comprises: forming an inorganic dielectric layer on the organic dielectric layer by utilizing one or more of a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a Chemical Vapor Deposition (CVD) process, a pulsed laser annealing process, or a spin-on-glass process, a transfer or compression molding process, or a vacuum lamination process, wherein the inorganic dielectric layer comprises a thickness of 10nm to 1600 nm.

18. The method of forming the microelectronic structure of claim 16, wherein forming the dielectric material on at least a portion of the substrate comprises:

forming an organic dielectric material comprising a plurality of inorganic filler materials on a first portion of the substrate, an

Forming an inorganic dielectric material on a second portion of the substrate adjacent to the first portion of the substrate, wherein the organic dielectric material comprises between 70% by weight and 95% by weight of the inorganic filler material.

19. The method of forming the microelectronic structure of claim 16, wherein the die dielectric material comprises an organic dielectric material, wherein an inorganic filler material is within the organic dielectric material.

20. The method of forming the microelectronic structure of claim 16, wherein forming the dielectric material comprises forming an organic dielectric material having a Coefficient of Thermal Expansion (CTE) in a direction perpendicular to a bonding interface between the organic dielectric material and the die, wherein the CTE of at least one of the conductive die interconnect structure or the conductive substrate interconnect structure in the direction perpendicular to the bonding interface is at least about 30% greater than the CTE of the organic dielectric material.

21. The method of forming the microelectronic structure of claim 17, wherein forming the dielectric material comprises forming one or more of a molding material, an epoxy material, or a spin-on glass material, or a build-up film filled with the inorganic fill material, wherein the inorganic fill material comprises one or more of silica, a silsesquioxane material, silicon nitride, silicon carbide, alumina, or a diamond material, and wherein the dielectric material comprises between 70% by weight and 90% by weight of the inorganic fill material.

Drawings

In the drawings, the materials described herein are illustrated by way of example and not by way of limitation. For simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the drawings:

FIGS. 1A-1E illustrate cross-sectional views of a hybrid binding structure according to an embodiment;

1F-1K illustrate cross-sectional and perspective views of a portion of a package structure including a hybrid junction structure, according to an embodiment;

2A-2G illustrate cross-sectional views of a method of fabricating a package structure having a hybrid bonding structure, according to an embodiment;

3A-3F illustrate cross-sectional views of a method of fabricating a package structure with a hybrid junction structure according to an embodiment;

4A-4H illustrate cross-sectional views of a method of fabricating a package structure with a hybrid junction structure according to an embodiment;

FIG. 5 illustrates a flow diagram of a method of fabricating a hybrid junction structure according to an embodiment;

FIG. 6 is a functional block diagram of a computing device having a hybrid junction structure, according to an embodiment.

Detailed Description

One or more embodiments are described with reference to the drawings. Although specific configurations and arrangements are discussed and depicted in detail, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to one skilled in the relevant art that the techniques and/or arrangements described herein may be employed in a variety of other systems and applications, in addition to those detailed herein.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. In addition, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of the features in the figures. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the claimed subject matter is defined only by the appended claims and equivalents thereof.

In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art that the embodiments herein may be practiced without these specific details. In some instances, well-known methods and apparatus are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments herein. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment herein. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment in any event that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) or in physical or electrical contact with each other, and/or that two or more elements are in cooperation or interaction with each other (e.g., as in a cause and effect relationship).

The terms "above …," "below …," "between …," and "above …" as used herein refer to the relative position of one component or material with respect to other components or materials, where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed above or below another material may be in direct contact, or may have one or more intervening materials. Also, one material disposed between two materials or materials may be in direct contact with the two layers, or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with the second material/material. Similar distinctions are made in the context of assembly of components.

As used throughout this description and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "A, B or at least one of C" may mean a; b; c; a and B; a and C; b and C; or A, B and C.

The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially", "close", "approximately", "close" and "approximately" typically refer to within +/-10% of a target value.

Various implementations of embodiments herein may be formed or performed on a substrate, such as a package substrate. In some embodiments, the package substrate may include any suitable type of substrate capable of providing electrical communication between an electrical component, such as an Integrated Circuit (IC) die, and a next level component to which the IC package may be coupled, such as, for example, a circuit board. In other embodiments, the substrate may comprise any suitable type of substrate capable of providing electrical communication between the IC die and an upper IC package coupled to a lower IC/die package, and in some embodiments, the substrate may comprise any suitable type of substrate capable of providing electrical communication between the upper IC package and a next level component to which the IC package is coupled.

The substrate may also provide structural support for the device (such as a die). For example, in some embodiments, the substrate may comprise a multilayer substrate built up around a core layer (dielectric or metallic core) -comprising alternating layers of dielectric material and metal, and may include a through via structure extending through the core. In other embodiments, the substrate may comprise a coreless multi-layer substrate, in which case the via structure may not be present. Other types of substrates and substrate materials may also be used with the disclosed embodiments (e.g., ceramic, sapphire, glass, etc.). Furthermore, according to some embodiments, the substrate may include alternating layers of dielectric material and metal that are built up on the die itself — this process is sometimes referred to as a "bumpless build-up process. With this approach, conductive interconnects may or may not be needed (as in some cases build-up layers may be provided directly on the die/device).

In some embodiments, the die may include a front side and an opposing back side, and may be an integrated circuit die and/or an integrated circuit device. In some embodiments, one or both of the front side or the back side of the die may be referred to as the "active surface" of the die. A plurality of interconnects may extend from the front and/or back surfaces of the die to the underlying and/or overlying substrates, respectively, and these interconnects may electrically couple the die and one or more substrates. In some cases, the die may be directly coupled to a board, such as a motherboard. The interconnects/traces may comprise any type of structure and material capable of providing electrical communication between the die and the substrate/board. In some embodiments, the die may be disposed on the substrate in a flip-chip arrangement. In some embodiments, the interconnect includes conductive terminals (e.g., pads, bumps, stud bumps, columns, pillars, or other suitable structures or combinations of structures) on the die and corresponding conductive terminals (e.g., pads, bumps, stud bumps, columns, pillars, or other suitable structures or combinations of structures) on the substrate.

Solder (e.g., in the form of balls or bumps) may be on the terminals of the substrate and/or die, and these terminals may then be connected, for example, using a solder reflow process. Of course, it should be understood that many other types of interconnects and materials are possible (e.g., wire bonds extending between the die and the substrate). In some embodiments herein, the die may be coupled with the substrate in a flip-chip arrangement through a plurality of interconnects. However, in other embodiments, alternative structures and/or methods may be utilized to couple the die to the substrate, wherein solder may not be used, as will be further described herein.

Described herein are embodiments of microelectronic package structures having hybrid, hybrid junction interfaces. In an embodiment, the composite organic dielectric layer may be on a substrate (such as, for example, a low CTE carrier substrate). The composite organic dielectric layer may comprise an organic dielectric layer filled with an inorganic filler material, such as, for example, silica. One or more conductive substrate interconnect structures may be disposed within the composite organic dielectric layer. A die may be on the composite organic dielectric layer, the die having one or more conductive die interconnect structures within the die dielectric material/layer. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic fill material of the composite organic dielectric material is directly (e.g., covalently) bonded to the die dielectric material, wherein the covalent bonding occurs after subsequent temperature processing of the microelectronic package structure. The metal-to-metal bonding of the conductive interconnect structure (which occurs after the dielectric covalent bond is created) is accomplished without the use of solder or underfill materials. The composite organic dielectric layer includes a CTE in a direction perpendicular to the bonding interface that is substantially lower than a CTE of the conductive interconnect structures of the die and the substrate. For pitches well below 50 microns, pitch scaling between die interconnect structures is achieved.

The composite organic dielectric layer may have a CTE in a direction perpendicular to the bonding interface plane that is substantially lower than the CTE of the conductive interconnect structures of the die and the substrate. The CTE of the composite organic dielectric layer in the in-plane direction may be optimized to reduce CTE mismatch between the die and the substrate. By reducing CTE mismatch, yield and reliability are improved, and interconnect pitch can be reduced. Direct metal-to-metal bonding of the conductive substrate interconnect structure to the conductive die interconnect structure is achieved without the use of solder or underfill material after the dielectric bond between the two interface surfaces is formed. For pitches below 50 microns, pitch scaling between die interconnect structures is achieved.

FIG. 1A is a cross-sectional view of a portion of a hybrid junction structure 10 arranged in accordance with some embodiments of the present disclosure. The hybrid bonded structure 10 includes a substrate 104 and a die 114. The die 114, which may include any suitable type of die/device, may include any number of circuit elements, such as any type of transistor elements and/or passive elements. Die 114 may include N-type and/or P-type transistors, which may include materials such as, for example, silicon, germanium, indium, antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The die may include structures such as planar and/or non-planar transistors, FinFET transistors, nanowire transistors, and/or nanoribbon transistors.

The die 114 may include a die bonding layer 120. In an embodiment, the die-bonding layer may include an inorganic dielectric material 116, the inorganic dielectric material 116 having a conductive die interconnect structure 118 disposed therein. The inorganic dielectric material 116 may comprise any suitable inorganic dielectric material, such as, for example, an inorganic dielectric material comprising silicon, nitrogen, carbon, or oxygen, and combinations thereof. One or more conductive die interconnect structures 118 may be within the inorganic dielectric layer 116. The one or more conductive die interconnect structures 118 may include any suitable conductive material, such as, for example, copper, ruthenium, titanium, tantalum, or cobalt, and combinations thereof. Each of the one or more conductive die interconnect structures 118 may include a surface 126. In an embodiment, the surface 126 may be slightly recessed below the surface 124 of the dielectric material 116 of the die-bonding layer 120. For example, in some cases, surface 126 may be about 1nm to about 10nm below surface 124 of die dielectric material 116.

The one or more conductive die interconnect structures 118 are separated from each other by the inorganic dielectric material 116. In an embodiment, the spacing 129 between adjacent ones of the conductive die interconnect structures 118 may comprise about 50 microns or less. In other embodiments, pitch 129 may be greater than 50 microns, depending on the particular application. The substrate 104 may include a substrate bonding layer 102 on a platform 119. The platform 119 may comprise any suitable platform such as a carrier or handle wafer, and may comprise materials such as silicon, glass materials, III-V materials, or multiple layers of organic materials on a low CTE carrier. The substrate bonding layer 102 of the substrate 104 may include a composite organic dielectric layer 107 and one or more conductive substrate interconnect structures 112. The one or more conductive substrate interconnect structures 112 may comprise any suitable conductive material, such as, for example, copper, ruthenium, titanium, tantalum, or cobalt, and combinations thereof. Each of the one or more conductive substrate interconnect structures 112 may include a top surface 113.

The composite dielectric layer 107 (which has a top surface 110) includes a plurality of inorganic filler materials/particles 108 disposed within an organic dielectric material/layer 106. The organic dielectric material 106 may include materials such as a mold compound (mold compound), an epoxy system such as a build up material (build up material), an aromatic polymer, a polyimide, a Perfluorocyclobutane (PFCB) material, a benzocyclobutene (BCB) material, or a combination thereof. In other embodiments, the organic dielectric material 106 may comprise a spin-on glass or sol-gel system with a low CTE filler material.

In embodiments, the inorganic fill material 108 may include a silica material (such as silica particles), low CTE dielectric fibers, dielectric particles or flakes (platlets), silicon nitride, silicon dioxide, silicon carbide, silicon carbonitride, alumina, diamond particles (such as CVD diamond particles), or combinations thereof. In an embodiment, the composite dielectric layer 107 may include between about 70% to about 95% by weight of the inorganic filler material 108. The weight percentage of the inorganic filler material 108 may be optimized to produce a low CTE of the composite dielectric layer 107 of the substrate bonding layer 102. In an embodiment, the CTE of the composite dielectric layer 107 may be comprised between about 0.5 ppm per degree celsius to about 10 ppm per degree celsius. The CTE of the composite dielectric layer 107 is optimized to be significantly less than the CTE of the conductive interconnects 112, 118 in the bonding direction (out-of-plane). Furthermore, by using a low CTE carrier substrate 119 in some cases, the in-plane CTE mismatch between die 114 and substrate 104 is minimized to achieve a smaller conductive interconnect layer spacing 129. In an embodiment, the CTE of the conductive interconnects 118, 112 is greater than about 30% of the CTE of the composite organic dielectric layer 107 in the bonding direction. The die bonding layer 120 is directly on the substrate bonding layer 102 and is electrically coupled to the substrate bonding layer 102.

In fig. 1B (which depicts a cross-sectional portion of the interface between the die bonding layer 120 and the substrate bonding layer 102), a covalent bonding region 130 is disposed between the top surface 124 of the inorganic dielectric material 116 of the die bonding layer 120 and the top surface 110 of the substrate bonding layer 102. In an embodiment, one or more of the plurality of inorganic filler materials 108 of the substrate bonding layer 102 may form an inorganic covalent bond 131 with the inorganic dielectric material 116 of the die bonding layer 120. Further, the conductive die interconnect structure 118 and the conductive substrate interconnect structure 112 form a direct metal bond 133 with each other in the metal bond region 132. Thus, by utilizing a hybrid, hybrid bonding process according to embodiments described herein, wherein both a metal bond 133 and an inorganic dielectric bond 131 are used to bond the substrate and the die together, bonding can be performed at the die-to-organic interface without the use of solder materials. There is no underfill material and no seed layer plating material on the conductive die and substrate interconnect structures (and between the die bonding layer 120 and the substrate bonding layer 102 interface 127), because plating, solder, and underfill material are not necessary to bond the conductive interconnect structures to each other. The composite dielectric layer 107 includes a CTE 121 in a direction perpendicular to the plane of the bonding interface 127 that is substantially lower than a CTE 123 (in a direction perpendicular to the plane of the bonding interface 127) of the conductive interconnect structures of the die and the substrate.

In FIG. 1C, a cross-sectional view of a portion of a hybrid junction structure 12 is depicted in accordance with some embodiments of the present disclosure. The hybrid bonded structure 12 includes a substrate 104 and a die 114. The die 114 includes a die-bonding layer 120, the die-bonding layer 120 including an inorganic dielectric material 116, wherein one or more conductive die interconnect structures 118 are disposed within the inorganic dielectric layer 116. The one or more conductive die interconnect structures 118 include a top surface 126, wherein the top surface 126 may be directly on the top surface 113 of the conductive substrate interconnect structure 112.

In an embodiment, a coating 111, which may include an inorganic layer 111, may be on a surface of the composite dielectric layer 107 (e.g., which is similar to the composite dielectric material of fig. 1A). In an embodiment, the inorganic layer 111 may include a thickness between about 10nm to about 1600 nm. In an embodiment, the coating 111 may include materials such as silicon, oxygen, nitrogen, or carbon, and combinations thereof. The coating 111 may comprise a material such as a Physical Vapor Deposition (PVD) material, an Atomic Layer Deposition (ALD) material, a Chemical Vapor Deposition (CVD) material, and in some cases a pulsed laser anneal or a spin-on dielectric material. The coating 111 may be directly on the organic dielectric material 106 including the inorganic filler material 108, such that the particles of the inorganic filler material 108 may be in direct contact with the coating 111 and may be covalently bonded to the coating 111.

In an embodiment, the coating 111 is on the organic dielectric material 106, but not on the top surface 113 of the conductive substrate interconnect structure 112, and on a portion of the sidewalls of the conductive substrate interconnect structure 112. The coating 111 is on the top surface of the die bonding layer 120. The inorganic layer 111 is covalently bonded to the inorganic dielectric material 116 and the die interconnect structure 118 is directly bonded to the substrate interconnect structure 112 without the use of solder or underfill materials. The CTE of the composite dielectric layer 107 including the plurality of inorganic filler materials 108 is less than the CTE of the conductive interconnect structures of the die 112 and the substrate 118 in a direction perpendicular to the bonding interface plane.

In FIG. 1D, a cross-sectional view of a portion of the hybrid junction structure 14 is depicted in accordance with some embodiments of the present disclosure. The hybrid bonded structure 14 includes a substrate 104 and a die 114. The die 114 includes a die-bonding layer 120, the die-bonding layer 120 including a composite dielectric layer 107, wherein a plurality of inorganic filler materials 108 are disposed within an organic dielectric material 106. In an embodiment, the composite dielectric layer 107 of the die-bonding layer 120 and the composite dielectric layer of the substrate-bonding layer 102 may include between about 70% to about 95% by weight of the inorganic filler material 108. One or more conductive die interconnect structures 118 are within the composite dielectric layer 107 of the die-bonding layer 120.

The one or more conductive die interconnect structures 118 are separated from each other by a composite dielectric layer 107. The substrate bonding layer 102 of the substrate 104 includes a composite dielectric layer 107 with a plurality of inorganic filler materials 108 within an organic dielectric material 106. The composite dielectric layer 107 of the die bonding layer 120 is on the top surface 110 of the substrate bonding layer 102, wherein the inorganic filler material 108 of the die bonding layer 120 is covalently bonded to the inorganic filler material 108 of the substrate bonding layer 102, and the die interconnect structure 118 is directly bonded to the substrate interconnect structure 112 without the use of solder or underfill material. The CTE of the composite dielectric layer 107 of the substrate bonding layer and the CTE of the composite dielectric layer 107 of the die bonding layer 120 are less than the CTE of the conductive interconnect structures of the die 112 and the substrate 118 in a direction perpendicular to the bonding interface plane.

In an embodiment, the composite dielectric layer 107 of the die-bonding layer 120 may comprise substantially the same material as the composite dielectric layer 107 of the substrate-bonding layer, but in other embodiments, these materials may be different from each other. Thus, by utilizing a hybrid bonding process according to embodiments described herein, where both metallic and inorganic dielectric bonds are used to bond the substrate and die together, bonding can be performed at the die-to-organic interface without the use of solder materials. There is no underfill material, solder material, and no seed layer plating material at the die bonding layer 120 and substrate bonding layer 102 interface, as these materials are not necessary to bond the conductive interconnect structures to each other.

In FIG. 1E, a cross-sectional view of a portion of a hybrid junction structure 16 is depicted in accordance with some embodiments of the present disclosure. The hybrid bonded structure 16 includes a substrate 104 and a die 114. The die 114 includes a die-bonding layer 120, the die-bonding layer 120 including an inorganic dielectric material 116. One or more conductive die interconnect structures 118 are disposed within the inorganic dielectric material 116. The one or more conductive die interconnect structures 118 may include a top surface 126.

The one or more conductive die interconnect structures 118 are separated from each other by the inorganic dielectric material 116. In an embodiment, the substrate bonding layer 102 of the substrate 104 includes a first portion 115, wherein the first portion 115 includes the composite dielectric material 107, wherein the plurality of inorganic filler materials 108 are disposed within the organic dielectric material 106. The second portion 125 of the substrate bonding layer 102 includes an inorganic dielectric material 117 that is free of the inorganic filler material 108. In an embodiment, the inorganic filler material 108 of the first portion 115 of the substrate bonding layer 102 may include a silica material (such as silica particles), low CTE dielectric fibers, particles or flakes, silicon nitride, silicon oxide, silicon carbide, silicon carbonitride. In an embodiment, the composite dielectric layer 107 of the first portion 115 of the substrate bonding layer 102 may include between about 70% to about 95% by weight of an inorganic filler material. The CTE of the composite dielectric layer 107 of the first portion 115 of the substrate bonding layer 102 may be optimized according to specific device/system design requirements.

The inorganic dielectric layer 116 of the die-bonding layer 120 is on the top surface of the substrate-bonding layer 102, wherein the inorganic dielectric material 116 of the die-bonding layer 120 is covalently bonded to the inorganic filler material 108 of the first portion 115 of the substrate-bonding layer 102, and the inorganic dielectric layer 116 of the die-bonding layer 120 is also covalently bonded to the inorganic dielectric material 117 of the second portion 125 of the substrate-bonding layer 102. The die interconnect structure 118 is bonded directly to the substrate interconnect structure 112 without the use of solder or underfill material. The CTE of the composite dielectric layer 107 of the substrate bonding layer 102 is less than the CTE of the conductive interconnect structures of the die 112 and the substrate 118 in a direction perpendicular to the bonding interface plane. In addition, the conductive die interconnect structure 118 and the conductive substrate interconnect structure 112 form a direct metal bond to each other. There is no underfill material and no seed layer plating material on the conductive die and substrate interconnect structures (at the interface between the top surface 126 of the die conductive interconnect structure 118 and the top surface 113 of the substrate conductive interconnect structure 112) because plating is not necessary to bond the conductive interconnect structures to each other.

In fig. 1F, a perspective view of a package structure 151 is depicted, in accordance with an embodiment. The first die 140 is embedded within one or more of the composite dielectric layers 107, where the first die 140 may be electrically and physically coupled to interconnect structures (not shown) within the composite dielectric layers 107. The composite organic dielectric layer 107 is attached to a package substrate 150. The first side 156 of the composite layer 107 is on the package substrate 150. The composite dielectric layer 107 may include a die attach layer on the second side 156 (opposite side 158) according to any of the embodiments described herein. The second die 142 and the third die 142' are on the second side 158 of the composite dielectric layer 107 and are physically and electrically coupled to interconnect structures (not shown) within the composite dielectric layer 107. The second die 142 and the third die 142 ' may include die-bonding layers 120, 120 ', with the die-bonding layers 120, 120 ' on the second side 158 of the composite dielectric layer 107 (fig. 1G, cross-sectional view). The die-bonding layers 120, 120' may include any of the embodiments of the die-bonding layers 120 described herein. The dielectric layer of the die attach layer 120 may be covalently bonded to an organic filler material (not shown) of the composite dielectric layer 107. Conductive interconnect structures (not shown, but including any embodiments of the die-bonding layers included herein) within the die-bonding layers of the dies 142, 142' and conductive interconnect structures (not shown) within the composite dielectric layer 107 are bonded together with a metallic bond, for example, as shown on fig. 1B.

In fig. 1H, a perspective view of a package structure 153 is depicted, in accordance with an embodiment. The first side 156 of the composite dielectric layer 107 is physically and electrically coupled to the package substrate 150 through interconnect structures (not shown) within the composite dielectric layer 107. The first die 142 and the second die 142' are embedded within the composite dielectric layer 107 and may be adjacent to each other. The composite dielectric layer 107 may include the substrate bonding layer 102 according to any of the embodiments described herein. The third die 143 can include a die-bonding layer 120 according to any embodiment herein, wherein the die-bonding layer 120 is on the substrate-bonding layer 102 of the organic composite layer 107 (fig. 1I, cross-sectional view). The dielectric layer of the die attach layer 120 may be covalently bonded to an inorganic filler material (not shown) of the composite dielectric layer 107. The conductive interconnect structures within the die-bonding layer 120 and the conductive substrate interconnect structures within the composite dielectric layer 107 are bonded together using dielectric and metallic bonding, for example, as shown in fig. 1B.

In fig. 1J, a perspective view of a package structure 155 is depicted, in accordance with an embodiment. The first die 142 and the second die 142' are on the second side 158 of the composite dielectric layer 107 and are physically and electrically coupled by interconnect structures (not shown) within the composite dielectric layer 107. The first side 156 of the composite dielectric layer 107 is physically and electrically coupled to the package substrate 150 through interconnect structures (not shown) within the composite dielectric layer 107. The first die 142 and the second die 142 ' may include die bonding layers 120, 120 ', with the die bonding layers 120, 120 ' on the second side 158 of the composite dielectric layer 107 (fig. 1K, cross-sectional view). The die-bonding layers 120, 120' may include any of the embodiments of the die-bonding layers 120 described herein. The dielectric layer of the die attach layer 120 may be covalently bonded to an inorganic filler material (not shown) of the composite dielectric layer 107. The die and the conductive interconnect structures (not shown) of the composite dielectric layer 107 are bonded together using dielectric and metallic bonds, for example, as shown on fig. 1B.

Fig. 2A-2E depict cross-sectional views of a method of forming a hybrid bonded package structure, according to an embodiment. In fig. 2A, a portion of a package structure 204 is shown. Build-up substrate 162, such as, for example, a damascene build-up (build up) or redistribution layer, may be on a carrier/handle 160, such as a silicon carrier or any other suitable carrier material. In some embodiments, build-up substrate 162 may include conductive and dielectric materials that may be patterned according to a particular application. For example, in some embodiments, build-up substrate 162 may include a conductive interconnect structure/routing layer 219 within the dielectric layer(s), which may be configured to route electrical signals between any number of dies.

For example, the interconnect structure may include routing structures, such as pads or traces, configured to receive electrical signals to and from the devices. In some embodiments, the conductive interconnect structure/routing layer includes trenches, ground planes, power planes, redistribution layers (RDLs), and/or any other suitable electrical routing features. Build-up substrate 162 may also provide structural support for discrete components and/or any other type of device. Die 264 may be on build-up substrate 162. Die 264 may include any suitable die, such as a central processing unit. In some embodiments, die 264 may include a processing system (single core or multi-core). In some embodiments, the die 106 may be a microprocessor, graphics processor, signal processor, network processor, chipset, memory device, or any type of passive device, or the like. In some embodiments, die 264 may be a system on a chip (SoC) having a plurality of functional units (e.g., one or more processing units, one or more graphics units, one or more communication units, one or more signal processing units, one or more security units, etc.). Adjacent to die 264 and on build-up substrate 262 is one or more substrate conductive interconnect structures 212.

In fig. 2B, a formation process 201 (such as a composite dielectric material formation process 201) may be employed to form a composite dielectric layer 107, the composite dielectric layer 107 including an organic dielectric material 106 filled with an inorganic filler material, such as, for example, an inorganic filler material including: silica materials (such as silica particles), low CTE dielectric fibers, dielectric particles or flakes, silicon nitride, silicon dioxide, silicon carbide, silicon carbonitride, alumina, diamond particles, or combinations thereof. The CTE of the composite dielectric layer 107 is much less than the CTE of the conductive interconnect structure 212. The formation process 201 may include formation techniques such as CVD, PVD, ALD, spin-on techniques, layer-by-layer deposition using laser pulse annealing or thermal annealing, transfer or compression molding, or vacuum lamination, and may utilize materials such as molding compound materials, epoxy materials, silsesquioxanes, spin-on-glass materials, which are filled with inorganic filler materials such as, for example, silica particles. The composite dielectric layer 107 may include a thickness of about 5 to about 200 microns and may include about 70% to about 95% by weight of the inorganic filler material 108. Each particle of the inorganic filler material 108 may include a diameter between about 0.002 microns to about 12 microns.

In fig. 2C, a planarization process 203 may be performed on the top surface 110 of the composite dielectric layer 107 and the top surface 213 of the substrate interconnect structure 212, as well as on the die 264. In an embodiment, the planarization process 203 may include a Chemical Mechanical Polishing (CMP) process, wherein the topography of the surfaces of the die, the composite dielectric layer 107, and the substrate interconnect structure 212 may be optimized for a particular application. For example, the smoothness of the surface 110 of the inorganic dielectric layer of the die 264 and the composite dielectric layer 107 may be adjusted by changing planarization parameters such as slurry composition, spin rate, pressure, and/or time. In an embodiment, the amount of root mean square roughness of the composite dielectric layer 107 may be less than about 0.5nm, but is dependent on the optimization of the planarization process 203. The amount of dishing (recessing recess) of the interconnect structure on the die 264 and the surface 213 of the conductive interconnect structure 212 can also be adjusted by varying the planarization process 203 parameters, such as, for example, the slurry chemistry. When performing the planarization process 203, some of the inorganic filler material 108 at the surface of the composite dielectric layer 107 may be exposed, and the surface of the conductive substrate interconnect structure 212 may also be exposed. The surface of the conductive substrate interconnect structure may be slightly recessed from the surface of the composite dielectric layer 107 and from the inorganic dielectric layer of the die 264.

In fig. 2D, a die attach process 205 may be employed to attach the die 114 to a portion of the substrate 204. In an embodiment, die 114 may include a die-bonding layer 120, similar to die-bonding layer 120 of fig. 1A. The die-bonding layer 120 may include a dielectric layer 116 and one or more die interconnect structures 118, the dielectric layer 116 may be an inorganic dielectric layer. The top surface 126 of the conductive die interconnect structure 118 may be bonded to the top surface 213 of the substrate conductive interconnect structure 212 by a metal bond.

The top surface 110 of the composite dielectric layer 107 may be bonded to the top surface 124 of the dielectric material 116 of the die bonding layer 120. In an embodiment, the dielectric material 116 of the die-bonding layer 120 and the inorganic filler material 108 of the composite dielectric layer 107 (and, in some embodiments, of the dielectric of the die 264) may initially form a covalent bond with each other, and then the conductive metallic bonding of the die interconnect structure 118 and the conductive interconnect structure 112 may occur during a subsequently specified temperature process. In this manner, by utilizing both inorganic covalent bonding within the organic dielectric and metal-to-metal bonding to bond the die 114 to the substrate 204, the use of solder and underfill materials is not necessary because the die attach process 205 is accomplished by using the hybrid bonding process disclosed herein. Fig. 2E depicts an embodiment of a portion of a package structure 270 in which carrier 160 has been removed and a plurality of solder interconnect structures 152 are formed between conductive interconnects of package substrate 170 and organic substrate 204.

Fig. 2F depicts an embodiment in which the coating 267 can be selectively formed on the composite dielectric layer 107, or in which the coating 267 can be formed on the entire surface of the substrate 204, and then subsequently patterned and/or planarized. Coating 267 may comprise an inorganic material, such as, for example, an inorganic dielectric material. For example, the coating 267 may be formed at a temperature below the degradation temperature of the organic dielectric material 106 of the composite dielectric layer 107, or at a temperature above the degradation temperature but for a typically very short duration (such as several microseconds) through a pulsed laser annealing process. Coating 267 may be formed by one or more of PVD, ALD, CVD, or spin coating processes, with or without thermal annealing. Following formation of coating 267, coating 267 may optionally be subjected to pulsed laser annealing. The coating 267 forms a bond with the composite dielectric layer 107. In fig. 2G, a die attach process 205 may be employed to attach the die 114 to portions of the die 264 and the substrate 204, including a coating 267 across two features. In an embodiment, die 114 may include a die-bonding layer 120, similar to die-bonding layer 120 of fig. 1A. The die-bonding layer 120 may include a dielectric layer 116 and one or more die interconnect structures 118, the dielectric layer 116 may be an inorganic dielectric layer. The top surface 126 of the conductive die interconnect structure 118 may be bonded to the top surface 213 of the substrate conductive interconnect structure 212 by a metal bond. Coating 267 may be bonded to inorganic dielectric 116 of die 114.

Fig. 3A-3F depict cross-sectional views of a method of forming a hybrid bonded package structure, according to an embodiment. In fig. 3A, a portion of a substrate structure 304 is shown. A build-up substrate 162, such as, for example, a damascene build-up layer or redistribution layer (RDL), may be on a carrier/handle 160, such as a silicon carrier or any other suitable carrier material. In some embodiments, build-up substrate 162 may include conductive and dielectric materials that may be patterned according to the design requirements of a particular application. Die 364 may be on build-up substrate 162. Die 364 may include any suitable die, such as, for example, a CPU.

In fig. 3B, a formation process 301, such as a composite dielectric material formation process 301, may be employed to form a composite dielectric layer 107, the composite dielectric layer 107 including an organic dielectric material filled with an inorganic filler material, such as, for example, an inorganic filler material 108 including silica particles. The CTE of the composite dielectric layer 107 is much less in the direction perpendicular to the interface plane than the CTE of the conductive interconnect structure to be subsequently formed. The formation process 301 may include formation techniques such as CVD, PVD, ALD, spin-on techniques, transfer or compression molding, and/or vacuum lamination, and may utilize materials such as molding compound materials, epoxy materials, silsesquioxanes, spin-on-glass materials, which are filled with inorganic filler materials such as, for example, silica particles.

In fig. 3C, a removal process 303 (such as, for example, an etching process) may be employed to remove a portion of the composite dielectric layer 107 to form one or more openings 366. The removal process 303 may expose one or more conductive traces 163 in the build-up layer 162. In fig. 3D, a metal formation process 305 may be employed. In an embodiment, a thin seed layer and an optional barrier layer (not shown) may first be formed within the one or more openings 366. The seed layer and/or the barrier layer may include any suitable conductive material, such as, for example, a copper alloy material, titanium, tantalum nitride, or a combination thereof, and may be formed by a sputtering process, a physical deposition process, or any other suitable formation process. In an embodiment, the seed layer may include a thickness of 10nm to 400nm and may include a conductive metal, such as a copper alloy. A subsequent electroplating process then fills the one or more openings 366 with a conductive material, such as copper, to form one or more substrate conductive interconnect structures 312. A portion of the conductive metal 367 may be on a top surface 368 of a portion of the substrate 304.

In fig. 3E, a metal planarization process 307 may be performed on the top surface 368 of the conductive material 367, such that the top surface of the conductive interconnect structure 312 and the top surface of the die 264 may be slightly recessed from the top surface 110 of the composite dielectric layer 107, as well as from the top surface of the dielectric material of the die 264. In an embodiment, the planarization process 307 may include a Chemical Mechanical Polishing (CMP) process, wherein the topography of the conductive interconnect structure and the top surface 108 of the composite dielectric layer 107 may be optimized for a particular application. For example, the smoothness of the surface 108 of the composite dielectric material may be adjusted by varying planarization parameters such as slurry composition, rotational speed, time, and the like.

In an embodiment, the amount of root mean square roughness of the composite dielectric layer 107 may be less than about 0.5 nm. Similarly, the amount of dishing or dishing of the surface of the conductive interconnect structure 312 may also be adjusted by varying the planarization process 307 parameters (such as, for example, the slurry chemistry). In performing the planarization process 307, some of the inorganic fill material 108 at the surface of the composite dielectric layer 107 and the dielectric of the die 364 may be exposed, and the surface of the conductive substrate interconnect structure 312 and the surface on the die 364 may be exposed. In some cases, the surface of the conductive substrate interconnect structure may be slightly recessed from the surface of the composite dielectric material.

In fig. 3F, a die attach process 309 may be employed to attach the die 114 to a portion of the substrate 204. In an embodiment, die 114 may include a die-bonding layer 120, similar to die-bonding layer 120 of fig. 1A. The die-bonding layer 120 may include a dielectric layer 116 and one or more die interconnect structures 118, the dielectric layer 116 may be an inorganic dielectric layer. The top surface 126 of the conductive die interconnect structure 118 may be bonded to the top surface 113 of the substrate conductive interconnect structure 312 by a metal bond.

The top surface 110 of the composite dielectric material 106 and the top surface of the die 364 may be bonded with the top surface 124 of the dielectric material 116 of the die bonding layer 120. In an embodiment, the dielectric material 116 of the die-bonding layer and the inorganic filler material 108 of the composite dielectric layer 107 may form a covalent bond with each other. During subsequent temperature processing, a metal bond is formed between the conductive interconnects 118, 112. In this manner, by utilizing both inorganic covalent bonding and metal-to-metal bonding to bond die 114 to substrate 204 and die 364, the use of solder and underfill materials is not necessary because the die attach process is accomplished by using the hybrid bonding process disclosed herein. In an embodiment, the carrier 160 has been removed and the organic substrate is attached to a package substrate, wherein a plurality of solder interconnect structures 152 are formed between the package substrate 170 and interconnect structures within the organic substrate 304.

Fig. 4A-4H depict cross-sectional views of a method of forming a hybrid bonded package structure, according to an embodiment. In fig. 4A, a portion of a substrate structure 404 is shown. Build-up substrate 162 (such as, for example, a damascene build-up layer or RDL) may be disposed on carrier/handle 160 (such as a silicon carrier or any other suitable carrier material). In some embodiments, build-up substrate 162 may include conductive and dielectric materials that may be patterned according to the design requirements of a particular application. The etch stop layer 420 may be selectively patterned across the build-up layer substrate 162.

In fig. 4B, a formation process 401 (such as a composite dielectric material formation process 401) may be employed to form a composite dielectric layer 107 on the build-up substrate 162. The composite dielectric layer 107 includes an organic dielectric material filled with an inorganic filler material, such as, for example, an inorganic filler material including silica particles. The CTE of the composite dielectric layer 107 is much less in the direction perpendicular to the plane of the bonding interface than the CTE of the subsequently formed conductive interconnect structure. The formation process 301 may include formation techniques such as CVD, PVD, ALD, spin-on techniques, transfer or compression molding, and/or vacuum lamination utilizing materials such as molding compound materials, epoxy materials, silsesquioxanes, spin-on glass materials, build-up materials, or combinations thereof, filled with inorganic filler materials such as, for example, silica particles.

In fig. 4C, a removal process 403 (such as, for example, an etching process) may be employed to remove a portion of the composite dielectric layer 107 to form one or more openings 466. The removal process 403 may expose one or more conductive traces or pads 163 in the build-up layer 162. In fig. 4D, a metal formation process 405 may be employed. In an embodiment, a thin seed layer and optional barrier layer (not shown) may first be formed within the one or more openings 466. The forming process 405 then fills the one or more openings 466 with a conductive material, such as copper or a copper alloy, to form one or more substrate conductive interconnect structures 412 via electroplating, solder paste printing, cold spraying, or similar such processes.

In fig. 4E, a removal process 407 (such as, for example, an etching process) may be employed to remove a portion of the composite dielectric layer 107 to form an opening 368. The selective etch stop layer 420 may be utilized to prevent damage to the underlying dielectric surface. In an embodiment, during process 407, an additional selective etch step may be utilized to remove the selective etch stop. In fig. 4F, die 464 may be attached to build-up substrate 162 by utilizing process 409. The gap 470 may be adjacent to the die 464. The gap 470 (fig. 4G) may be filled with a dielectric layer 472 and the die 114 may be attached to the substrate 404 (fig. 4H) after the top surface (depicted in fig. 4G) is prepared, for example, by chemical mechanical polishing to meet particular design requirements. A die attach process may be employed to attach the die 114 to a portion of the substrate 404. In an embodiment, die 114 may include a die-bonding layer 120, similar to die-bonding layer 120 of fig. 1A. The die-bonding layer 120 may include a dielectric layer 116 and one or more die interconnect structures 118, the dielectric layer 116 may be an inorganic dielectric layer. A surface of the one or more conductive die interconnect structures 118 may be bonded to a surface of the substrate conductive interconnect structure 412 including a surface of the die 464 by a metal bond.

The top surface of the composite dielectric material 106 and the dielectric surface of the die 464 may be bonded to the top surface of the dielectric material 116 of the die bonding layer 120. In an embodiment, the dielectric material 116 of the die-bonding layer and the inorganic filler material 108 of the composite dielectric material 106 and the dielectric of the die 464 may form a covalent bond with each other and, during subsequent temperature processing, form a bond between the conductive interconnects 412, 118. In this manner, by utilizing both inorganic covalent bonding and metal-to-metal bonding to bond the die 114 to the substrate 204, the use of solder and underfill materials is not necessary because the die attach process is accomplished by using the hybrid bonding process disclosed herein. In an embodiment, the carrier 160 has been removed and the organic substrate 404 is attached to the package substrate 170, wherein a plurality of solder interconnect structures 152 are formed between the package substrate 170 and the conductive features of the organic substrate 404.

FIG. 5 depicts a flow diagram of an embodiment of a method 500 of forming a hybrid junction structure as disclosed herein. The hybrid junction structure described in the embodiments enables higher density interconnects with finer pitch assembly. Eliminating the need for solder also mitigates the removal of underfill or mold around the solder. Less warpage is achieved and the need for solder plating and photolithography is eliminated. With the removal of solder from a system incorporating embodiments described herein, power delivery and reliability are improved. Method 500 may share any or all of the characteristics with any other method discussed herein, such as, but not limited to, the methods disclosed in, for example, fig. 2A-2G, 3A-3F, and 4A-4H, which may show cross-sectional views of structures employing any of the operations described in method 500. It should be noted that the order of the operations of method 500 may be varied depending on the particular application.

At operation 502, a composite dielectric material may be formed on at least a portion of a substrate, wherein the composite dielectric material includes an organic dielectric material and is filled with a plurality of inorganic filler materials. In embodiments, the composite dielectric material may be formed on the substrate using any suitable formation process, such as has been described in embodiments herein. A plurality of inorganic filler materials may be added to a suitable organic dielectric material, such as has been described in the embodiments, in order to reduce the overall CTE of the organic substrate in a direction perpendicular to the plane of the bonding interface with respect to the CTE of the metal interconnects.

At operation 504, one or more conductive substrate interconnect structures may be formed within the composite dielectric material. In an embodiment, the top surface of the one or more conductive substrate interconnect structures may be slightly recessed along with the top surface of the composite dielectric material. In other embodiments, the top surface of one or more conductive substrate interconnect structures may be recessed or slightly recessed from the surface of the composite dielectric material, depending on design requirements. For example, the surface topography of the composite dielectric material and conductive structures can be tuned, for example, with a CMP process, and typically the root mean square roughness of the dielectric must be less than 0.5 nm.

At operation 506, a die may be attached to the top surface of the composite dielectric material, where the die may include one or more conductive die interconnect structures within the die dielectric material. The die dielectric material may comprise an inorganic material or may comprise a composite dielectric material having an organic dielectric material filled with inorganic filler particles.

At operation 508, the one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures by metal-to-metal bonding. As described herein, the composite dielectric material of the substrate is covalently bonded to the die.

Fig. 6 is a schematic diagram of a computing device 600, which computing device 600 may be implemented in conjunction with the packaging structure described in any embodiment herein including hybrid bonded structures. The hybrid bond structure of the packaged device herein provides a smaller pitch and is free of solder and underfill materials, such as the hybrid bond structure depicted, for example, in fig. 1A. In an embodiment, computing device 600 houses a board 602, such as, for example, a motherboard 602. The board 602 may include a number of components including, but not limited to, a processor 604, on-die memory 606, and at least one communication chip 608. The processor 604 may be physically and electrically coupled to the board 602. In some implementations, the at least one communication chip 608 may be physically and electrically coupled to the board 602. In further implementations, the communication chip 608 is part of the processor 604.

Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to board 602, and may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM) 609, non-volatile memory (e.g., ROM) 610, flash memory (not shown), a Graphics Processor Unit (GPU) 612, a chipset 614, an antenna 616, a display 618 such as a touchscreen display, a touchscreen controller 620, a battery 622, an audio codec (not shown), a video codec (not shown), a Global Positioning System (GPS) device 626, an integrated sensor 628, a speaker 630, a camera 632, an amplifier (not shown), a Compact Disc (CD) (not shown), a Digital Versatile Disc (DVD) (not shown), and so forth. These components may be connected to the system board 602, mounted to the system board, or combined with any other components.

The communication chip 608 enables wireless and/or wired communication for communicating data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 608 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet and derivatives thereof, as well as any other wireless and wired protocols designated as 3G, 4G, 5G, and beyond.

The computing device 600 may include a plurality of communication chips 608. For example, a first communication chip may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and so on. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a wearable device, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital video camera, a portable music player, or a digital video recorder. In further implementations, the computing device 400 may be any other electronic device that processes data.

Embodiments of the device structures described herein may be implemented as part of one or more memory chips, controllers, CPUs (central processing units), microchips or integrated circuits interconnected using a motherboard, Application Specific Integrated Circuits (ASICs), and/or Field Programmable Gate Arrays (FPGAs).

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Thus, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the spirit and scope of the disclosure.

It will be recognized that the embodiments herein are not limited to the embodiments so described, but may be practiced with modification and alteration without departing from the scope of the appended claims.

However, the above embodiments are not limited in these respects, and in various implementations, the above embodiments may include taking only a subset of such features, taking a different order of such features, taking a different combination of such features, and/or taking additional features in addition to those expressly listed. The scope of the embodiments herein should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.