阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 璁稿钩 许平 于 2020-07-21 设计创作，主要内容包括：本发明公开一种半导体装置及其制造方法。该半导体装置包括一基底、多个导电特征部件设置于该基底的上方、多个连接垫设置于该基底的上方、一覆盖层设置于该基底的上方及多个电容结构设置于该基底的上方。其中两相邻的连接垫的轴线夹角小于180度。(The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of conductive feature components arranged above the substrate, a plurality of connecting pads arranged above the substrate, a covering layer arranged above the substrate and a plurality of capacitor structures arranged above the substrate. Wherein the included angle of the axes of two adjacent connecting pads is less than 180 degrees.)

1. A semiconductor device, comprising:

a substrate;

a plurality of conductive features disposed over the substrate;

the connecting pads are arranged above the substrate, and the axial included angle of two adjacent connecting pads is less than 180 degrees;

a covering layer arranged above the substrate;

a plurality of capacitor structures are disposed above the substrate.

2. The semiconductor device of claim 1, wherein the plurality of conductive features are disposed below the plurality of capacitive structures.

3. The semiconductor device of claim 1, wherein the plurality of conductive features are disposed over the plurality of capacitive structures.

4. The semiconductor device of claim 1, further comprising a plurality of word lines disposed in the substrate and a first doped region disposed between an adjacent pair of the plurality of word lines, wherein one of the plurality of conductive features is disposed on the first doped region.

5. The semiconductor device of claim 4, wherein one of the plurality of connection pads is disposed between one of a plurality of bit lines and the first doped region.

6. The semiconductor device of claim 4, further comprising a plurality of isolation structures disposed in said substrate, wherein said plurality of isolation structures are spaced apart from each other and define a plurality of active regions in said substrate.

7. The semiconductor device of claim 1, further comprising a plurality of second doped regions and a plurality of active regions, wherein each active region intersects two word lines, and the plurality of second doped regions are disposed between the two word lines and the plurality of isolation structures.

8. The semiconductor device of claim 7, wherein the connection pads are disposed between the capacitor structures and the second doped regions.

9. The semiconductor device of claim 6, wherein two of said plurality of word lines extend along a first direction and said plurality of active regions extend along a direction that is oblique to said first direction.

10. The semiconductor device of claim 1, further comprising a plurality of bit line contact plugs disposed above the substrate and a plurality of bit lines disposed above the substrate, wherein one of the plurality of bit line contact plugs is disposed on the cap layer and below one of the plurality of bit lines.

11. The semiconductor device of claim 1, wherein said plurality of capacitor structures comprise a plurality of capacitor bottom electrodes concavely disposed above said substrate, a capacitor insulating layer disposed on said plurality of capacitor bottom electrodes and a capacitor top electrode disposed on said capacitor insulating layer.

12. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a plurality of conductive features over the substrate;

forming a covering layer on the substrate;

forming a plurality of connecting pads above the substrate, wherein the included angle between the axes of two adjacent connecting pads is less than 180 degrees.

13. The method of claim 12, further comprising forming a plurality of capacitor structures over the substrate.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the plurality of conductive features are formed under the plurality of capacitive structures.

15. The method of claim 13, wherein the plurality of conductive features are formed over the plurality of capacitive structures.

16. The method of claim 12, further comprising forming a plurality of word lines formed in the substrate and a first doped region formed between an adjacent pair of the plurality of word lines, wherein one of the conductive features is formed on the first doped region.

17. The method of claim 16, wherein one of the plurality of connection pads is formed between one of a plurality of bit lines and the first doped region.

18. The method of claim 12, further comprising forming a plurality of bit line contact plugs and a plurality of bit lines, wherein one of the plurality of bit line contact plugs is formed on the cap layer and under one of the plurality of bit lines.

19. The method according to claim 13, wherein the plurality of capacitor structures comprise a plurality of capacitor bottom electrodes formed concavely above the substrate, a capacitor insulating layer formed on the plurality of capacitor bottom electrodes, and a capacitor top electrode formed on the capacitor insulating layer.

20. The method according to claim 12, wherein the plurality of connection pads are formed between a plurality of capacitor structures and a plurality of second doped regions.

Technical Field

The present disclosure claims priority and benefit of 2019/09/25 application U.S. official application No. 16/582,191, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a method of manufacturing the same. More particularly, a semiconductor device having selectively formed anisotropic bond pads and related methods of manufacture.

Background

Semiconductor devices are used in a variety of electronic devices, including mobile phones or other communication devices, automotive electronics, or other technology platforms. As the demand for functionality and miniaturization of mobile devices such as mobile phones, digital cameras, and notebook computers increases, the demand for a package-on-package semiconductor device capable of providing an elastic interconnection geometry (interconnect geometry) also increases. The stack package technology is widely used in the manufacture of semiconductor devices, and plays an increasingly important role in the future. In addition to providing the advantage of smaller size, the package-on-package technology provides semiconductor devices with faster signal propagation and reduced noise and cross-talk (cross-talk) due to the shorter interconnect wiring. However, the stack packaging process suffers from various problems that affect the final electrical characteristics, quality and yield of the semiconductor device. Accordingly, challenges remain in improving the performance, quality, yield, and reliability of semiconductor devices.

The above description of "prior art" merely provides background and is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as an admission that it forms part of the present disclosure.

Disclosure of Invention

One aspect of the present disclosure discloses a semiconductor device, which includes a substrate, a plurality of conductive features disposed above the substrate, a plurality of connecting pads disposed above the substrate, a cover layer disposed above the substrate, and a plurality of capacitor structures disposed above the substrate, wherein an included angle between axes of two adjacent connecting pads is less than 180 degrees.

In some embodiments of the present disclosure, the conductive feature is disposed below the plurality of capacitive structures.

In some embodiments of the present disclosure, the conductive feature is disposed over the plurality of capacitive structures.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of word lines disposed in the substrate and a first doped region disposed between an adjacent pair of the plurality of word lines, wherein one of the plurality of conductive features is disposed on the first doped region.

In some embodiments of the present disclosure, one of the plurality of connection pads is disposed between one of a plurality of bit lines and the first doped region.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of isolation structures disposed in the substrate, wherein the isolation structures are spaced apart from each other and define a plurality of active regions in the substrate.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of second doping regions and a plurality of active regions, wherein each active region intersects two word lines, and the plurality of second doping regions are disposed between the two word lines and the plurality of isolation structures.

In some embodiments of the present disclosure, the plurality of connection pads are disposed between a plurality of capacitor structures and the second doped region.

In some embodiments of the present disclosure, two of the plurality of word lines extend along a first direction, and the plurality of active regions extend along a direction inclined with respect to the first direction.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of bit line contact plugs disposed above the substrate and a plurality of bit lines disposed above the substrate, wherein one of the plurality of bit line contact plugs is disposed on the capping layer and below one of the plurality of bit lines.

In some embodiments of the present disclosure, the plurality of capacitor structures include a plurality of capacitor bottom electrodes concavely disposed above the substrate, a capacitor insulating layer disposed on the plurality of capacitor bottom electrodes, and a capacitor top electrode disposed on the capacitor insulating layer.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, which includes providing a substrate, forming a plurality of conductive features over the substrate, forming a capping layer over the substrate, and forming a plurality of connection pads over the substrate, wherein an included angle between axes of two adjacent connection pads is less than 180 degrees.

In some embodiments of the present disclosure, the method further includes forming a plurality of capacitor structures over the substrate.

In some embodiments of the present disclosure, the conductive feature is formed under the plurality of capacitive structures.

In some embodiments of the present disclosure, the conductive feature is formed over the plurality of capacitive structures.

In some embodiments of the present disclosure, the method further includes forming a plurality of word lines formed in the substrate and a first doped region formed between an adjacent pair of the plurality of word lines, wherein one of the plurality of conductive features is formed on the first doped region.

In some embodiments of the present disclosure, one of the plurality of connection pads is disposed between one of a plurality of bit lines and the first doped region.

In some embodiments of the present disclosure, the method of fabricating the semiconductor device further comprises forming a plurality of bit line contact plugs and a plurality of bit lines, wherein one of the plurality of bit line contact plugs is formed on the capping layer and under one of the plurality of bit lines.

In some embodiments of the present disclosure, the plurality of capacitor structures include a plurality of capacitor bottom electrodes concavely formed above the substrate, a capacitor insulating layer formed on the plurality of capacitor bottom electrodes, and a capacitor top electrode formed on the capacitor insulating layer.

In some embodiments of the present disclosure, the plurality of connection pads are formed between the plurality of capacitor structures and a plurality of second doped regions.

Due to the design of the semiconductor device of the present disclosure, the anisotropic bonding pads can improve the flexibility of the bonding geometry in the semiconductor device, and thus the alignment tolerance of the semiconductor device is improved.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages, which constitute the subject of the present disclosure, will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein like reference numerals refer to like elements, when considered in conjunction with the accompanying drawings.

Fig. 1 is a flow chart illustrating a method of fabricating a semiconductor device in one embodiment of the present disclosure.

Fig. 2 and 3 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 4 is a plan view illustrating the semiconductor device in fig. 3.

Fig. 5 to 7 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 8 is a plan view illustrating the semiconductor device in fig. 7.

Fig. 9 and 10 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 11 is a plan view illustrating the semiconductor device in fig. 10.

Fig. 12 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

Fig. 13 is a plan view illustrating the semiconductor device in fig. 12.

Fig. 14 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

Fig. 15 is a plan view illustrating the semiconductor device in fig. 14.

Fig. 16 to 18 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 19 is a plan view illustrating the semiconductor device in fig. 18.

Fig. 20 to 22 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Fig. 23 is a plan view illustrating the semiconductor device in fig. 22.

Fig. 24 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

Fig. 25 and 26 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Fig. 27 is a plan view illustrating the semiconductor device in fig. 26.

Fig. 28 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Description of reference numerals:

10: method of producing a composite material

101: substrate

103: isolation structure

105: active region

201: word line

203: bottom layer

205: intermediate layer

207: top layer

209: trench opening

301: first doped region

303: second doped region

401: first contact plug

403: second contact plug

405: bit line contact plug

407: covering layer

409: bit line

411: first plug

413: second plug

415: bottom perforation

417: conductive layer

500: capacitor structure

501: bottom electrode

503: capacitor insulating layer

505: top electrode

507: capacitor trench

601: a first insulating layer

603: a second insulating layer

605: a third insulating layer

607: a fourth insulating layer

609: a fifth insulating layer

611: a sixth insulating layer

613: a seventh insulating layer

700: connecting cushion layer

701: connecting pad

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It is apparent that the implementation of the disclosure does not limit the specific details known to a person skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details. The scope of the present disclosure is not limited by the detailed description but is defined by the related application documents.

In the present disclosure, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Such as electro-optical devices, light emitting display devices, semiconductor circuits and electronic devices, will be included in the category of semiconductor devices.

In the description of the present disclosure, the upper side corresponds to the arrow direction of the Z-axis, and the lower side corresponds to the opposite direction of the arrow of the Z-axis.

Fig. 1 is a flow chart illustrating a method 10 of fabricating a semiconductor device in accordance with one embodiment of the present disclosure. Fig. 2 and 3 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 4 is a plan view illustrating the semiconductor device in fig. 3.

Referring to fig. 1 and 2, in step S11, a substrate 101 is provided. The substrate 101 is formed of silicon (silicon), doped silicon (silicon), silicon germanium (silicon germanium), silicon on insulator (silicon on insulator), silicon on sapphire (silicon on sapphire), silicon germanium on insulator (silicon germanium on insulator), silicon carbide (silicon carbide), germanium (germanium), gallium arsenide (gallium arsenide), gallium phosphide (gallium arsenide), gallium arsenide phosphide (gallium arsenide phosphide), indium phosphide (indium phosphide), or indium gallium phosphide (indium gallium phosphide).

Referring to fig. 1, 3 and 4, in step S13, a plurality of isolation structures 103 are formed in the substrate 101. In the cross-sectional view, the isolation structures 103 are spaced apart from each other, and the isolation structures 103 define active regions 105. The isolation structures 103 are formed of an insulating material. Such as silicon oxide (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), silicon nitride oxide (silicon nitride oxide), fluorine-doped silicate (fluorine-doped silicate), or the like. In a top view, the active regions 105 extend in a direction inclined with respect to the first direction X. In the present disclosure, silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxide nitride refers to a material that includes silicon, nitrogen, and oxygen, where the proportion of nitrogen is greater than the proportion of oxygen.

Fig. 5 to 7 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 8 is a plan view illustrating the semiconductor device in fig. 7.

Referring to fig. 1, 5 to 8, in step S15, a plurality of word lines 201 are formed in the substrate 101. In the illustrated embodiment, the plurality of word lines 201 extend along the first direction X, and each word line 201 includes a bottom layer 203, an intermediate layer 205, a top layer 207, and a trench opening 209. Referring to FIG. 5, in the illustrated embodiment, a photolithography process is performed to pattern the substrate 101 to define the locations where the trench openings 209 are to be formed. After the photolithography process, an etching process is performed to form the trench openings 209 in the substrate 101, wherein the etching process is anisotropic dry etching. Referring to fig. 6, after the etching process, the bottom layers 203 are correspondingly formed and attached to the sidewalls and bottom surfaces of the trench openings 209. The plurality of bottom layers 203 are formed of silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide, or the like.

Referring to fig. 7 and 8, the plurality of intermediate layers 205 are correspondingly formed on the plurality of bottom layers 203. The top surfaces of the intermediate layers 205 are lower than the top surface of the substrate 101. The plurality of intermediate layers 205 are formed of doped polysilicon (polysilicon), metal (metal), or metal silicide (metal silicide), and the metal silicide is nickel silicide (nickel silicide), platinum silicide (platinum silicide), titanium silicide (titanium silicide), molybdenum silicide (molybdenum silicide), cobalt silicide (cobalt silicide), tantalum silicide (tantalum silicide), tungsten silicide (tungsten silicide), or the like. The plurality of top layers 207 are correspondingly formed on the plurality of intermediate layers 205. The top surfaces of the plurality of top layers 207 are flush with the top surface of the substrate 101. The top layers 207 are formed of silicon oxide, silicon nitride, silicon oxynitride or silicon nitride oxide, or the like.

Fig. 9 is a cross-sectional view illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 1 and 9, in step S17, a plurality of doped regions are formed in the plurality of active regions 105 of the substrate 101. In each active region 105, the doped regions include a first doped region 301 and a plurality of second doped regions 303. The first doped region 301 is disposed between an adjacent pair (adjacent pair) of the plurality of word lines 201. The second doped regions 303 are respectively disposed between the isolation structures 103 and the word lines 201. The first doped region 301 and the plurality of second doped regions 303 are doped with a dopant (dopant), which is phosphorus, arsenic or antimony. The first doped region 301 and the plurality of second doped regions 303 have dopant concentrations between about 1E17 atoms/cm ^3 and about 1E19 atoms/cm ^3, respectively.

Fig. 10 is a cross-sectional view illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 11 is a plan view illustrating the semiconductor device in fig. 10.

Referring to fig. 1, 10 and 11, in step S19, a plurality of conductive features are formed on the substrate 101. A first insulating layer 601 is formed on the substrate 101. The first insulating layer 601 is formed of silicon nitride, silicon oxide, silicon oxynitride, undoped silicate glass (undoped silicate glass), borosilicate glass (borosilicate glass), phosphosilicate glass (phosphosilicate glass), borophosphosilicate glass (phosphosilicate glass), or a combination thereof, but is not limited thereto. The plurality of conductive features are formed in the first layer of insulating layer 601. The plurality of conductive features includes a first contact plug 401 and a plurality of second contact plugs 403. A lithographic process is performed to pattern the first insulating layer 601 to define the locations where the conductive features are to be formed. After the photolithography process, an etching process is performed to form a plurality of contact plug openings in the first insulating layer 601, and the etching process is anisotropic dry etching. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited into the contact plug openings to form the conductive features through a metallization process (metallization), such as chemical vapor deposition (chemical vapor deposition), physical vapor deposition (sputtering), sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes.

More specifically, referring to fig. 10 and 11, the first contact plug 401 is disposed on the first doping region 301 and electrically connected to the first doping region 301. The second contact plugs 403 are respectively disposed on the second doping regions 303 and electrically connected to the second doping regions 303. In the illustrated embodiment, the first contact plug 401 includes tungsten. In addition, the plurality of second contact plugs 403 includes tungsten. When the top surface of the first contact plug 401 is exposed to oxygen or air, the first contact plug 401 including tungsten is prone to form defects (defects) on the top surface of the first contact plug 401, thereby affecting the yield of the semiconductor device.

Fig. 12 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. Fig. 13 is a plan view illustrating the semiconductor device in fig. 12.

Referring to fig. 1, 12 and 13, in step S21, bit line contact plugs 405 are formed on the substrate 101. A second insulating layer 603 is formed over the first insulating layer 601. The second insulating layer 603 and the first insulating layer 601 can be formed of the same material, but not limited thereto. A photolithography process is performed to pattern the second insulating layer 603 to define locations where the bit line contact plugs 405 are to be formed. After the photolithography process, an etching process is performed to form a plurality of bit line contact plug openings in the second insulating layer 603, and the etching process is anisotropic dry etching. The top surface of the first contact plug 401 will be exposed through the bit line contact plug openings. A cleaning process using a reducing agent of titanium tetrachloride (titanium tetrachloride), tantalum tetrachloride (tantalum tetrachloride), or a combination thereof may be selectively performed to remove defects on the top surface of the first contact plug 401 including tungsten.

Referring to fig. 12 and 13, after the cleaning process, a capping layer 407 is formed to cover sidewalls and a bottom surface of the bit line contact plug openings, wherein the capping layer 407 comprises tungsten nitride (tungsten nitride). The capping layer 407 prevents the top surface of the first contact plug 401 including tungsten from being exposed to oxygen or air; therefore, the capping layer 407 can reduce the formation of defects on the top surface of the first contact plug 401 including tungsten. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited into the bit line contact plug openings to form the bit line contact plugs 405 through a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes.

Referring to fig. 12 and 13, the bit line contact plugs 405 are correspondingly electrically connected to the first contact plugs 401, i.e., the bit line contact plugs 405 are electrically connected to the first doping region 301.

Fig. 14 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. Fig. 15 is a plan view illustrating the semiconductor device in fig. 14.

Referring to fig. 1, 14 and 15, in step S23, a plurality of bit lines 409 are formed on the substrate 101. A third insulating layer 605 is formed on the second insulating layer 603. The third insulating layer 605 and the first insulating layer 601 may be formed of the same material, but not limited thereto. A photolithography process is performed to pattern the third insulating layer 605 to define the locations where the bit lines 409 are to be formed. After the photolithography process, an etching process is performed to form a plurality of bit line trenches in the third insulating layer 605, and the etching process is anisotropic dry etching. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited into the bit line trenches to form the bit lines 409 through a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes. The bit line contact plugs 405 are located at intersections (intersections) of the bit lines 409 and the active regions 105.

Fig. 16 is a cross-sectional view illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 1 and 16, in step S25, a plurality of first plugs 411 are formed over the substrate 101. A photolithography process is performed to pattern the third insulating layer 605 to define the locations where the first plugs 411 will be formed. After the photolithography process, an etching process is performed to form a plurality of plug openings through the third insulating layer 605 and the second insulating layer 603, wherein the etching process is anisotropic dry etching. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys, is deposited into the plug openings to form the first plugs 411 through a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes.

Fig. 17 and 18 are cross-sectional views illustrating a partial flow of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 19 is a plan view illustrating the semiconductor device in fig. 18.

Referring to fig. 1, 17 to 19, in step S27, a plurality of bonding pads 701 are formed on the substrate 101. The connecting pads 701 are formed of a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys. A bonding pad 700 is formed on the substrate 101. The plurality of connection pads 701 are formed from the connection pad layer 700. A self-aligned etching process (self-aligned etching process) is performed to pattern the bonding pad layer 700 to form the bonding pads 701. Typically, the self-aligned etching process is performed by forming the connection pad layer 700 on the third insulating layer 605, forming a hard mask layer on the connection pad layer 700, and defining the locations of the connection pads 701 on the hard mask layer by an ion implantation process (ion implantation). Next, the bonding pads 701 are patterned on the hard mask layer by self-aligned etching, and the bonding pads 701 are formed after etching the bonding pad layer 700. Specifically, after the self-aligned etching process, an anisotropic etching process is performed on the bonding pad layer 700 to form the bonding pads 701, wherein the bonding pads 701 have different dimensions (dimensions) in different directions. More specifically, the included angle between the axes of two adjacent connecting pads 701 is less than 180 degrees; preferably, the included angle between the axes of two adjacent connecting pads 701 is 90 degrees (as shown in FIG. 19). The anisotropic bonding pads 701 can improve the flexibility of the connection geometry in the semiconductor device, so that the alignment tolerance (tolerance) of the semiconductor device is improved.

Referring to fig. 1, 20 to 23, in step S29, a plurality of capacitor structures 500 are formed on the substrate 101. The plurality of capacitor structures 500 includes a plurality of bottom electrodes 501, a capacitor insulating layer 503, and a top electrode 505. Referring to fig. 20 and 21, a plurality of second plugs 413 are formed over the substrate 101. A fourth insulating layer 607 is formed over the third insulating layer 605. The fourth insulating layer 607 can be formed of the same material as the first insulating layer 601, but is not limited thereto. A first photolithography process is performed to pattern the fourth insulating layer 607 to define the locations where the second plugs 413 are to be formed. After the first photolithography process, an etching process is performed to form a plurality of plug openings in the fourth insulating layer 607, and the etching process is anisotropic dry etching. After the etching process, a conductive material is deposited into the plurality of plug openings to form the plurality of second plugs 413 through a metallization process, the plurality of second plugs 413 are formed above the plurality of connection pads 701, the conductive material is aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys, and the metallization process is chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes. After the second plugs 413 are formed, a fifth insulating layer 609 is formed on the fourth insulating layer 607. The fifth insulating layer 609 can be formed of the same material as the first insulating layer 601, but is not limited thereto. A second photolithography process is performed to pattern the fifth insulating layer 609 to define locations where a plurality of capacitor trenches 507 are to be formed. After the second photolithography process, an etching process is performed to form the plurality of capacitor trenches 507 in the fifth insulating layer 609, wherein the etching process is anisotropic dry etching. The plurality of second plugs 413 are exposed through the plurality of capacitor trenches 507.

Referring to fig. 22, the bottom electrodes 501 are correspondingly formed in the capacitor trenches 507, i.e., the bottom electrodes 501 are concavely formed in the fifth insulating layer 609. The bottom electrode 501 is formed of doped polysilicon, metal silicide, aluminum, copper, or tungsten. The bottom electrodes 501 are electrically connected to the second plugs 413, respectively. The capacitor insulating layer 503 is formed and attached to the sidewall and bottom surface of the bottom electrode 501 and the top surface of the fifth insulating layer 609. The capacitor insulating layer 503 is formed of a high dielectric constant (high dielectric constant) material, such as barium strontium titanate (barium titanate), lead zirconium titanate (lead zirconium titanate), titanium oxide (titanium oxide), aluminum oxide (aluminum oxide), hafnium oxide (hafnium oxide), yttrium oxide (yttrium oxide), zirconium oxide (zirconium oxide), or the like. Alternatively, in another embodiment, the capacitor insulating layer 503 is a multi-layer structure composed of silicon oxide, silicon nitride, and silicon oxide. Referring to fig. 22 and 23, the top electrode 505 is formed to fill the plurality of capacitor trenches 507 and cover the capacitor insulating layer 503. The top electrode 505 is formed of doped polysilicon, copper, or aluminum.

Fig. 24 is a cross-sectional view illustrating a partial flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present disclosure.

Referring to fig. 1 and 24, in step S31, a bottom via 415 and a conductive layer 417 are formed over the substrate 101. A sixth insulating layer 611 is formed on the top electrode 505. The sixth insulating layer 611 may be formed of the same material as the first insulating layer 601, but is not limited thereto. A photolithography process is performed to pattern the sixth insulating layer 611 to define the locations where the bottom vias 415 are to be formed. After the photolithography process, an etching process is performed to form a bottom via opening in the sixth insulating layer 611, wherein the etching process is anisotropic dry etching. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metals or metal alloys, is deposited into the bottom via opening to form the bottom via 415 in the sixth insulating layer 611 through a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, is performed to remove excess filler and provide a planar surface for subsequent processes. After forming the bottom via 415, a seventh insulating layer 613 is formed on the sixth insulating layer 611. The seventh insulating layer 613 may be formed of the same material as the first insulating layer 601, but is not limited thereto. A photolithography process is performed on the seventh insulating layer 613 to define the position where the conductive layer 417 is to be formed. After the photolithography process, an etching process is performed to form a conductive layer trench in the seventh insulating layer 613, and the etching process is anisotropic dry etching. The top surface of the bottom via 415 is exposed through the conductive trench. Next, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited into the conductive layer trench to form the conductive layer 417 by a metallization process, such as chemical vapor deposition, physical vapor deposition, sputtering, or the like.

The connection pads 701 are relay stations (relay stations) for electrical connection of high aspect ratio (aspect ratio), for example, connecting the first plug 411 and the second plug 413.

In other embodiments shown, referring to fig. 1 and fig. 25 to fig. 28, the connecting pads 701 are formed on the first insulating layer 601. The connection pad layer 700 is formed above the substrate 101. The plurality of connection pads 701 are formed from the connection pad layer 700. A self-aligned etching process is performed to pattern the bonding pad layer 700 to form the bonding pads 701. Typically, the self-aligned etching process is performed by forming the pad layer 700 on the first insulating layer 601, forming a hard mask layer on the pad layer 700, and defining the locations of the connecting pads 701 on the hard mask layer by an ion implantation process. Next, the bonding pads 701 are patterned on the hard mask layer by self-aligned etching, and the bonding pads 701 are formed after etching the bonding pad layer 700. Specifically, the self-aligned etching process is performed on the bonding pad layer 700 to form the bonding pads 701, wherein the bonding pads 701 have different dimensions in different directions. More specifically, the included angle between the axes of two adjacent connecting pads 701 is less than 180 degrees; preferably, the included angle between the axes of two adjacent connection pads 701 is 90 degrees. The anisotropic bonding pads 701 can improve the flexibility of the connection geometry in the semiconductor device, thereby improving the alignment tolerance of the semiconductor device.

Referring to fig. 28, the semiconductor device includes a substrate 101, a plurality of isolation structures 103, a plurality of word lines 201, a plurality of doped regions, a plurality of insulating layers, a plurality of conductive features, a plurality of bit line contact plugs 405, a first cap layer 407, a plurality of bit lines 409, a plurality of first plugs 411, a bottom via 413, a plurality of connection pads 701, a bottom via 415, a conductive layer 417, and a plurality of capacitor structures 500. It is noted that in the present disclosure, the plurality of conductive features can be regarded as the first contact plug 401, the second contact plug 403 and the bottom via 415, but not limited thereto.

Referring to fig. 28, the isolation structures 103 are disposed in the substrate 101 and separated from each other. The plurality of isolation structures 103 define a plurality of active regions 105 (only one active region 105 is shown in fig. 28). The word lines 201 are disposed in the substrate 101 and spaced apart from each other. Each word line 201 includes a bottom layer 203, an intermediate layer 205, and a top layer 207. The bottom layers 203 are respectively disposed in the substrate 101 in a concave manner. The intermediate layers 205 are respectively disposed on the bottom layers 203. The top surfaces of the intermediate layers 205 are lower than the top surface of the substrate 101. The top layers 207 are respectively disposed on the middle layers 205. The top surface of the plurality of top layers 207 is level with the top surface of the substrate 101.

Referring to fig. 28, the doped regions are respectively and correspondingly disposed in the active regions 105 of the substrate 101. Each doped region includes a first doped region 301 and a plurality of second doped regions 303. The first doped region 301 is disposed between an adjacent pair of the plurality of word lines 201 in the corresponding active region 105. The second doped regions 303 are respectively disposed between the isolation structures 103 and the word lines 201.

Referring to fig. 28, the insulating layers are disposed above the substrate 101. The plurality of insulating films include a first insulating layer 601, a second insulating layer 603, a third insulating layer 605, a fourth insulating layer 607, a fifth insulating layer 609, a sixth insulating layer 611, and a seventh insulating layer 613. The first insulating layer 601 is disposed on the substrate 101. The plurality of conductive features are disposed in the first layer of insulating layer 601. The plurality of conductive features includes the first contact plug 401 and the plurality of second contact plugs 403. The first contact plug 401 is disposed on the first doping region 301 and electrically connected to the first doping region 301. The second contact plugs 403 are respectively disposed on the second doping regions 303 and electrically connected to the second doping regions 303. In the illustrated embodiment, the first contact plug 401 includes tungsten.

Referring to fig. 28, the second insulating layer 603 is disposed on the first insulating layer 601. The bit line contact plugs 405 are disposed in the second insulating layer 603. (only one bit line contact plug 405 is shown in FIG. 28) the cover layer 407 is disposed in the second insulating layer 603 and on the top surface of the bonding pad 701 (only one bonding pad 701 is shown in FIG. 28); in other words, the cover layer 407 is disposed between the corresponding bit line contact plug 405 and the connecting pad 701. In addition, the capping layer 407 is attached to the sidewalls of the bit line contact plugs 405. The capping layer 407 comprises tungsten nitride.

Referring to fig. 28, the third insulating layer 605 is disposed on the second insulating layer 603. The bit lines 409 are disposed in the third insulating layer 605 and on the bit line contact plugs 405 and the cap layer 407. (only one bit line 409 is shown in FIG. 28.) the first plugs 411 penetrate through the third insulating layer 605 and the second insulating layer 603. The plurality of first plugs 411 are electrically connected to the plurality of second contact plugs 403, respectively. The fourth insulating layer 607 is disposed on the third insulating layer 605. The bonding pad 701 is disposed in the second insulating layer 603, wherein the bonding pad 701 is disposed under the cap layer 407.

Referring to fig. 28, the fifth insulating layer 609 is disposed on the fourth insulating layer 607. The plurality of capacitor structures 500 are disposed in the fifth insulating layer 609. The plurality of capacitor structures 500 includes a plurality of bottom electrodes 501, a capacitor insulating layer 503, and a top electrode 505. The bottom electrodes 501 are disposed in the fifth insulating layer 609. The capacitor insulating layer 503 is disposed on the plurality of bottom electrodes 501. The top electrode 505 is disposed on the capacitor insulating layer 503.

Referring to fig. 28, the sixth insulating layer 611 is disposed on the top electrode 505. The bottom via 415 is disposed in the sixth insulating layer 611 and electrically connected to the top electrode 505. The bottom via 415 comprises tungsten. The seventh insulating layer 613 is disposed on the sixth insulating layer 611. The conductive layer 417 is disposed in the seventh insulating layer 613 and above the bottom via 415.

One aspect of the present disclosure discloses a semiconductor device, which includes a substrate, a plurality of conductive features disposed above the substrate, a plurality of connecting pads disposed above the substrate, a cover layer disposed above the substrate, and a plurality of capacitor structures disposed above the substrate, wherein an included angle between axes of two adjacent connecting pads is less than 180 degrees.

Another aspect of the present disclosure provides a method for fabricating a semiconductor device, which includes providing a substrate, forming a plurality of conductive features over the substrate, forming a capping layer over the substrate, and forming a plurality of connection pads over the substrate, wherein an included angle between axes of two adjacent connection pads is less than 180 degrees.

Due to the design of the semiconductor device of the present disclosure, the non-isotropic bonding pads 701 can improve the flexibility of the bonding geometry in the semiconductor device, and thus the tolerance of the alignment of the semiconductor device will be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.