阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 刘承勇 李钟振 金洛焕 郑恩志 洪元赫 于 2020-08-05 设计创作，主要内容包括：提供了半导体装置。所述半导体装置包括设置在基底上并具有第一沟槽的第一层间绝缘膜。第一下导电图案填充第一沟槽并且包括在与基底的上表面平行的第一方向上彼此间隔开的第一谷区域和第二谷区域。第一谷区域和第二谷区域朝向基底凹陷。第二层间绝缘膜设置在第一层间绝缘膜上并且包括暴露第一下导电图案的至少一部分的第二沟槽。上导电图案填充第二沟槽并且包括上阻挡膜和设置在上阻挡膜上的上填充膜。上导电图案至少部分地填充第一谷区域。(A semiconductor device is provided. The semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. The first lower conductive pattern fills the first trench and includes a first valley region and a second valley region spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley regions are recessed toward the substrate. The second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of the first lower conductive pattern. The upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The top conductive pattern at least partially fills the first valley region.)

1. A semiconductor device, the semiconductor device comprising:

a first interlayer insulating film disposed on the substrate and including a first trench;

a first lower conductive pattern filling the first trench and including first and second valley regions spaced apart from each other in a first direction parallel to an upper surface of the substrate, the first and second valley regions being recessed toward the substrate;

a second interlayer insulating film disposed on the first interlayer insulating film and including a second trench exposing at least a portion of the first lower conductive pattern; and

an upper conductive pattern filling the second trench and including an upper barrier film and an upper filling film disposed on the upper barrier film,

wherein the upper conductive pattern at least partially fills the first valley region.

2. The semiconductor device of claim 1, wherein the upper conductive pattern also at least partially fills the second valley region.

3. The semiconductor device according to claim 2, wherein the upper barrier film completely fills at least one of the first and second valley regions.

4. The semiconductor device according to claim 2,

the top surface of the first lower conductive pattern includes first and second valley portions defining first and second valley regions, respectively, and

the upper barrier film extends along all surfaces of the first and second valley portions.

5. The semiconductor device according to claim 2,

the top surface of the first lower conductive pattern includes first and second valley portions defining first and second valley regions, respectively, and

the upper barrier film extends along a partial portion of the surface of the first and second valley portions.

6. The semiconductor device according to claim 1, wherein a depth of the first valley region is the same as a depth of the second valley region.

7. The semiconductor device according to claim 1,

the first lower conductive pattern includes a lower barrier film and an under fill film disposed on the lower barrier film, and

the first and second valley regions are defined by upper surfaces of the lower filling film and portions of the upper surface of the lower barrier film that are not covered by the lower filling film.

8. The semiconductor device according to claim 7,

the first lower conductive pattern further includes a lower liner disposed between the lower barrier film and the lower filling film, and

bottom portions of the first and second valley regions are defined by the underlying liner.

9. The semiconductor device of claim 1, wherein the second valley region is filled with an insulating material.

10. The semiconductor device according to claim 1, wherein the second valley region comprises a wiring void.

11. The semiconductor device according to claim 1, further comprising:

a second lower conductive pattern disposed in the first interlayer insulating film and spaced apart from the first lower conductive pattern in the first direction,

wherein the second lower conductive pattern includes a third valley region and a fourth valley region spaced apart from each other in the first direction, and

wherein at least one of the third and fourth valley regions is filled with an insulating material.

12. The semiconductor device according to claim 1, further comprising:

a second lower conductive pattern disposed in the first interlayer insulating film and spaced apart from the first lower conductive pattern in the first direction,

wherein the second lower conductive pattern includes a third valley region and a fourth valley region spaced apart from each other in the first direction, and

wherein at least one of the third valley region and the fourth valley region includes a wiring void.

13. A semiconductor device, the semiconductor device comprising:

a lower conductive pattern including a lower barrier film defining a filled film trench and a lower filled film disposed on the lower barrier film in the filled film trench, the lower conductive pattern having a top surface with a first width in a first direction parallel to an upper surface of the substrate; and

an upper conductive pattern disposed on the lower conductive pattern, the upper conductive pattern being connected to the lower conductive pattern and including an upper barrier film and an upper filling film disposed on the upper barrier film,

wherein the bottom surface of the upper conductive pattern has a second width in the first direction,

wherein the second width is greater than or equal to the first width, and

the upper barrier film covers a portion of the lower barrier film defining sidewalls of the filled film trench.

14. The semiconductor device according to claim 13,

the top surface of the lower conductive pattern includes a first valley portion and a second valley portion, and

the first and second valley portions are defined by a portion of the lower barrier film covered by the upper barrier film and the lower filling film.

15. The semiconductor device according to claim 14,

the first valley portion defines a first valley region extending in a second direction crossing the first direction,

the second valley portion defines a second valley region extending in the second direction, and

the first and second valley regions are spaced apart from each other in the first direction.

16. The semiconductor device according to claim 13,

the lower conductive pattern further includes a lower liner disposed between the lower barrier film and the lower filling film, and

the uppermost portion of the lower liner is lower than the uppermost portion of the lower barrier film and the uppermost portion of the lower fill film.

17. A semiconductor device, the semiconductor device comprising:

a first interlayer insulating film disposed on the substrate and including a first trench;

a lower conductive pattern disposed in the first trench and including a lower barrier film, a lower liner disposed on the lower barrier film, and a lower filling film disposed on the lower liner;

a second interlayer insulating film disposed on the first interlayer insulating film and including a second trench exposing at least a portion of a top surface of the lower conductive pattern; and

an upper conductive pattern filling the second trench and including an upper barrier film and an upper filling film disposed on the upper barrier film,

wherein the lower conductive pattern further includes a valley region defined by the lower barrier film, the lower liner and the under fill film and extending in a thickness direction of the substrate, and

wherein the upper conductive pattern fills the valley region.

18. The semiconductor device according to claim 17, wherein a width of a top surface of the lower conductive pattern is less than or equal to a width of a bottom surface of the upper conductive pattern.

19. The semiconductor device according to claim 17, wherein a lowermost portion of the upper filling film is higher than an uppermost portion of the lower barrier film.

20. The semiconductor device according to claim 17,

the lower barrier film comprises tantalum and is,

the underlying liner comprises cobalt, and

the underfill film includes copper.

Technical Field

The present inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background

In view of the recent trend of the technical progress of electronic devices and the miniaturization of electronic devices, semiconductor chips having high integration density and low power consumption have attracted increasing attention. Accordingly, the feature size of semiconductor devices has been continuously reduced to meet these requirements.

As the feature size of semiconductor devices has been reduced, various studies have been made on the manner of stably connecting wirings.

Disclosure of Invention

Exemplary embodiments of the inventive concept provide a semiconductor device with improved performance and reliability.

Exemplary embodiments of the inventive concept also provide a method of manufacturing a semiconductor device with improved performance and reliability.

However, the exemplary embodiments of the inventive concept are not limited to the exemplary embodiments set forth herein. The foregoing and other exemplary embodiments of the inventive concept will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an exemplary embodiment of the inventive concept, a semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. The first lower conductive pattern fills the first trench and includes a first valley region and a second valley region spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley regions are recessed toward the substrate. The second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of the first lower conductive pattern. The upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The top conductive pattern at least partially fills the first valley region.

According to an exemplary embodiment of the inventive concept, a semiconductor apparatus includes a lower conductive pattern including a lower barrier film defining a filled film trench and a lower filling film disposed on the lower barrier film in the filled film trench. The lower conductive pattern has a top surface having a first width in a first direction parallel to an upper surface of the substrate. The upper conductive pattern is disposed on the lower conductive pattern. The upper conductive pattern is connected to the lower conductive pattern, and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The bottom surface of the upper conductive pattern has a second width in the first direction. The second width is greater than or equal to the first width. The upper barrier film covers a portion of the lower barrier film defining sidewalls of the filled film trench.

According to the foregoing and other exemplary embodiments of the present inventive concept, a semiconductor device includes a first interlayer insulating film disposed on a substrate and including a first trench. The lower conductive pattern is disposed in the first trench and includes a lower barrier film. The lower liner is disposed on the lower barrier film. The underfill film is disposed on the underfill pad. The second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of a top surface of the lower conductive pattern. The upper conductive pattern fills the second trench, and includes an upper barrier film and an upper fill film disposed on the upper barrier film. The lower conductive pattern further includes a valley region defined by the lower barrier film, the lower liner, and the lower filling film and extending in a thickness direction of the substrate. The upper conductive pattern fills the valley region.

According to the foregoing and other exemplary embodiments of the present inventive concept, a method of manufacturing a semiconductor device includes forming a lower conductive pattern in a first interlayer insulating film, the lower conductive pattern including a valley region extending in a thickness direction of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film, the second interlayer insulating film including a trench exposing at least a partial portion of a top surface of the lower conductive pattern. An upper barrier film is formed along the sidewalls of the trench and the surface of the valley region. An upper fill film is formed on the upper barrier film.

Other features and other embodiments may be apparent from the accompanying description, the drawings, and the claims.

Drawings

The above and other embodiments and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 2 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 1 according to an exemplary embodiment of the inventive concept;

fig. 3 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 4 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 5 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 6 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 8 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 7 according to an exemplary embodiment of the inventive concept;

fig. 9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 10 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 11 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 10 according to an exemplary embodiment of the inventive concept;

fig. 12 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 13 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 14 and 15 are enlarged cross-sectional views of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept;

fig. 16 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 17 and 18 are enlarged cross-sectional views of a portion Q of the semiconductor device of fig. 16, according to exemplary embodiments of the inventive concept;

fig. 19 is an enlarged cross-sectional view of a portion Q of the semiconductor device of fig. 16 according to an exemplary embodiment of the inventive concept;

fig. 20 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 21 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 22 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 23 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

fig. 24 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept; and

fig. 25 to 29 are sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Detailed Description

Fig. 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 2 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 1 according to an exemplary embodiment of the inventive concept.

Referring to fig. 1 and 2, the semiconductor apparatus may include a first lower conductive pattern 200_1, a second lower conductive pattern 200_2, and an upper conductive pattern 300.

The semiconductor device includes a substrate 100. In an exemplary embodiment, the substrate 100 may be a bulk silicon (bulk silicon) substrate or a silicon-on-insulator (SOI) substrate. In another exemplary embodiment, the substrate 100 may be a silicon substrate, or may include at least one material selected from silicon germanium, Silicon Germanium On Insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide. However, exemplary embodiments of the inventive concept are not limited thereto.

The substrate 100 may further include a conductive pattern. In exemplary embodiments, the conductive pattern may be a metal wiring, a contact, a conductive pad, a gate electrode and source/drain of a transistor, or a diode. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the substrate 100 may include a transistor formed in a front-end-of-line (FEOL) process or a contact wiring formed in a middle-end-of-line process. In addition, the substrate 100 may include connection wirings formed in a back end of line (BEOL) process.

The lower interlayer insulating film 110 may be disposed on the substrate 100 (e.g., in the second direction D2 that is the thickness direction of the substrate 100). For example, as shown in the exemplary embodiment of fig. 1, the lower surface of the lower interlayer insulating film 110 may be in direct contact with the upper surface of the substrate 100. The lower interlayer insulating film 110 may include at least one lower pattern trench 200 t.

In an exemplary embodiment, the lower interlayer insulating film 110 may include at least one compound selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. For example, the lower interlayer insulating film 110 may include a low-k material to reduce the occurrence of a coupling phenomenon between adjacent conductive patterns. The low-k material may be a material having sufficient amounts of carbon and hydrogen, such as, for example, SiCOH.

The dielectric constant of the low-k material can be further reduced because of the inclusion of carbon in the low-k material. In an exemplary embodiment, the low-k material may include pores or cavities filled with gas or air to further reduce the dielectric constant of the low-k material.

In exemplary embodiments, the low-k material may include at least one compound selected from tetraethyl orthosilicate (FTEOS), Hydrogen Silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), Octamethylcyclotetrasiloxane (OMCTS), Hexaethyldisiloxane (HMDS), Trimethylsilylborate (TMSB), diacetoxy di-tert-butoxysilane (DADBS), Trimethylsilylphosphate (TMSP), Polytetrafluoroethylene (PTFE), tosz (tonen silazen), Fluoride Silicate Glass (FSG), polyimide nanofoam, polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, aerogel, silica xerogel, mesoporous silica, and combinations thereof. However, exemplary embodiments of the inventive concept are not limited thereto.

The first and second lower conductive patterns 200_1 and 200_2 may be disposed on the substrate 100 and may be spaced apart from each other in a first direction D1, the first direction D1 being parallel to the upper surface of the substrate 100 and crossing the second direction D2. The first and second lower conductive patterns 200_1 and 200_2 may be disposed in the lower interlayer insulating film 110.

The first and second lower conductive patterns 200_1 and 200_2 may fill the lower pattern trench 200 t.

The first lower conductive pattern 200_1 may be connected to the upper conductive pattern 300. As shown in the exemplary embodiment of fig. 1, the second lower conductive pattern 200_2 may not be connected to the upper conductive pattern 300. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, at least one second lower conductive pattern 200_2 may be connected to a conductive pattern spaced apart from the upper conductive pattern 300 in the upper interlayer insulating film 130 in a third direction D3, the third direction D3 being parallel to the upper surface of the substrate and crossing the first and second directions D1 and D2.

The first and second lower conductive patterns 200_1 and 200_2 may each include a lower barrier film 210 and an underfill film 220. The lower filling film 220 may be disposed on the lower barrier film 210.

The lower barrier film 210 may extend along sidewalls and a bottom of each lower pattern trench 200 t. The lower barrier film 210 may define a filling film trench 210t in the lower pattern trench 200 t.

The lower filling film 220 may fill the lower pattern trench 200t in which the lower barrier film 210 is formed. The underfill film 220 may at least partially fill the underfill film trench 210 t.

As shown in the exemplary embodiment of fig. 1, the second lower conductive pattern 200_2 may further include a cover film 230 disposed on an upper surface of the lower filling film 220 (e.g., in the second direction D2). In an exemplary embodiment, the first lower conductive pattern 200_1 may not include the cover film 230 in a portion thereof connected to the upper conductive pattern 300. However, the first lower conductive pattern 200_1 may include the cover film 230 in a portion thereof not connected to the upper conductive pattern 300. Although the exemplary embodiment illustrated in fig. 1 illustrates the cover film 230 as being formed on the upper surface of the lower filling film 220 in each of the second lower conductive patterns 200_2, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the cover film 230 may also be formed on at least one sidewall and/or bottom surface of the lower barrier film 210 in each of the second lower conductive patterns 200_ 2.

In an exemplary embodiment, the lower barrier film 210 may include at least one material selected from tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), Vanadium Nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). However, exemplary embodiments of the inventive concept are not limited thereto. For example, the lower barrier film 210 may include Ta.

The under fill film 220 may include at least one material selected from aluminum (Al), Cu, W, and Co. However, exemplary embodiments of the inventive concept are not limited thereto. In embodiments where the underfill film 220 includes Cu, the underfill film 220 may further include at least one material selected from carbon (C), Ag, Co, Ta, indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), Al, and Zr.

In an exemplary embodiment, the capping film 230 may include at least one of Co, Ru, and Mn. However, exemplary embodiments of the inventive concept are not limited thereto.

The shape of the first lower conductive pattern 200_1 will be described hereinafter with reference to fig. 2. The shape of the second lower conductive pattern 200_2 is substantially the same as that of the first lower conductive pattern 200_1, and thus, a detailed description thereof will be omitted.

Referring to fig. 2, the first lower conductive pattern 200_1 may include a first valley region 200Va and a second valley region 200 Vb. The first and second valley regions 200Va and 200Vb may be spaced apart from each other in the first direction D1.

The first and second valley regions 200Va and 200Vb may be regions recessed toward the substrate 100. The first and second valley regions 200Va and 200Vb may be recess regions formed in the first lower conductive pattern 200_1, and may have a recess shape.

The first and second valley regions 200Va and 200Vb may be formed on a top surface 200us of the first lower conductive pattern 200_1 (such as a top surface of the lower filling film 220). For example, the first and second valley regions 200Va and 200Vb may extend in the thickness direction of the lower interlayer insulating film 110 (e.g., in the second direction D2). The first and second valley regions 200Va and 200Vb may be recessed regions extending in the second direction D2.

The lower barrier film 210 may include a bottom portion 210b and first and second sidewall portions 210sa and 210sb, the bottom portion 210b extending (e.g., substantially in the first direction D1) along the bottom of the lower pattern trench 200t and corresponding to the first lower conductive pattern 200_1, the first and second sidewall portions 210sa and 210sb extending along the sidewall of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1 and being spaced apart from each other in the first direction D1. The first and second sidewall portions 210sa and 210sb may extend substantially in the second direction D2 along the sidewall of the lower pattern groove 200t corresponding to the first lower conductive pattern 200_ 1.

First sidewall portion 210sa and second sidewall portion 210sb extend from base portion 210 b. The filling film trench 210t corresponding to the first lower conductive pattern 200_1 may be defined by the first and second sidewall portions 210sa and 210sb and the bottom portion 210 b.

As shown in the exemplary embodiment of fig. 2, the top surface of the lower filling film 220 may be upwardly convex (e.g., in the second direction D2). As a result, a side edge portion (e.g., a side edge in the first direction D1) of the top surface of the lower filling film 220 may have a height (e.g., a distance from the upper surface of the substrate 100 in the second direction D2) lower than upper portions of the first and second side wall portions 210sa and 210sb of the lower barrier film 210. For example, as shown in the exemplary embodiment of fig. 2, the side edge portion of the lower filling film 220 may not cover the upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 (which define the sidewall of the filling film trench 210t corresponding to the first lower conductive pattern 200_ 1).

The first and second valley regions 200Va and 200Vb may be defined by a height difference between side edge portions of the top surface of the lower barrier film 210 and an upper portion of the lower filling film 220. The first and second valley regions 200Va and 200Vb may be regions between the top surface of the under fill film 220 and the first and second sidewall portions of the lower barrier film 210 that are not covered by the under fill film 220.

For example, as shown in the exemplary embodiment of fig. 2, the first and second valley regions 200Va and 200Vb may have a generally triangular cross-sectional shape. However, in other exemplary embodiments, the top surface of the lower filling film 220 may have other shapes than the upwardly convex shape shown in the exemplary embodiment of fig. 1 to 2, and the concave regions forming the first and second valley regions 200Va and 200Vb may have various different shapes defined by the lower filling film 220 and the lower barrier film 210.

The first lower conductive pattern 200_1 may include a top surface 200us that is curved (e.g., upwardly convex in the second direction D2). For example, the top surface 200us of the first lower conductive pattern 200_1 may include a first valley portion 200us _1, a second valley portion 200us _2, a first protrusion portion 200us _3, a second protrusion portion 200us _4, and a valley connecting portion 200us _5 connecting the first valley portion 200us _1 and the second valley portion 200us _ 2.

The first protruding part 200us _3 may include a top surface of the first sidewall portion 210sa of the lower barrier film 210, and the second protruding part 200us _4 may include a top surface of the second sidewall portion 210sb of the lower barrier film 210. The first valley portion 200us _1 may include one side edge (e.g., a left side edge) of the top surface of the underfill film 220 and a portion of the first sidewall portion 210sa of the adjacent lower barrier film 210 that is not covered by the underfill film 220. The second valley portion 200us _2 may include the other side edge (e.g., right side edge) of the top surface of the underfill film 220 and a portion of the second sidewall portion 210sb of the adjacent lower barrier film 210 that is not covered by the underfill film 220. The valley connecting portion 200us _5 may include a top surface of the underfill film 220 (e.g., in the first direction D1) extending between the first valley portion 200us _1 and the second valley portion 200us _ 2. In an exemplary embodiment, the valley connecting portion 200us _5 may be substantially flat. However, exemplary embodiments of the inventive concept are not limited thereto.

The first and second valley portions 200us _1 and 200us _2 may be defined by the underfill film 220 and upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 that are not covered by the underfill film 220. The valley connecting portion 200us _5 may be defined by an upper portion of the underfill film 220 (e.g., in the first direction D1) extending between the first valley portion 200us _1 and the second valley portion 200us _ 2.

The first valley region 200Va may be defined by a first valley portion 200us _1 of the top surface 200us of the first lower conductive pattern 200_ 1. The second valley region 200Vb may be defined by a second valley portion 200us _2 of the top surface 200us of the first lower conductive pattern 200_ 1.

For example, the upper surface of the first valley region 200Va may extend between the uppermost portion (e.g., in the second direction D2) of the first sidewall portion 210sa of the lower barrier film 210, which defines the filling film trench 210t corresponding to the first lower conductive pattern 200_1, and the uppermost portion (e.g., in the first direction D1) of the lower filling film 220 (e.g., in the second direction D2). The bottom of the first valley region 200Va may correspond to a region where the upper portion of the first sidewall portion 210sa of the lower barrier film 210 and the side edge of the top surface of the lower filling film 220 meet.

The first valley region 200Va may have a first depth D1 (e.g., a length in the second direction D2) with respect to a top surface of the first lower conductive pattern 200_1 (e.g., an uppermost portion of the lower filling film 220), and the second valley region 200Vb may have a second depth D2 with respect to an uppermost portion of the lower filling film 220. As shown in the exemplary embodiment of fig. 2, the first depth d1 may be the same as the second depth d 2. However, in other exemplary embodiments of the inventive concept, the first depth d1 and the second depth d2 may be different from each other.

The first sidewall part 210sa of the lower barrier film 210 may have a first height h1 (e.g., a length in the second direction D2) with respect to the bottom of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1, and the second sidewall part 210sb of the lower barrier film 210 may have a second height h2 (e.g., a length in the second direction D2) with respect to the bottom of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_ 1. As shown in the exemplary embodiment of fig. 2, the first height h1 may be the same as the second height h 2. However, exemplary embodiments of the inventive concept are not limited thereto.

Like the first lower conductive pattern 200_1, the second lower conductive patterns 200_2 may each include first and second valley regions 200Va and 200Vb spaced apart from each other in the first direction D1. The depth (e.g., the length from the top surface to the bottom surface in the second direction D2) of the first valley region 200Va of the second lower conductive pattern 200_2 may be the same as or different from the depth of the second valley region 200Vb of the second lower conductive pattern 200_ 2.

The etch stop film 120 may be disposed on the lower interlayer insulating film 110. The etch stop film 120 may cover the top surface of the lower interlayer insulating film 110 and the top surface of the second lower conductive pattern 200_ 2. For example, as shown in the exemplary embodiment of fig. 1, the lower surface of the etch stop film 120 may be in direct contact with the upper surface of the capping film 230 of the second lower conductive pattern 200_2 and the upper surface of the lower interlayer insulating film 110.

In an exemplary embodiment, the etch stop film 120 may include, for example, a silicon-based insulating material. The etch stop film 120 may include a silicon-based insulating material film. For example, the etch stop film 120 may include at least one compound selected from silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbonate (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonitride (SiOCN). However, exemplary embodiments of the inventive concept are not limited thereto. In the present specification, the term "silicon oxycarbonitride" merely means that the corresponding material contains silicon (Si), carbon (C), and oxygen (O), and does not necessarily mean any specific ratio of Si, C, and O in the corresponding material.

The first and/or second valley regions 200Va and 200Vb of the second lower conductive pattern 200_2 may be filled with an insulating material.

For example, as shown in the exemplary embodiment of fig. 1 to 2, both the first and second valley regions 200Va and 200Vb of the second lower conductive pattern 200_2 are filled with an insulating material. The etch stop film 120 may fill the first and second valley regions 200Va and 200Vb of the second lower conductive pattern 200_ 2. However, exemplary embodiments of the inventive concept are not limited thereto.

The upper interlayer insulating film 130 may be disposed on the etch stop film 120. For example, as shown in the exemplary embodiments of fig. 1 to 2, a lower portion of the upper interlayer insulating film 130 may be in direct contact with an upper portion of the etch stop film 120. The upper interlayer insulating film 130 may include an upper pattern trench 300 t. The upper pattern trench 300t may extend into the etch stop film 120. For example, as shown in the exemplary embodiment of fig. 1, the upper pattern trench 300t may extend through the etch stop film 120.

The upper pattern trench 300t may expose at least a portion of the first lower conductive pattern 200_ 1. The upper pattern trench 300t may include a first upper via trench 301t and an upper routing trench 305 t. At least a partial portion of the first lower conductive pattern 200_1 may be exposed by the first upper via trench 301 t.

In an exemplary embodiment, the upper interlayer insulating film 130 may include at least one compound selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. However, exemplary embodiments of the inventive concept are not limited thereto.

The upper conductive pattern 300 may be disposed in the upper interlayer insulating film 130. As shown in the exemplary embodiment of fig. 1, the upper conductive pattern 300 may fill the upper pattern trench 300 t. The upper conductive pattern 300 may be connected to the first lower conductive pattern 200_ 1.

The upper conductive pattern 300 may include an upper barrier film 310 and an upper filling film 320. The upper fill film 320 may be disposed on the upper barrier film 310.

The upper barrier film 310 may extend along sidewalls and a bottom of the upper pattern trench 300 t. The upper barrier film 310 may extend along sidewalls of the first upper via trench 301t and along sidewalls and a bottom of the upper routing trench 305 t. A portion of the upper barrier film 310 may extend along the top surface 200us of the first lower conductive pattern 200_ 1. The upper filling film 320 may fill the upper pattern trench 300t in which the upper barrier film 310 is formed.

The upper conductive pattern 300 may include a first upper via 301 filling the first upper via trench 301t and an upper connection wire 305 filling the upper wire trench 305 t.

In an exemplary embodiment, the upper barrier film 310 may include at least one material selected from Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, W, WN, WCN, Zr, ZrN, V, VN, Nb, NbN, Pt, Ir, and Rh. However, exemplary embodiments of the inventive concept are not limited thereto.

In an exemplary embodiment, the upper fill film 320 may include at least one material selected from Al, Cu, W, and Co. However, exemplary embodiments of the inventive concept are not limited thereto.

In the exemplary embodiment shown in fig. 1, the cover film 230 is not formed on the upper filling film 320. However, exemplary embodiments of the inventive concept are not limited thereto. Further, in the exemplary embodiment shown in fig. 1, a valley region is not formed between the upper filling film 320 and the upper barrier film 310. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in an alternative embodiment, the upper conductive pattern 300 may include at least one valley region, like the first and second lower conductive patterns 200_1 and 200_ 2.

In the exemplary embodiment shown in fig. 1, the upper fill film 320 included in the first upper via hole 301 and the upper fill film 320 included in the upper connection wiring 305 are directly connected to each other. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the upper barrier film 310 may be disposed between the upper fill film 320 included in the first upper via hole 301 and the upper fill film 320 included in the upper connection wiring 305.

The upper conductive pattern 300 may fill at least one of the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1. For example, as shown in the exemplary embodiments of fig. 1 to 2, the upper conductive pattern 300 may fill both the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1.

In an exemplary embodiment, the upper barrier film 310 may completely fill at least one of the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1. For example, as shown in the exemplary embodiments of fig. 1 to 2, the upper barrier film 310 may completely fill both the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1.

In the present specification, the expression "one element completely fills another element" means that one element completely fills another element in a cross-sectional view (for example, when viewed from the third direction D3).

Since the upper barrier film 310 completely fills the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_1, the level of the lowermost portion of the upper filling film 320 disposed on the upper barrier film 310 (e.g., the distance from the upper surface of the substrate 100 in the second direction D2) may be higher than the level of the uppermost portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210. For example, the upper barrier film 310 may be disposed between the lowermost portion of the upper filling film 320 and the uppermost portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 in the second direction D2.

The upper conductive pattern 300 may cover upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210, which define sidewalls of the filling film trench 210t corresponding to the first lower conductive pattern 200_ 1. For example, the upper barrier film 310 may cover portions of the first and second sidewall portions 210sa and 210sb (which define sidewalls of the filling film trench 210t corresponding to the first lower conductive pattern 200_ 1) of the lower barrier film 210.

The first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_1 may be defined by the top surface of the lower filling film 220 and upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 that are not covered by the lower filling film 220. As shown in the exemplary embodiment of fig. 1 to 2, the upper barrier film 310 may cover the first and second valley regions 200Va and 200 Vb. The first and second valley portions 200us _1 and 200us _2 of the top surface 200us of the first lower conductive pattern 200_1 may be defined by the top surface of the lower filling film 220 and portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 covered by the upper barrier film 310. The first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_1 may be regions between side edges of the top surface of the lower filling film 220 and upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 covered by the upper barrier film 310.

The bottom surface of the upper conductive pattern 300 may be the bottom surface 301bs of the first upper via 301 and portions of the upper barrier film 310 extending within the first and second valley regions 200Va and 200 Vb. As shown in the exemplary embodiment of fig. 2, a width W1 (e.g., a length in the first direction D1) of the top surface 200us of the first lower conductive pattern 200_1 may be smaller than a width W2 (e.g., a length in the first direction D1) of the bottom surface 301bs of the upper conductive pattern 300.

As shown in the exemplary embodiment of fig. 1, in the cross-sectional view, the bottom surface 301bs of the upper conductive pattern 300 may completely cover the top surface 200us of the first lower conductive pattern 200_1 (e.g., in the first direction D1).

Fig. 3 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. Fig. 4 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. Fig. 5 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. Fig. 6 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. For convenience, the semiconductor device of fig. 3 to 6 will be described hereinafter mainly focusing on differences from the semiconductor device of fig. 1 and 2.

Fig. 3 to 6 are enlarged cross-sectional views of portions of semiconductor devices according to some exemplary embodiments of the inventive concept corresponding to the portion P of fig. 1.

Referring to fig. 3, the first depth d1 of the first valley region 200Va may be different from the second depth d2 of the second valley region 200 Vb.

For example, the height (e.g., the length in the second direction D2) of the upper portion of the first sidewall part 210sa of the lower barrier film 210 not covered by the underfill film 220 may be different from the height of the upper portion of the second sidewall part 210sb of the lower barrier film 210 not covered by the underfill film 220.

For example, the height (e.g., the length in the second direction D2) of the upper portion of the first sidewall part 210sa of the lower barrier film 210 covered by the upper barrier film 310 may be different from the height of the upper portion of the second sidewall part 210sb of the lower barrier film 210 covered by the upper barrier film 310. As shown in the exemplary embodiment of fig. 3, the second depth d2 of the second valley region 200Vb may be greater than the first depth d1 of the first valley region 200 Va. However, exemplary embodiments of the inventive concept are not limited thereto.

The exemplary embodiment of fig. 3 shows the upper barrier film 310 as completely filling the second valley region 200 Vb. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the second valley region 200Vb may be only partially filled with the upper barrier film 310 and the second valley region 200Vb may also be filled with the upper filling film 320 according to the second depth d2 of the second valley region 200Vb and the thickness of the upper barrier film 310.

As shown in the exemplary embodiment of fig. 4, the first height h1 (e.g., the length in the second direction D2) of the first sidewall portion 210sa of the lower barrier film 210 may be different from the second height h2 of the second sidewall portion 210sb of the lower barrier film 210.

However, the depth of the first valley region 200Va may be the same as the depth of the second valley region 200 Vb.

The height of the upper portion of the first sidewall part 210sa of the lower barrier film 210 not covered by the underfill film 220 may be different from the height of the upper portion of the second sidewall part 210sb of the lower barrier film 210 not covered by the underfill film 220.

Referring to the exemplary embodiment of fig. 5, a width W1 (e.g., a length in the first direction D1) of the top surface 200us of the first lower conductive pattern 200_1 may be the same as a width W2 (e.g., a length in the first direction D1) of the bottom surface 301bs of the upper conductive pattern 300.

In the exemplary embodiment shown in fig. 5, the first upper via hole 301 of the upper conductive pattern 300 may be disposed to be aligned with the first lower conductive pattern 200_ 1. For example, the sidewalls forming the first upper via hole 301 and the first and second sidewall portions 210sa and 210sb of the first lower conductive pattern 200_1 may be aligned in the second direction D2.

Referring to the exemplary embodiment of fig. 6, the top surface 200us of the first lower conductive pattern 200_1 may not include the valley connecting portion 200us _ 5.

The first valley portion 200us _1 of the top surface 200us of the first lower conductive pattern 200_1 may be directly connected to the second valley portion 200us _2 of the top surface 200 us. In this embodiment, the top surface of the underfill film 220 may be generally curved and may not be flat. Accordingly, the curved surface of the top surface of the lower filling film 220 may form a portion of the first valley portion 200us _1 and a portion of the second valley portion 200us _2 of the top surface 200us, and the uppermost surface of the top surface 200us of the first lower conductive pattern 200_1 may form a common edge of the first valley portion 200us _1 and the second valley portion 200us _ 2.

Fig. 7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 8 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 7 according to an exemplary embodiment of the inventive concept. The semiconductor device of fig. 7 and 8 will be described hereinafter mainly focusing on differences from the semiconductor device of fig. 1 and 2.

Referring to fig. 7 and 8, each of the first and second lower conductive patterns 200_1 and 200_2 may further include a lower pad 240. The upper conductive pattern 300 may further include an upper pad 330.

The lower liner 240 may be disposed between the lower barrier film 210 and the lower filling film 220. The lower gasket 240 may be disposed on the lower barrier film 210. For example, the lower liner 240 may be formed along a partial portion of the contour of the lower barrier film 210.

The underlying liner 240 may extend along a portion of the sidewall of each of the filled film trenches 210t and the bottom of each of the filled film trenches 210 t. The lower spacer 240 may not cover the upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210.

Referring to fig. 8, the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_1 may be defined by the side edges of the lower filling film 220, the lower barrier film 210, and the lower liner 240. The first and second valley regions 200Va and 200Vb may be defined by upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 that are not covered by the lower liner 240, a top surface of the lower liner 240, and side edges (e.g., in the first direction D1) of the top surface of the lower filling film 220.

The first valley portion 200us _1 of the top surface 200us of the first lower conductive pattern 200_1 may include a left side edge of the top surface of the lower filling film 220, a left top surface of the lower liner 240, and an upper portion of the first sidewall portion 210sa of the lower barrier film 210 not covered by the lower liner 240. The second valley portion 200us _2 of the top surface 200us of the first lower conductive pattern 200_1 may include a right side edge of the top surface of the lower filling film 220, a right top surface of the lower liner 240, and an upper portion of the second sidewall portion 210sb of the lower barrier film 210 not covered by the lower liner 240.

The uppermost portion of the lower gasket 240 (e.g., in the second direction D2) may be lower than the uppermost portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210. The uppermost portion of the lower liner 240 may be lower than the uppermost portion of the lower fill film 220.

The bottom portions of the first and second valley regions 200Va and 200Vb may be defined by the lower liner 240 (such as the uppermost portion of the lower liner 240).

The upper liner 330 may be disposed between the upper barrier film 310 and the upper filling film 320. The upper liner 330 may be disposed on the upper barrier film 310. The upper liner 330 may be formed along the contour of the upper barrier film 310. For example, the upper liner 330 may cover the bottom surface and the sidewall surface of the upper barrier film 310.

In an exemplary embodiment, the lower and upper spacers 240 and 330 may include at least one material selected from Co, Ru, and Mn. However, exemplary embodiments of the inventive concept are not limited thereto.

Fig. 9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. The semiconductor device of the exemplary embodiment of fig. 9 will be described hereinafter mainly focusing on differences from the semiconductor devices of fig. 1 and 2.

Referring to the exemplary embodiment of fig. 9, at least one of the first and second valley regions 200Va and 200Vb of each of the second lower conductive patterns 200_2 may include a wiring gap 200 ag.

For example, as shown in the exemplary embodiment of fig. 9, both the first valley region 200Va and the second valley region 200Vb may include the wiring void 200 ag. The wiring void 200ag may be formed in each of the first and second valley regions 200Va and 200 Vb. However, exemplary embodiments of the inventive concept are not limited thereto.

One or more wiring voids 200ag may be defined between the lower surface of the etch stop film 120 and the top surface of the side edge of each second lower conductive pattern 200_ 2.

In an alternative embodiment, the first valley region 200Va may be filled with an insulating material, and the wiring void 200ag may be formed only in the second valley region 200 Vb. In another exemplary embodiment, the second valley region 200Vb may be filled with an insulating material, and the wiring void 200ag may be formed only in the first valley region 200 Va.

Fig. 10 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 11 is an enlarged cross-sectional view of a portion P of the semiconductor apparatus of fig. 10 according to an exemplary embodiment of the inventive concept. The semiconductor device of fig. 10 and 11 will be described hereinafter mainly focusing on differences from the semiconductor device of fig. 1 and 2.

Referring to fig. 10 and 11, the upper barrier film 310 may extend along the contour of the top surface 200us of the first lower conductive pattern 200_ 1.

For example, as shown in the exemplary embodiments of fig. 10 to 11, the upper barrier film 310 may extend along the contours of the first protrusion portion 200us _3, the first valley portion 200us _1, the valley connection portion 200us _5, the second valley portion 200us _2, and the second protrusion portion 200us _4 of the top surface of the first lower conductive pattern 200_ 1.

The first and/or second valley regions 200Va and 200Vb of the first lower conductive pattern 200_1 remaining unfilled by the upper barrier film 310 may be filled with the upper filling film 320. For example, as shown in the exemplary embodiments of fig. 10 to 11, the upper barrier films 310 may each have a recess portion extending below the height of the top surfaces of the first and second protruding portions 200us _3 and 200us _ 4. The upper filling film 320 may fill the recessed portion in the upper barrier film 310 to fill the portions of the first and second valley regions 200Va and 200Vb remaining unfilled by the upper barrier film 310.

Fig. 12 is an enlarged cross-sectional view of a portion P of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. The semiconductor device of fig. 12 will be described hereinafter mainly focusing on differences from the semiconductor devices of fig. 10 and 11.

Referring to fig. 12, the upper barrier film 310 may extend along partial portions of the first and second valley portions 200us _1 and 200us _2 of the top surface of the first lower conductive pattern 200_ 1.

For example, the upper barrier film 310 may be formed along upper portions of the first and second sidewall portions 210sa and 210sb of the lower barrier film 210. The upper barrier film 310 may be formed on the first and second valley portions 200us _1 and 200us _2 defined by the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 and the side edges of the top surface of the lower filling film 220.

However, the upper barrier film 310 may not extend along the top surface of the lower filling film 220. For example, as shown in the exemplary embodiment of fig. 12, the upper barrier film 310 may not be formed on at least partial portions of the first and second valley portions 200us _1 and 200us _2 and may not be formed on the valley connecting portion 200us _ 5. For example, portions of the upper barrier film 310 formed along the first and second sidewall portions 210sa and 210sb of the lower barrier film 210 may be disposed on side edges of the top surface of the lower filling film 220. However, as shown in the exemplary embodiment of fig. 12, the upper barrier film 310 may not cover portions of the first and second valley portions 200us _1 and 200us _2 defined by the underfill film 220. For example, the upper barrier film 310 may not cover a partial portion of the side edges of the first and second valley portions 200us _1 and 200us _2 defined by the lower filling film 220, which is away from the first and second sidewall portions 210sa and 210sb, and the relatively flat valley connecting portion 200us _5 defined by the lower filling film 220.

In an exemplary embodiment, a surface treatment may be performed on the top surface of the lower fill film 220 before the upper barrier film 310 is formed. As a result, the upper barrier film 310 may not be formed on the top surface of the lower filling film 220.

Fig. 13 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 14 and 15 are enlarged cross-sectional views of a portion P of the semiconductor apparatus of fig. 13 according to exemplary embodiments of the inventive concept. The semiconductor device of fig. 13 to 15 will be described hereinafter mainly focusing on differences from the semiconductor device of fig. 1 and 2.

Referring to fig. 13 to 15, the upper conductive pattern 300 may fill the first valley region 200Va of the first lower conductive pattern 200_ 1. However, the upper conductive pattern 300 may not fill the second valley region 200Vb of the first lower conductive pattern 200_ 1.

For example, the bottom surface 301bs of the upper conductive pattern 300 may cover only a partial portion of the top surface 200us of the first lower conductive pattern 200_ 1.

As shown in the exemplary embodiment of fig. 13, the cover film 230 may be formed on a portion of the lower filling film 220 that is not covered by the bottom surface 301bs of the upper conductive pattern 300. However, exemplary embodiments of the inventive concept are not limited thereto.

As shown in the exemplary embodiment of fig. 14, the second valley region 200Vb may be filled with an insulating material. For example, a portion of the etching stopper film 120 may be formed in the second valley region 200 Vb. As shown in the exemplary embodiment of fig. 14, the etch stop film 120 may be disposed on the capping film 230. For example, the lower surface of the etch stop film 120 may be in direct contact with the upper surface of the capping film 230.

Referring to the exemplary embodiment shown in fig. 15, the wiring void 200ag may be formed in the second valley region 200 Vb. The wiring void 200ag may be defined between the etch stop film 120 and the cover film 230 disposed on the side edge of the top surface 200us of the first lower conductive pattern 200_1 defining the second valley region 200 Vb.

For example, a width W1 (e.g., a length in the first direction D1) of the top surface 200us of the first lower conductive pattern 200_1 may be greater than a width W2 of the bottom surface 301bs of the upper conductive pattern 300. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the width W1 may be the same as the width W2. In another exemplary embodiment, the width W1 may be less than the width W2.

Fig. 16 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 17 and 18 are enlarged cross-sectional views of a portion Q of the semiconductor apparatus of fig. 16 according to exemplary embodiments of the inventive concept. The semiconductor device of fig. 16 to 18 will be described hereinafter mainly focusing on differences from the semiconductor device of fig. 1 and 2.

Referring to fig. 16 to 18, the etch stop film 120 may include a first sub etch stop film 121 and a second sub etch stop film 122.

The second sub etching stopper film 122 may be disposed on the first sub etching stopper film 121. For example, the lower surface of the second sub etching stopper film 122 may be in direct contact with the upper surface of the first sub etching stopper film 121. The first sub etching stopper film 121 may be disposed (e.g., in the second direction D2) between the second sub etching stopper film 122 and the lower interlayer insulating film 110.

In an exemplary embodiment, the first sub etch stop film 121 may include an insulating material including a metal. Accordingly, the etch stop film 120 may include a metal. For example, in an exemplary embodiment, the first sub etch stop film 121 may include an insulating material including Al. The first sub etch stop film 121 may include at least one compound selected from aluminum oxide (AlO), aluminum nitride (AlN), and aluminum oxycarbide (AlOC). However, exemplary embodiments of the inventive concept are not limited thereto.

In this specification, the term "aluminum oxycarbide" merely means that the corresponding material contains Al, O, and C, and does not necessarily mean any particular proportion of Al, O, and C in the corresponding material.

In an exemplary embodiment, the second sub etch stop film 122 may include a Si-based insulating material. However, exemplary embodiments of the inventive concept are not limited thereto.

As shown in the exemplary embodiment of fig. 17, the etch stop film 120 may include a pit pattern 120 dp. The pit patterns 120dp may be formed at portions defining sidewalls of the upper pattern groove 300 t. Specifically, the pit patterns 120dp may be formed at portions defining sidewalls of the first upper via grooves 301 t. For example, as shown in the exemplary embodiment of fig. 17, the pit patterns 120dp may be formed on the bottom portions of the sidewalls of the upper pattern groove 300 t. The pit pattern 120dp may be a portion recessed into the etch stop film 120. The pit pattern 120dp may be a portion expanded in the first direction D1.

The pit pattern 120dp may be formed on a portion of the sidewall of the first upper via groove 301t defined by the first sub-etch stop film 121. For example, as shown in the exemplary embodiment of fig. 17, the pit patterns 120dp may be formed on two portions of the sidewall of the first upper via groove 301t, which are defined by the first sub-etching stopper film 121. However, exemplary embodiments of the inventive concept are not limited thereto, and the pit pattern 120dp may be formed on only one sidewall of the first upper via groove 301t in other exemplary embodiments. In an exemplary embodiment, since the wet etching has isotropic etching characteristics, the pit pattern 120dp may be formed while removing the first sub-etching stopper film 121 by the wet etching.

The upper barrier film 310 may fill at least a portion of each pit pattern 120 dp. Referring to the exemplary embodiment shown in fig. 17, the upper barrier film 310 may be formed along the contour of the pit pattern 120 dp. The portion of the pit pattern 120dp remaining unfilled may be filled with the upper filling film 320. Accordingly, in these exemplary embodiments, the width of the upper fill film 320 on the same level as the first sub-etching stopper film 121 (e.g., the length in the first direction D1) may be wider than the width of the upper fill film 320 on the same level as the second sub-etching stopper film 122. Referring to the exemplary embodiment shown in fig. 18, the upper barrier film 310 may completely fill the pit pattern 120 dp. The sectional structure shown in the exemplary embodiment of fig. 17 or 18 may be obtained according to the thickness of the first sub-etching stopper film 121 and the degree of etching the first sub-etching stopper film 121.

Fig. 19 is an enlarged cross-sectional view of a portion Q of a semiconductor apparatus according to an exemplary embodiment of the inventive concept. The semiconductor device of fig. 19 will be described hereinafter mainly focusing on differences from the semiconductor devices of fig. 16 to 18.

Referring to the exemplary embodiment of fig. 19, the etch stop film 120 may further include a third sub etch stop film 123.

The third sub-etching stopper film 123 may be disposed on the second sub-etching stopper film 122. For example, as shown in the exemplary embodiment of fig. 19, the lower surface of the third sub etching stopper film 123 may be in direct contact with the upper surface of the second sub etching stopper film 122. In an exemplary embodiment, the third sub-etch stop film 123 may include an insulating material including a metal. Accordingly, the third sub-etching stopper film 123 may include a metal. For example, the third sub-etching stopper film 123 may include an insulating material containing Al. However, exemplary embodiments of the inventive concept are not limited thereto.

The pit pattern 120dp may be formed on a portion of the sidewall of the first upper via groove 301t defined by the first sub-etch stop film 121. The pit pattern 120dp may also be formed on a portion of the sidewall of the first upper via groove 301t defined by the third sub-etch stop film 123. The pit patterns 120dp formed in the sidewalls of the first upper via trench 301t defined by the first and third sub etching stopper films 121 and 123 are spaced apart from each other in the second direction D2.

Fig. 20 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 21 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 22 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. The semiconductor devices shown in the exemplary embodiments of fig. 20 to 22 will be described hereinafter mainly focusing on differences from the exemplary embodiments of the semiconductor devices shown in fig. 1 and 2.

Referring to fig. 20, the upper barrier film 310 may be conformally formed along the upper pattern trench 300 t. However, the lower barrier film 210 may not be conformally formed along the lower pattern trench 200 t.

For example, the thickness of a portion of the upper barrier film 310 at the bottom of the upper wiring trench 305t and extending substantially in the first direction D1 (e.g., the length in the second direction D2) may be substantially the same as the thickness of a portion of the upper barrier film 310 on the sidewall of the upper wiring trench 305t (e.g., the length in the first direction D1).

However, the thickness t11 (e.g., the length in the second direction D2) of a portion of the lower barrier film 210 at the bottom of each lower pattern trench 200t may be greater than the thickness t12 (e.g., the length in the first direction D1) of a portion of the lower barrier film 210 on the sidewalls of each lower pattern trench 200 t.

For example, in an exemplary embodiment, the upper barrier film 310 may be formed by a deposition method having excellent step coverage, and the lower barrier film 210 may be formed by a deposition method having poor step coverage.

Referring to the exemplary embodiment illustrated in fig. 21, the lower barrier film 210 may be conformally formed along the lower pattern trench 200 t. However, the upper barrier film 310 may not be conformally formed along the upper pattern trench 300 t.

For example, the thickness t21 (e.g., the length in the second direction D2) of the portion of the upper barrier film 310 at the bottom of the upper wiring trench 305t may be greater than the thickness t22 (e.g., the length in the first direction D1) of the portion of the upper barrier film 310 on the sidewall of the upper wiring trench 305 t.

However, as shown in the exemplary embodiment of fig. 21, the thickness of the portion of the lower barrier film 210 at the bottom of each lower pattern trench 200t may be substantially the same as the thickness of the portion of the lower barrier film 210 on the sidewall of each lower pattern trench 200 t.

In an exemplary embodiment, the lower barrier film 210 may be formed by a deposition method having excellent step coverage, and the upper barrier film 310 may be formed by a deposition method having poor step coverage.

However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, both the upper and lower barrier films 310 and 210 may not be conformally formed along the upper and lower pattern trenches 300t and 200t, respectively.

Referring to the exemplary embodiment of fig. 22, each of the first lower conductive patterns 200_1 may include a cover film 230.

The cover film 230 may be disposed between the upper conductive patterns 300 and the upper surface of the lower filling film 220 (e.g., in the second direction D2).

Fig. 23 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Fig. 24 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to the exemplary embodiment of fig. 23, the upper conductive pattern 300 may further include a second upper via 302 spaced apart from the first upper via 301 in the first direction D1.

The second upper via 302 may fill the second upper via trench 302 t. The second upper via hole 302 may be connected to the second lower conductive pattern 200_ 2.

As shown in the exemplary embodiment of fig. 23, the bottom of the second upper via hole 302 may completely cover the top surface of the second lower conductive pattern 200_ 2. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the second upper via hole 302 may cover only a partial portion of the top surface of the second lower conductive pattern 200_ 2.

Referring to the exemplary embodiment of fig. 24, the upper conductive pattern 300 may not include an upper connection wiring (such as the upper connection wiring 305 shown in the exemplary embodiment of fig. 1).

In the exemplary embodiment shown in fig. 24, the upper conductive pattern 300 may include only the first upper via hole 301.

Fig. 25 to 29 are sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

Referring to the exemplary embodiment illustrated in fig. 25, the first and second lower conductive patterns 200_1 and 200_2 may be formed in the lower interlayer insulating film 110 on the substrate 100.

Each of the first and second lower conductive patterns 200_1 and 200_2 may include a lower barrier film 210 formed along the lower pattern trench 200t and a lower filling film 220 formed on the lower barrier film 210. The cover film 230 may be formed along the top surface of the underfill film 220.

Each of the first and second lower conductive patterns 200_1 and 200_2 may include first and second valley regions 200Va and 200Vb extending in a thickness direction of the lower interlayer insulating film 110 (e.g., in the second direction D2).

Referring to the exemplary embodiment of fig. 26, the etch stop film 120 and the upper interlayer insulating film 130 may be sequentially formed on the lower interlayer insulating film 110 (e.g., in the second direction D2).

An upper pattern trench 300t exposing at least a partial portion of the first lower conductive pattern 200_1 may be formed in the etch stop film 120 and the upper interlayer insulating film 130. The capping film 230 formed on the lower filling film 220 of the first lower conductive pattern 200_1 may be etched and removed. The upper pattern trench 300t may include a first upper via trench 301t and an upper routing trench 305 t.

Referring to the exemplary embodiment of fig. 27, a preliminary upper barrier film 310p may be formed along sidewalls of the upper pattern trench 300t and the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1.

A preliminary upper barrier film 310p may be formed on the sidewalls of the first upper via trench 301t, the sidewalls and the bottom of the upper wiring trench 305t, and the surfaces of the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1. As shown in the exemplary embodiment of fig. 27, the preliminary upper barrier film 310p may completely fill the first and second valley regions 200Va and 200Vb of the first lower conductive pattern 200_ 1. However, exemplary embodiments of the inventive concept are not limited thereto.

In an exemplary embodiment, the preliminary upper barrier film 310p may be formed by Atomic Layer Deposition (ALD).

Referring to the example embodiment of fig. 28, the preliminary upper barrier film 310p may be densified (e.g., the density of the preliminary upper barrier film 310p is increased) by the densification treatment process 50. As a result, the preliminary upper barrier film 310p may form the upper barrier film 310.

For example, in exemplary embodiments, Physical Vapor Deposition (PVD) may be used for the densification process 50. PVD using a process gas may improve the quality of the preliminary upper barrier film 310 p. For example, almost no additional barrier film may be formed on the preliminary upper barrier film 310p by PVD. However, exemplary embodiments of the inventive concept are not limited thereto, and the densification process 50 may be performed by various different methods.

Referring to an exemplary embodiment of fig. 29, an upper fill film 320 filling the upper pattern trench 300t may be formed on the upper barrier film 310.

Summarizing the detailed description of the exemplary embodiments of the inventive concept, it will be appreciated by those skilled in the art that many variations and modifications may be made to the exemplary embodiments without substantially departing from the principles of the inventive concept. Accordingly, the disclosed exemplary embodiments of the inventive concept are used in a generic and descriptive sense only and not for purposes of limitation.