阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 黄柏瑜 林诗哲 王朝勋 赵高毅 王美匀 于 2020-08-18 设计创作，主要内容包括：公开了一种半导体装置,源极/漏极位于基板上。源极/漏极接点位于源极/漏极上。第一通孔位于源极/漏极接点上。第一通孔具有横向凸出的底部,与位于横向凸出的底部上的顶部。(A semiconductor device is disclosed, source/drain electrodes are located on a substrate. The source/drain contact is located on the source/drain. The first via is located over the source/drain contact. The first through hole has a laterally projecting bottom portion and a top portion located on the laterally projecting bottom portion.)

1. A semiconductor device, comprising:

a source/drain on a substrate;

a source/drain contact located on the source/drain; and

a first via over the source/drain contact, wherein the first via has a laterally protruding bottom and a top over the laterally protruding bottom.

Technical Field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to low resistance source/drain vias.

Background

The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, the functional density (e.g., the number of interconnect devices per unit chip area) generally increases as the geometries (e.g., the smallest features or lines created by the fabrication processes employed) shrink. The process of scaling down is generally advantageous in increasing throughput and reducing associated costs. The shrinking dimensions also increase the complexity of processing and fabricating integrated circuits.

For example, as source/drain vias shrink for each technology generation, the resistance of the source/drain vias may increase. Resistance increase is an undesirable phenomenon because it degrades device performance, such as speed. Although conventional methods of forming source/drain vias are generally suitable, they do not meet all of the requirements.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device including: a source/drain on the substrate; a source/drain contact located on the source/drain; and a first via over the source/drain contact, wherein the first via has a laterally protruding bottom and a top over the laterally protruding bottom.

An embodiment of the present invention provides a semiconductor device including: a source/drain on the substrate; a gate structure on the substrate; a first interlayer dielectric layer on the gate structure; an etch stop layer on the first interlayer dielectric layer; a second interlayer dielectric layer on the etch stop layer; a gate via over the gate structure, wherein the gate via extends vertically through the first interlayer dielectric, the etch stop layer, and the second interlayer dielectric; an adhesion layer between the gate via and the first interlayer dielectric layer, the etch stop layer, and the second interlayer dielectric layer; a source/drain contact on the source/drain, wherein the source/drain contact extends vertically through the first interlayer dielectric layer; and a source/drain via over the source/drain contact, wherein the source/drain via extends vertically through the second interlayer dielectric layer and the etch stop layer, and wherein a sidewall of the source/drain via is in direct physical contact with a sidewall of the etch stop layer and the second interlayer dielectric layer.

Another embodiment of the present invention provides a method for forming a semiconductor device, including: forming a source/drain and gate structure on the substrate; forming a first interlayer dielectric layer on the source/drain and gate structures; forming source/drain contacts on the source/drain, wherein the source/drain contacts extend vertically through the first interlayer dielectric layer; forming an etch stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form a first via hole exposing the source/drain contact; forming a source/drain via in the first via, wherein the source/drain via is in direct physical contact with the source/drain contact, the etch stop layer, and the second interlayer dielectric layer; after the source/drain through hole is formed, etching the second interlayer dielectric layer, the etching stop layer and the first interlayer dielectric layer to form a second through hole exposing the grid structure; and forming a gate through hole in the second through hole.

Drawings

FIG. 1A is a perspective view of an integrated circuit device in various embodiments of the invention.

FIG. 1B is a plan top view of an integrated circuit device, in various embodiments of the invention.

Fig. 2-14 are cross-sectional views of an integrated circuit device at various stages of fabrication, in accordance with various embodiments of the present invention.

FIG. 15 is a top view of an integrated circuit device at a stage of fabrication in accordance with various embodiments of the present invention.

FIG. 16 is a cross-sectional view of an integrated circuit device at a stage of fabrication in accordance with various embodiments of the present invention.

Fig. 17 is a flow chart of a method of fabricating a semiconductor device in various embodiments of the present invention.

Description of reference numerals:

AA': cutting line

90: integrated circuit device

110: substrate

120: fin structure

122: source/drain structure

130: isolation structure

140: grid structure

230: gate spacer

300: multilayer interconnection structure

310,410: interlayer dielectric layer

320: contact trench

330: metal silicide

350: source/drain contact

370: barrier layer

390: etch stop layer

430,480,570: etching process

450,580: through hole

450A, 550A: top part

450B, 550B: bottom part

500,510,510B,520,670,680: size of

540: selective metal growth process

550: source/drain vias

560,560B,610,700,710,720: distance between two adjacent plates

590,620: deposition process

600: adhesive layer

630: conductive layer

650: planarization process

900: method of producing a composite material

910,920,930,940,950,960,970,980,990: step (ii) of

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. Further, when a value or range of values is described as "about", "approximately", or the like, it includes +/-10% of the stated value, unless otherwise specified. For example, the term "about 5 nm" includes a size range between 4.5nm to 5.5 nm.

Embodiments of the present invention generally relate to semiconductor devices, and more particularly, to field effect transistors such as planar field effect transistors or three-dimensional fin field effect transistors. One embodiment of the present invention relates to forming low resistance source/drain vias as part of the fabrication of semiconductor devices. For example, conventional methods of forming source/drain vias require first forming an adhesive layer in the source/drain vias and then forming source/drain vias in the adhesive layer to fill the vias. This is because the source/drain vias do not adhere strongly to the surrounding material (e.g., dielectric material) on which they are formed if the source/drain vias are deposited directly in the via holes without the use of an adhesion layer. The lack of adhesion may cause the source/drain vias to peel off during subsequent polishing processes. Although the presence of the adhesion layer may reduce the problem of source/drain via peeling, the overall resistance of the source/drain via is substantially increased because the resistance of the adhesion layer is higher than the resistance of the source/drain via material. High resistance is an undesirable phenomenon because it negatively impacts device performance, such as speed.

In order to overcome the above problems, the method for forming the source/drain via according to the embodiments of the present invention does not use an adhesive layer. For example, selective metal growth techniques may be used to form source/drain vias directly over the source/drain contacts, which may provide good adhesion between the source/drain vias and the source/drain contacts. The source/drain vias also have laterally protruding bottoms, which may provide various advantages such as reduced resistance, protection from abrasive corrosion, or other advantages, as described in more detail below.

Fig. 1A and 1B show a three-dimensional perspective view and a top view, respectively, of a portion of an integrated circuit device 90. The integrated circuit device 90 may be an intermediate device in processing an integrated circuit or portion thereof, which may include static random access memory and/or other logic circuitry, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., p-type field effect transistors, n-type field effect transistors, fin-type field effect transistors, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells). Embodiments of the present invention are not limited to any particular number of devices or device regions or any particular device arrangement unless described in a related application. For example, although integrated circuit device 90 is shown as a three-dimensional finfet device, the concepts of the present embodiments may also be applied to planar fet devices.

As shown in fig. 1A, the integrated circuit device 90 includes a substrate 110. The substrate 110 may comprise a single semiconductor element (e.g., silicon, germanium, and/or other suitable materials), a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials), or a semiconductor alloy (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or other suitable materials). The substrate 110 may be a single layer of material of uniform composition. In other embodiments, the substrate 110 may include multiple material layers of similar or different compositions for fabricating integrated circuit devices. In one example, the substrate 110 can be a silicon-on-insulator substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in or on the substrate 110. The doped region may be doped with an n-type dopant, such as phosphorus or arsenic, and/or a p-type dopant, such as boron, depending on design requirements. The doped region may be formed directly on the substrate 110, in a p-well structure, in an n-well structure, in a twin-well structure, or in a raised structure. The doped regions may be formed by implanting dopant atoms, epitaxial growth with in-situ doping, and/or other suitable techniques.

A three-dimensional active region is formed on the substrate 110. The active region is an extended fin structure protruding upward from the substrate 110. As such, the active region may be considered as fin structure 120. The fin structure 120 may be formed by any suitable process, including photolithography and etching. The photolithography process may include forming a photoresist layer on the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask unit (not shown) containing the photoresist. Then, a mask unit is used and is etched and recessed into the substrate 110 to leave the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching, and/or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning process or a multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes that produce a pattern pitch that is smaller than that obtained using a single direct photolithography process. For example, a layer may be formed on a substrate and patterned using a photolithography process. Spacers may be formed along the sides of the patterned layer using a self-aligned process. The layer is then removed and the fin structure 120 is patterned with the remaining spacers or cores.

Integrated circuit device 90 also includes source/drain structure 122 formed on fin structure 120. Source/drain structures 122 may include an epitaxial layer epitaxially grown on fin structure 120.

The integrated circuit device 90 further includes an isolation structure 130 formed on the substrate 110. The isolation structure 130 electrically separates the various components of the integrated circuit device 90. The isolation structure 130 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low-k dielectric material, and/or other suitable materials. In some embodiments, the isolation structure 130 may comprise a shallow trench isolation structure. In one embodiment, the isolation structure 130 may be formed by etching a trench in the substrate 110 during the formation of the fin structure 120. Then, the isolation material is filled into the trench, and a chemical mechanical polishing process is performed. Other isolation structures such as field oxide, local silicon oxide, and/or other suitable structures may also be implemented as the isolation structure 130. In other embodiments, the isolation structure 130 may include a multi-layer structure, such as having one or more thermal oxide liner layers.

Integrated circuit device 90 also includes a gate structure 140 formed on fin structures 120 and joining fin structures 120 from three sides of the channel region of each fin structure 120. The gate structure 140 may be a dummy gate structure (e.g., a gate dielectric layer including oxide and a polysilicon gate), or a high-k dielectric layer and a metal gate structure (formed by replacing the dummy gate structure). Although not shown, the gate structure 140 may include additional material layers such as an interface layer, a cap layer, other suitable layers, or a combination thereof on the fin structure 120.

As shown in fig. 1B, the length direction of the fin structures 120 is along the X direction, and the length direction of the gate structures 140 is along the Y direction (generally perpendicular to the fin structures 120). In many embodiments, the integrated circuit device 90 includes additional structures such as gate spacers along sidewalls of the gate structure 140, a hard mask layer over the gate structure 140, and a variety of other structures. For simplicity, the process steps of one embodiment of the present invention are illustrated using the cross-sectional views of fig. 2-12, wherein the cross-sectional view of the integrated circuit device 90 is along the cross-sectional line AA' shown in fig. 1A and 1B.

As shown in fig. 2, the integrated circuit device 90 includes the substrate 110. The gate structure 140 is formed on the substrate 110 in a Z-direction, which is perpendicular to a horizontal surface defined by the X-direction and the Y-direction. The gate structures 140 are each sandwiched between a source region and a drain region, wherein a channel region is defined in the substrate 110 between the source and drain regions. The gate structure 140 is connected to the channel region, so that current can flow between the source/drain regions during operation. In some embodiments, the gate structures 140 are formed on fin structures (e.g., the fin structures 120 of fig. 1A and 1B) such that the gate structures 140 each wrap around a portion of the fin structure. For example, the gate structure 140 covers the channel region of the fin structure, and is sandwiched between the source region and the drain region of the fin structure.

In some embodiments, the gate structure 140 includes a metal gate stack configured to perform a function required by design requirements. For example, the metal gate stacks may each include a gate dielectric layer and a gate. A gate dielectric layer is on the substrate 110 and a gate is on the gate dielectric layer. In some embodiments, the gate dielectric layer is conformally disposed on the sidewall surfaces and the bottom surface of the integrated circuit device 90 defining the metal gate stack, such that the gate dielectric layer is generally U-shaped and has a substantially uniform thickness. The gate dielectric layer may comprise a dielectric material such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. High dielectric constant dielectric materials are generally considered to be dielectric materials having a high dielectric constant, such as dielectric materials having a dielectric constant greater than that of silicon oxide (e.g., about 3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable compositions, or combinations thereof. In some embodiments, the gate dielectric layer comprises a multi-layered structure, such as an interfacial layer (e.g., silicon oxide) and a high-k dielectric layer (e.g., hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, aluminum oxide, hafnium-aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, other suitable high-k dielectric materials, or combinations thereof).

The gate electrode includes a conductive material. In some embodiments, the gate electrode includes multiple layers, such as one or more cap layers, work function layers, adhesion and/or barrier layers, and/or metal fill (or base) layers. The cap layer comprises a material that prevents and/or eliminates compositional reaction and/or diffusion between the gate dielectric layer and other layers of the gate. In some embodiments, the capping layer comprises a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, or a combination thereof. The work function layer includes a conductive material, such as an n-type work function material and/or a p-type work function material, which may be tuned to have a desired work function (e.g., an n-type work function or a p-type work function). The p-type work function material comprises titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other p-type work function materials, or combinations thereof. The n-type work function material comprises titanium, aluminum, silver, manganese, zirconium, titanium aluminum carbide, tantalum carbonitride, tantalum silicon nitride, tantalum aluminum carbide, titanium aluminum nitride, other n-type work function materials, or combinations thereof. The adhesion layer and/or barrier layer may comprise materials that promote adhesion between adjacent layers, such as a work function layer and a metal fill layer, and/or block and/or reduce diffusion between gate layers, such as a work function layer and a metal fill layer. For example, the adhesion layer and/or barrier layer comprises a metal (such as tungsten, aluminum, tantalum, titanium, nickel, copper, cobalt, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (such as titanium nitride), or combinations thereof. The metal fill layer may comprise a suitable conductive material such as aluminum, tungsten, and/or copper.

The gate structure 140 may be fabricated according to a gate replacement process, which may be a gate first process or a gate last process. For example, the dummy gate stack may be formed first in the gate replacement process and then replaced with the gate structure 140. For example, the dummy gate stack includes an interfacial layer (e.g., comprising silicon oxide) and a dummy gate layer (e.g., comprising polysilicon). The dummy gate is removed to form an opening (e.g., a trench), and the metal gate of the gate structure 140 is then filled into the opening. In some embodiments, the dummy gate stack may be formed before the formation of the interlayer dielectric layer and replaced with the gate structure 140 after the formation of the interlayer dielectric layer.

The gate post-processing and/or gate-first processing may implement a deposition process, a lithography process, an etch process, other suitable processes, or a combination thereof. The deposition process comprises chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, organometallic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, plating, other suitable methods, or combinations thereof. The photolithography process may include coating a photoresist (e.g., spin coating), soft baking, aligning a mask, exposing, post-exposure baking, developing a photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. In other embodiments, other methods such as maskless lithography, e-beam writing, or ion beam writing may assist, implement, or replace the lithography exposure process. The etching process includes a dry etching process, a wet etching process, other etching processes, or a combination thereof.

As shown in fig. 2, the gate spacers 230 may be adjacent to the gate structure 140, such as formed on sidewalls of the gate structure 140 in the Y-direction. The gate spacers 230 may be formed by depositing a dielectric material and patterning the dielectric material. The deposited dielectric material may contain silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, the dielectric layer of the embodiments may comprise silicon and nitrogen, such as a silicon nitride layer. A dielectric layer may be deposited on the substrate 110 and then anisotropically etched to form the gate spacers 230. In some embodiments, the gate spacer 230 may comprise a multi-layer structure such as a first dielectric layer comprising silicon oxide and a second dielectric layer comprising silicon oxide. In some embodiments, the gate spacers 230 may include more than one set of spacers to be adjacent to the gate structure 140, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers. In these embodiments, the plurality of sets of spacers may comprise materials of different etch rates. For example, a first dielectric layer comprising silicon and oxygen may be deposited on the substrate 110, followed by anisotropic etching of the first dielectric layer to form a first set of spacers adjacent to the gate stack. A second dielectric layer comprising silicon and nitrogen may be deposited on the substrate 110 followed by anisotropic etching of the second dielectric layer to form a second set of spacers adjacent to the first set of spacers. An implantation, diffusion, and/or annealing process may be performed before and/or after the formation of the gate spacers 230 to form lightly doped source/drain structures and/or heavily doped source/drain structures (both not shown in fig. 2) in the source/drain regions.

As shown in fig. 2, source/drain structures 122 are formed in the source/drain regions of the substrate 110. In some embodiments, the source/drain structure 122 may be formed using an epitaxial process. For example, a semiconductor material may be epitaxially grown on the substrate 110 to form source/drain structures 122, such as epitaxially grown structures. In the illustrated embodiment, gate structures 140 are sandwiched between respective source/drain structures 122, and respective channel regions are defined between respective epitaxial source/drain structures 122 and in substrate 110 beneath respective gate structures 140. The integrated circuit device 90 may thus be configured to include transistors including the gate structure 140 and the corresponding source/drain structures 122 and channel regions. In some embodiments, the source/drain structure 122 wraps around source/drain regions of a fin structure (e.g., fin structure 120 of fig. 1A and 1B) extending from the substrate 110, such that the transistor is configured as a finfet.

The epitaxial process may implement chemical vapor deposition techniques (e.g., vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, low pressure chemical vapor deposition, and/or plasma assisted chemical vapor deposition), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. The epitaxial process may employ gaseous and/or liquid precursors that interact with the composition of the substrate 110. The source/drain structures 122 may be doped with n-type dopants and/or p-type dopants. In some embodiments, the transistor is configured as an n-type device, and the source/drain structure 122 may be a silicon-containing epitaxial layer or a carbon-and-silicon-containing epitaxial layer (e.g., a silicon phosphide-forming epitaxial layer or a silicon carbon phosphide epitaxial layer) doped with phosphorus, other n-type dopants, or a combination thereof. In some embodiments, the transistor is configured as a p-type device, and the source/drain structure 122 may be a silicon and germanium-containing epitaxial layer (e.g., an epitaxial layer forming silicon germanium boride) doped with boron, other p-type dopants, or a combination thereof. In some embodiments, the source/drain structures 122 comprise materials and/or dopants that achieve a desired tensile stress and/or compressive stress in the channel region. In some embodiments, the source material for the epitaxial process is added as deposited to dope source/drain structures 122. In some embodiments, the deposition process may be followed by an ion implantation process to dope source/drain structures 122. In some embodiments, an annealing process may be performed to activate dopants in the source/drain structure 122 and/or other source/drain regions of the integrated circuit device 90.

Isolation structures (not shown) may also be formed on and/or in the substrate 110 to isolate various regions of the integrated circuit device 90. For example, the isolation structures define and electrically isolate the active device region and/or the passive device region from each other. In some embodiments, isolation structures may be provided to isolate transistors corresponding to the gate structure 140 and the source/drain structure 122 from other transistors, devices, and/or regions of the integrated circuit device 90. The isolation structure comprises an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., silicon, oxygen, nitrogen, carbon, and/or other suitable isolation compositions), or combinations thereof. The isolation structures may include different structures, such as shallow trench isolation structures, deep trench isolation structures, and/or local silicon oxide structures.

In some embodiments, the shallow trench isolation structure may be formed by etching a trench in the substrate 110 (e.g., using a dry etching process and/or a wet etching process), and filling the trench with an insulating material (e.g., using a chemical vapor deposition process or a spin-on-glass process). A chemical mechanical polishing process may be performed to remove excess insulating material and/or planarize the upper surface of the shallow trench isolation structure. In some embodiments, the sti structure may be formed by depositing an insulating material on the substrate 110 after forming the fins, filling the insulating material layer into the gaps (e.g., trenches) between the fins, and then etching back the insulating material layer. In some embodiments, the isolation structure includes a multi-layer structure filling the trench, such as a bulk dielectric layer on a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer comprise materials according to design requirements. For example, a bulk dielectric layer comprising silicon nitride may be located on a liner dielectric layer comprising thermal oxide. In some embodiments, the isolation structure includes a dielectric layer over a doped liner layer (such as borosilicate glass or phosphosilicate glass).

As shown in fig. 2, the multi-layer interconnect structure 300 is located on the substrate 110 in the Z-direction. The multilevel interconnect structure 300 electrically couples various devices (e.g., transistors, resistors, capacitors, and/or inductors) and/or components (e.g., gate structures and/or source/drain structures) of the integrated circuit device 90 together such that the various devices and/or components operate in accordance with design requirements of the integrated circuit device 90. The multilevel interconnect structure 300 includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form a variety of interconnect structures. The conductive layers are configured to form vertical interconnect structures such as contacts and/or vias (to provide vertical connections and/or vertical electrical traces between structures) and/or horizontal interconnect structures such as conductive traces (to provide horizontal electrical traces). The vertical interconnect structure may generally connect horizontal interconnect structures in different levels (or different planes) of the multilevel interconnect structure 300. In operation, the multilevel interconnect structure 300 may route signals (e.g., timing signals, voltage signals, and/or ground signals) between devices and/or components of the integrated circuit device 90 and/or route signals to devices and/or components of the integrated circuit device 90. Although the multilayer interconnect structure 300 shown in the drawings has a given number of dielectric and conductive layers, embodiments of the present invention may have more dielectric and/or conductive layers or fewer dielectric and/or conductive layers in the multilayer interconnect structure 300.

In the stage of fabrication shown in fig. 2, the multilevel interconnect structure 300 includes an interlayer dielectric layer 310 overlying the substrate 110 and the gate structure 140 in the Z-direction and laterally surrounding the gate structure 140 in the X-direction. In some embodiments, the interlayer dielectric layer 310 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from tetraethoxysilane, phosphosilicate glass, borophosphosilicate glass, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include fluorine-doped silicate glasses, carbon-doped silicon oxides, and,(Applied Materials, Santa Clara, Calif.), xerogels, aerogels, amorphous fluorinated carbons, parylene, benzocyclobutene, SiLK (Dow Chemical, Midland, Michigan), polyimides, other low dielectric constant dielectric Materials, or combinations thereof. In some embodiments, the interlayer dielectric layer 310 may comprise a multi-layer structure of multiple dielectric materials. The method for forming the interlayer dielectric layer 310 on the substrate 110 may be a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, other suitable methods, or a combination thereof. In some embodiments, the interlayer dielectric layer 310 is formed by a flowable chemical vapor deposition process that includes depositing a flowable material (e.g., a liquid compound) on the substrate 110 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and/or ultraviolet treatment. After the deposition of the ild layer 310, one or more cmp processes and/or other planarization processes may be performed to form the ild layer 310 with a substantially planar upper surface.

As shown in fig. 3, the contact trenches 320 may be formed using one or more etching processes. One or more etching processes may etch portions of the interlayer dielectric layer 310 over the source/drain structures 122 until the source/drain structures are at least partially exposed. In other words, the contact trenches 320 each extend vertically through the interlayer dielectric layer 310 in the Z-direction.

As shown in fig. 4, a metal suicide 330 may be formed in the contact trench 320 on the exposed upper surface of the source/drain structure 122. In some embodiments, the metal silicide 330 may be formed by depositing a layer of metal material (e.g., titanium or nickel) on the exposed upper surface of the source/drain structure 122 and performing an annealing process to react the deposited metal material with the silicon-containing material of the source/drain structure 122. The reaction between the deposited metal material and the source/drain structures 122 results in the formation of a metal silicide 330. The metal silicide 330 has a lower resistance than other components of the integrated circuit device 90.

Source/drain contacts 350 are formed in the contact trenches 320. For example, a conductive material, such as a metallic material, may be deposited in the contact trench 320, and the deposition method may employ a suitable deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof. In some embodiments, the deposited conductive material may comprise cobalt. In other embodiments, the deposited conductive material may comprise tungsten or ruthenium. The deposited conductive material may completely fill the contact trench 320 and a portion of the conductive material may be deposited on the top surface of the ild layer 310. After removing the portion of the conductive material outside the contact trench 320 (e.g., the portion deposited on the top surface of the interlayer dielectric layer 310), a planarization process, such as a chemical mechanical polishing process, may be performed to make the top surface of the conductive material filled in the contact trench 320 substantially coplanar with the top surface of the interlayer dielectric layer 310. The source/drain contacts 350 may be formed from the remaining portions of the conductive material that fill the contact trenches 320. The metal silicide 330 may serve as a suitable electrical interface between the source/drain contacts 350 and the source/drain structure 122 due to its low resistance. In other embodiments, the metal silicide 330 may be considered part of the source/drain contacts 350 themselves.

In some embodiments, as illustrated in fig. 4, a barrier layer 370 may be formed between the source/drain contacts 350 and the interlayer dielectric layer 310. For example, a barrier layer 370 (which includes promoting adhesion between adjacent layers or reducing diffusion between adjacent layers) may be formed on the sidewalls of the interlayer dielectric layer 310 (such as the sidewalls of the contact trench 320), followed by the formation of source/drain contacts 350 on the barrier layer 370. In some embodiments, barrier layer 370 may comprise tungsten, aluminum, tantalum, titanium, nickel, copper, cobalt, or metal oxides or metal nitrides thereof.

As shown in fig. 5, an etch stop layer 390 may be formed in the Z-direction on the interlayer dielectric layer 310 and the source/drain contacts 350, and an interlayer dielectric layer 410 may be formed in the Z-direction on the etch stop layer 390. The etch stop layer 390 and the ild layer 410 may also be considered part of the multilevel interconnect structure 300. The etch stop layer 390 and the interlayer dielectric layer 410 may be formed by a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metal organic chemical vapor deposition, remote plasma chemical vapor deposition, plasma assisted chemical vapor deposition, low pressure chemical vapor deposition, atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition, or a combination thereof. The material composition of the interlayer dielectric layer 410 may be substantially similar to the material composition of the interlayer dielectric layer 310.

The material composition of the etch stop layer 390 is set to be different from the material composition of the interlayer dielectric layers 310 and 410, which facilitates reaching an etch selectivity between the etch stop layer 390 and the interlayer dielectric layer 310 or 410 during one or more etching processes. For example, the etch stop layer 390 may be selectively etched with respect to the interlayer dielectric layers 310 and 410 (in other words, the interlayer dielectric layers 310 and 410 may be etched without etching or with minimal etching), and vice versa. In various embodiments, the etch stop layer 390 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, other suitable dielectric materials (such as silicon, oxygen, nitrogen, carbon, and/or other suitable isolating components), or combinations thereof, as long as the material composition of the etch stop layer 390 is different from the material composition of the interlayer dielectric layers 310 and 410. It is understood that a planarization process, such as a chemical mechanical polishing process, may be performed to planarize the upper surface of the etch stop layer 390 before the formation of the interlayer dielectric layer 410, and another planarization process may be performed to planarize the upper surface of the interlayer dielectric layer 410 after the formation of the interlayer dielectric layer 410.

As shown in fig. 6, an etch process 430 is performed on the integrated circuit device 90 to etch the top 450A of the via 450 into the ild layer 410. The etching process 430 may include a dry etching process of some embodiments, or a wet etching process of other embodiments. As described above, the etch process 430 may be configured to have etch selectivity between the interlayer dielectric layer 410 and the etch stop layer 390 due to the difference in material composition between the interlayer dielectric layer 410 and the etch stop layer 390. In other words, the etch process 430 etches away the interlayer dielectric layer 410 at a substantially higher rate than the etch stop layer 390. As such, the etching process 430 may stop at the etch stop layer 390, such as when the upper surface of the etch stop layer 390 is reached. Notably, the via holes 450 are aligned in the X-direction with the source/drain contacts 350. In subsequent processing, conductive material is filled into the via 450 to form source/drain vias, which provide electrical connection to the source/drain contacts 350.

As shown in fig. 7, the integrated circuit device 90 is subjected to an etch process 480 to etch the bottom 450B of the via 450 into the etch stop layer 390. The etch process 480 may be considered a process through the etch stop layer since it extends vertically in the Z-direction from the interlayer dielectric layer 410 down through the hole 450 into the etch stop layer 390. The etch process 480 is also configured to have sufficient etch selectivity between the interlayer dielectric layer 410 or 310 and the etch stop layer 390 so that the etch stop layer 390 may be etched away without substantially affecting the interlayer dielectric layer 410 or 310. In other words, the etch stop layer 390 has an etch rate substantially greater (e.g., more than ten times greater) than the etch rate of the interlayer dielectric layer 410 or 310. Similarly, the etch process 480 is also configured to have sufficient etch selectivity between the source/drain contacts 350 and the etch stop layer 390 so that the etch stop layer 390 may be etched away without substantially affecting the source/drain contacts 350.

As shown in fig. 7, one of the unique physical characteristics of the present embodiment is that the bottom 450B of the through hole 450 may protrude laterally in the X-direction. In other words, rather than retaining the tapered profile of the top 450A, the bottom 450B projects laterally further out into the etch stop layer 390, making the bottom 450B substantially wider in the X-direction than the top 450A and wider in the X-direction than the source/drain contacts 350 (although not necessarily wider in the Y-direction than the source/drain contacts 350).

For example, the top 450A may have a maximum lateral dimension 500 in the X-direction (such as at its widest opening), the bottom 450B may have a maximum lateral dimension 510 in the X-direction, and the source/drain contacts 350 may have a maximum lateral dimension 520 in the X-direction. For clarity of the drawing (and in view of fig. 7), the maximum lateral dimension 520 for the source/drain contacts 350 is indicated for the source/drain contacts 350 to the right of the via holes 450, rather than for the source/drain contacts 350 directly beneath the via holes 450, although it is understood that the two source/drain contacts 350 may have substantially similar dimensions. In any case, the etch process 480 causes the maximum lateral dimension 510 of the bottom 450B of the via 450 to be substantially greater than the maximum lateral dimension 500 of the top 450A of the via 450, and the maximum lateral dimension 510 is also substantially greater than the maximum lateral dimension 520 of the source/drain contact 350 in the X-direction.

In some embodiments, the process time of the etch process 480 may be set to achieve the lateral protrusion of the bottom 450B of the via 450. For example, after the etch process 480 is performed for a time X, the via hole 450 may be allowed to extend vertically through the etch stop layer 390 without causing any lateral protrusion. Therefore, in order to achieve the lateral protrusion, the etching process 480 is performed substantially beyond the time X. The additional etch time etches away the additional material of the etch stop layer 390, thereby laterally expanding the bottom 450B.

At the same time, the additional etch time does not affect (or at least minimally affects) the interlayer dielectric layer 410 or 310 and the source/drain contacts 350 due to the etch selectivity between the etch stop layer 390 and the interlayer dielectric layer 410 or 310 and the source/drain contacts 350. In some embodiments, the etching process 480 is performed using an etching gas mixture of methane fluoride, carbon tetrafluoride, and hydrogen, wherein a ratio of the methane fluoride to the carbon tetrafluoride is about 1:3 to about 3:1, a ratio of the carbon tetrafluoride to the hydrogen is about 1:50 to about 3:40, and a time of the etching process is between 20 seconds and 60 seconds. As described above, the etching process time is not randomly selected, but is specifically set to ensure that the bottom 450B of the via hole 450 can achieve a laterally protruding profile.

In other embodiments, the etch process 480 may be a two-step process, wherein a first step may vertically etch through the etch stop layer 390 and a second step may laterally etch the etch stop layer 390. In some embodiments, the two steps may be performed with different etchants and/or different etching conditions.

This profile has advantages regardless of how the lateral convex profile for the bottom 450B of the through hole 450 is achieved. One of the advantages is a reduction in source/drain via resistance formed in the via hole 450, since lateral protrusion can translate into a large via size or large interface area between the via and the source/drain contact 350. Reducing the resistance may speed up the integrated circuit device 90. Another advantage is the laterally protruding profile so that subsequently formed source/drain vias can avoid contamination of underlying source/drain contacts 350 from chemicals used in subsequent fabrication processes. For example, if the source/drain contact 350 is exposed to a slurry used in a subsequent chemical mechanical polishing process, the slurry will attack the source/drain contact 350. The wide bottom of the source/drain vias here may act as a barrier that is effectively resistant to chemicals, helping to avoid damaging the source/drain contacts 350.

As shown in fig. 8, a selective metal growth process 540 is performed on the integrated circuit device 90 to form source/drain vias 550 in the via holes 450. In some embodiments, source/drain vias 550 have a tungsten composition. In other embodiments, the source/drain vias 550 may comprise ruthenium or cobalt. In some embodiments, the material composition of the source/drain vias 550 is different from the material composition of the source/drain contacts 350, such that the source/drain vias 550 may act as a barrier against chemicals (e.g., cmp slurries) that may attack the source/drain contacts 350.

In contrast to other metal deposition processes that deposit metal on surfaces of various materials, including dielectric materials, the selective metal growth process 540 deposits metal material on the upper surface (e.g., metal surface) of the source/drain contact 350 exposed by the via 450, but does not deposit metal material on the exposed surface of the interlayer dielectric layer 410 or 310 and the exposed surface of the etch stop layer 390. Thus, source/drain vias 550 are formed in a bottom-up manner, with bottom portions 550B formed first over source/drain contacts 350 and top portions 550A formed next over bottom portions 550B. In fact, the growth of the source/drain vias 550 directly on the source/drain contacts 350 may result in good adhesion between the two, making the source/drain vias 550 difficult to peel off during subsequent polishing processes.

In the above manner, the method of forming the source/drain via 550 does not use an adhesive layer and is different from the conventional process. The adhesive-free layer described herein means that the side surface of the bottom 550B of the source/drain via 550 is in direct physical contact with the side surface of the etch stop layer 390, and the top 550A of the source/drain via 550 is in direct physical contact with the side surface of the interlayer dielectric layer 410. In contrast, conventional fabrication processes implement adhesion layers between the source/drain vias 550 and the interlayer dielectric layer 410 (and the etch stop layer 390). The adhesion layer used in the prior art may add additional resistance, as described above. The embodiments of the present invention may further reduce the resistance of the source/drain via 550 by eliminating the adhesion layer in the method of forming the source/drain via 550, thereby improving the device performance such as speed.

In some embodiments, the selective metal growth process 540 may employ a selective chemical vapor deposition technique. For example, using tungsten hexafluoride or tungsten pentachloride as the precursor gas, polycrystalline tungsten may optionally be deposited on the exposed upper surfaces of the source/drain contacts 350 in the via holes 450. The precursor gas may also be mixed with hydrogen gas in a proportion of about 0.1% to about 1.5%. The pressure of the selective chemical vapor deposition technique may be between about 1Torr and about 50 Torr. The temperature of the selective chemical vapor deposition technique may be between about 200 ℃ to about 400 ℃. These process parameters are not randomly selected but are carefully set to ensure that the metal material (e.g., tungsten) of the source/drain vias 550 can successfully grow on the source/drain contacts 350 with sufficient adhesion to the source/drain contacts 350.

As described above with reference to fig. 8, one of the unique physical characteristics of the integrated circuit device 90 is that the source/drain vias 550 have laterally protruding bottoms 550B. For example, the bottom portion 550B projects laterally outward from the bottom of the sidewall of the top portion 550A by a distance 560, wherein the top portion 550A is connected to the bottom portion 550B. In some embodiments, the ratio between the distance 560 and the dimension 500 of the top is about 1:6 to about 1: 10.

As shown in fig. 9, the integrated circuit device 90 is subjected to one or more etching processes 570 to form a via 580 on one of the gate structures 140 adjacent to the source/drain contact 350. The via hole 580 extends vertically through the ild layer 410, the etch stop layer 390, and the ild layer 310. The via 580 may also extend partially into the gate structure 140. This is because the gate structure 140 may include one or more dielectric hard mask layers over the gate. To simplify the drawing, one or more dielectric hard mask layers are not separately shown from the gate. The via 580 is etched until the upper surface of the gate is exposed, meaning that the via 580 extends through one or more dielectric hard mask layers.

As shown in fig. 10, a deposition process 590 is performed on the integrated circuit device 90 to form an adhesive layer 600. Adhesion layer 600 is formed on the bottom surface and sidewalls of via hole 580, and on the top surfaces of interlayer dielectric layer 410 and source/drain via 550. In some embodiments, adhesion layer 600 comprises titanium, titanium nitride, or a combination thereof. The adhesive layer 600 may be used to improve adhesion. The adhesion layer 600 may also reduce unwanted native oxide formation and/or accumulation on the upper surface of the gate structure 140.

As shown in fig. 11, a deposition process 620 is performed on the integrated circuit device 90 to form a conductive layer 630 on the adhesive layer 600. In some embodiments, conductive layer 630 comprises tungsten, ruthenium, cobalt, or combinations thereof. The conductive layer 630 completely fills the via 580.

As shown in fig. 12, the integrated circuit device 90 is subjected to a planarization process 650. For example, the planarization process 650 may include a chemical mechanical polishing process that employs an abrasive and/or corrosive chemical (as a slurry for chemical mechanical polishing) in combination with a polishing pad to polish the top surface of various layers of the integrated circuit device 90. The planarization process 650 is performed until the portions of the conductive layer 630 and the adhesive layer 600 outside the through hole 580 are removed. In other words, the planarization process 650 may be performed until the top surfaces of the interlayer dielectric layer 410 and the source/drain vias 550 are exposed. These upper surfaces are coplanar with the upper surfaces of the remaining portions of the conductive layer 630. The remaining portion of the conductive layer 630 is electrically connected to the gate structure 140 thereunder, thereby forming a gate via. Conductive layer 630 can then be considered a gate via.

As described above, the polishing slurry used in the planarization process 650 may contain polishing and/or etching chemistries. If the slurry physically contacts the source/drain contacts 350, the slurry can attack the source/drain contacts 350, particularly source/drain contacts 350 that use cobalt, since the etchant chemistry of the slurry is more likely to damage the cobalt. The wider bottom 550B of the source/drain via 550 here may cover a greater amount of the surface area of the source/drain contact 350, thereby acting as a barrier against the slurry. In many embodiments, the source/drain vias 550 are implemented using tungsten, which is less sensitive to the abrasive's etching chemistry than cobalt (e.g., the cobalt used to implement the source/drain contacts 350). As such, the unique design of the source/drain via 550 herein reduces the possibility of damage to the source/drain contact 350 by the slurry of the planarization process 650, which is one of the advantages of the via design of the present invention.

Another advantage of the source/drain vias 550 herein is reduced resistance. As described above, by laterally protruding bottom 550B (whose dimension 510 is greater than dimension 500 of top 550A), there is a large interface area between source/drain vias 550 and source/drain contacts 350. Large interfaces cause a drop in resistance. Additionally, eliminating the adhesion layer also reduces the overall resistance, since the resistance of the adhesion layer material is greater than the material resistance of the source/drain vias 550.

Another advantage is that the selective growth process 540 is used to grow source/drain vias 550 over the source/drain contacts 350 (as described above with reference to fig. 8), resulting in a strong adhesion between the source/drain vias 550 and the source/drain contacts 350. Due to this strong adhesion, the polishing step of the planarization process 650 is less likely to peel off the source/drain vias 550. In addition, the interlevel dielectric layer 410 may pin the laterally protruding bottom 550B, making the source/drain vias 550 more difficult to exfoliate.

Another advantage of the source/drain vias 550 of embodiments of the present invention relates to a more gradual transition, as described below with respect to fig. 13. In this regard, fig. 3 is also a partial cross-sectional view of a portion of the integrated circuit device 90, except that it is along the YZ plane instead of the XZ plane shown in fig. 2-12. In other words, fig. 2 to 12 show the X-cut plane, and fig. 13 shows the Y-cut plane.

As shown in fig. 13, source/drain vias 550 are still formed over the source/drain contacts 350, as described above. However, the lateral dimension of the source/drain contact 350 in the Y-direction is much greater than the lateral dimension in the X-direction. For example, the maximum lateral dimension 670 of the source/drain contact 350 in the Y-direction is substantially greater than the maximum dimension 520 in the X-direction (see fig. 7). At the same time, the maximum lateral dimension 680 (shown in fig. 13) of the source/drain vias 550 in the Y-direction is less than dimension 670. It is noted that the maximum dimension 680 may be the dimension of the top 550A or the dimension of the bottom 550B. Although dimension 680 is smaller than dimension 670, it is still a more gradual dimension. In contrast, the bottom surface of the conventional source/drain via is much smaller than the top surface of the source/drain contact in the Y-direction because the conventional source/drain via lacks a laterally protruding bottom profile. As a result, the conventional scheme causes a large change when the wider source/drain contacts are changed to very narrow source/drain vias. Large dimensional variations are undesirable because they can lead to defects or other fabrication related difficulties. Since the bottom 550B of the source/drain via 550 is here much wider than the existing source/drain via, there is a gradual change from the source/drain contact 350 to the source/drain via 550 to reduce possible defects or fabrication problems.

In the above embodiments, the source/drain vias 550 and gate vias, such as conductive layer 630, may be at least partially laterally aligned. In other words, at least a portion of source/drain via 550 is in the same XZ profile as at least a portion of a gate via, such as conductive layer 630. However, embodiments of the invention are not limited thereto. In other embodiments, the positions of the source/drain vias 550 and gate vias, such as the conductive layer 630, may be offset in both the X-direction and the Y-direction. This embodiment is shown in fig. 14 and 15, where fig. 14 is a partial cross-sectional view along the X-Z plane (similar to fig. 2-12), and fig. 15 is a partial top view of another embodiment of an integrated circuit device 90.

As shown in fig. 14 and 15, the source/drain vias 550 are formed using the same fabrication process described above. However, source/drain vias 550 and gate vias, such as conductive layer 630, are offset or misaligned with respect to each other in both the X-direction and the Y-direction. As shown in fig. 14, due to the offset, gate vias such as conductive layer 630 may not be directly visible because the cross-section along the X-Z plane cuts into source/drain vias 550 but not into gate vias such as conductive layer 630. However, to simplify the drawing, the outline of a gate via such as the conductive layer 630 in fig. 14 may be represented by a dotted line. If the cross-sectional profile is at a different point along the X-Z plane, the gate via is visible as conductive layer 630 but source/drain via 550 is not.

As shown in fig. 15, the top view in some embodiments may be along a plane that intersects the top 550A of source/drain via 550, or the top view in some other embodiments may be along a plane that intersects the bottom 550B of source/drain via 550. In other words, the source/drain vias 550 shown in fig. 15 correspond to the top 550A in some embodiments, or the bottom 550B in other embodiments.

As shown in fig. 15, source/drain vias 550 and gate vias, such as conductive layer 630, are spaced apart from each other by a distance 700 in the X-direction. Source/drain vias 550 and gate vias, such as conductive layer 630, are separated from each other by a distance 710 in the Y-direction. Source/drain vias 550 and gate vias, such as conductive layer 630, may be diagonally separated by a distance 720, which may be the open root of the sum of the square of distance 700 and the square of distance 610. In some embodiments, distances 700 and 710 may each be between about two times the critical dimension and about three times the critical dimension, and distance 720 may be between about 2.8 times the critical dimension and about 4.2 times the critical dimension. For example, the critical dimension may be considered as a minimum dimension for the structure of the integrated circuit device, such as the width of the fin structure 120 described above. In another example, the critical dimension may be considered as the width of the gate structure 140. In yet another example, the critical dimension may be considered as the spacing between adjacent metal lines in the metal layer.

Embodiments of the present invention can minimize the risk of electrical bridging (e.g., electrical shorts) between source/drain vias 550 and gate vias, such as conductive layer 630, by placing the X-direction and Y-direction offsets (and thus placing the diagonal offsets) within these ranges. This arrangement is particularly advantageous because source/drain vias 550 project laterally toward the gate vias, such as conductive layer 630. Since source/drain vias 550 are offset not only in the X-direction but also in the Y-direction, the lateral protrusion of source/drain vias 550 still has no significant risk of externally contacting gate vias such as conductive layer 630.

Fig. 16 is a cross-sectional view of an integrated circuit device 90 in another embodiment. For clarity and consistent illustration, components shown in the embodiment of fig. 2-14 and the embodiment of fig. 16 will be identified with the same reference numerals. One of the differences between the embodiment of fig. 2-14 and the embodiment of fig. 16 is the lateral protrusion of the bottom 550B of the source/drain via 550. In fig. 16, the bottom 550B of the source/drain via 550 still projects laterally outward, but significantly less than the projection distance shown in the embodiments of fig. 2-14. For example, the laterally protruding distance 560B may correspond to the distance between the sidewall of the bottom 550B and the sidewall bottom of the top 550A. In some embodiments, the ratio of distance 560B to dimension 500 is between about 1:13 and about 1:17, which is less than the above-described ratio of distance 560 to dimension 500 associated with fig. 8. Further, the bottom 550B has a dimension 510B in the embodiment of FIG. 16 that is less than the dimension 510 described above in connection with FIG. 12. In some embodiments, dimension 510B may also be smaller than dimension 500 of top 550A. In some embodiments, the ratio of dimension 510B to dimension 500 is between about 1: 1to about 1: 1.1.

It should also be understood that the projections of the bottom 550B may not have the sharp edges shown in fig. 16 (or in the embodiments of fig. 12-14). Conversely, the projections may be more gradual and more rounded. For example, the sidewalls of the bottom 550B may have some rounding or curvature, rather than being linear. Furthermore, the top 550A and bottom 550B may not form an acute angle, while the transition between the top 550A and bottom 550B may be smoother than that shown in fig. 16.

Fig. 17 is a flow chart of a method 900 of fabricating a semiconductor device in accordance with another embodiment of the present invention. The method 900 includes a step 910 of forming source/drain and gate structures on a substrate.

The method 900 includes a step 920 of forming a first interlayer dielectric layer on the source/drain and gate structures.

The method 900 includes a step 930 of forming source/drain contacts on the source/drains. The source/drain contacts extend vertically through the first interlevel dielectric layer.

The method 900 includes a step 940 of forming an etch stop layer on the first interlayer dielectric layer.

The method 900 includes a step 950 of forming a second interlayer dielectric layer on the etch stop layer.

The method 900 includes step 960, in which the second ild and the etch stop layer are etched to form a first via exposing the source/drain contact.

Method 900 includes step 970, which forms a source/drain via in the first via hole. The source/drain via is in direct physical contact with the source/drain contact, the etch stop layer, and the second interlayer dielectric layer.

The method 900 includes step 980, after forming the source/drain via, etching the second ild, the etch stop layer, and the first ild to form a second via exposing the gate structure.

Method 900 includes a step 990 of forming a gate via in the second via hole.

In some embodiments, the second interlayer dielectric layer and the etch stop layer are etched using one or more etch processes, wherein the etch stop layer has an etch rate greater than an etch rate of the second interlayer dielectric layer.

In some embodiments, the source/drain vias are formed using a selective metal growth process.

In some embodiments, the first and second vias are offset from each other in both a first and second lateral direction (perpendicular to the first lateral direction).

It is understood that additional steps may be performed before, during, or after steps 910 through 990. For example, after forming the second via hole but before forming the gate via, the method 900 may form an adhesive layer on the sidewall surface of the second via hole and the gate structure, wherein the gate via is formed on the adhesive layer. As another example, after forming the source/drain vias, the method 900 may perform one or more semiconductor fabrication processes that employ one or more chemistries that are corrosive in nature, wherein the material composition of the source/drain vias is more resistant to the one or more chemistries than the material composition of the source/drain contacts. Additional steps may include processes for forming additional interconnect structures, packaging, or testing.

In summary, the embodiments of the present invention relate to a method for forming source/drain vias without using an adhesive layer. For example, selective metal growth techniques may be employed to grow source/drain vias over the source/drain contacts. The resulting source/drain vias may be in direct physical contact with the sidewalls of adjacent dielectric layers, such as the interlevel dielectric layer and the etch stop layer. Embodiments of the present invention also provide source/drain via profiles (e.g., lateral etch stop layers) to the bottom of the lateral protrusion.

In light of the foregoing, embodiments of the present invention provide further advantages over conventional source/drain vias. It is to be understood, however, that not necessarily all advantages may be described herein, that different embodiments may provide different advantages, and that no particular advantage is necessarily required of any embodiment. One advantage of embodiments of the present invention is that the resistance of the source/drain vias is reduced. Conventional source/drain vias require an adhesion layer to ensure adequate adhesion between adjacent materials, otherwise the source/drain vias may peel off during subsequent cmp processes. However, the adhesion layer has a high electrical resistance, which negatively affects device performance. The selective metal growth process herein eliminates the need for an adhesion layer to reduce the resistance of the source/drain vias. The selective metal growth process also ensures sufficient adhesion between the source/drain via and the underlying source/drain contact to prevent peeling of the source/drain via during the cmp process. The wide bottom profile of the source/drain vias tends to result in a larger surface area, which also reduces resistance. Another advantage is that the larger bottom dimension of the source/drain via facilitates a more gradual transition between the source/drain contact and the source/drain via, which may reduce potential problems and/or defects associated with fabrication. Yet another advantage is that the source/drain vias and nearby gate vias may be disposed offset from each other in both the X and Y lateral directions. This also reduces the likelihood of electrical bridging (e.g., electrical shorts) between the source/drain vias and adjacent gate vias. Other advantages may include compatibility with existing fabrication processes, ease of implementation, and reduced cost of implementation.

The advanced lithography processes, methods, and materials described above may be used in a variety of applications, including finfet transistors. For example, the fins may be patterned to create closer spacing between structures as appropriate for the above. In addition, the spacers (also referred to as cores) used to form the fins of the finfet may be processed in accordance with the above.

An embodiment of the present invention relates to a semiconductor device. The semiconductor device includes: a source/drain on the substrate; a source/drain contact located on the source/drain; and a first via over the source/drain contact, wherein the first via has a laterally protruding bottom and a top over the laterally protruding bottom.

In some embodiments, the semiconductor device further includes a gate structure on the substrate; and a second via on the gate structure, wherein the first via and the second via have substantially coplanar upper surfaces.

In some embodiments, the first and second vias are offset from each other in both the X-direction and the Y-direction of the top view.

In some embodiments, the semiconductor device further includes an adhesive layer on a side surface and a lower surface of the second via.

In some embodiments, the adhesion layer comprises titanium or titanium nitride.

In some embodiments, a first maximum lateral dimension of the bottom portion of the lateral projection is greater than a second maximum lateral dimension of the top portion.

In some embodiments, the semiconductor device further comprises: a first interlayer dielectric layer on the substrate, wherein the first interlayer dielectric layer at least partially laterally surrounds the source/drain; an etch stop layer on the first interlayer dielectric layer; and a second interlayer dielectric layer on the etch stop layer, wherein a side surface of the first via directly physically contacts the etch stop layer and the second interlayer dielectric layer.

In some embodiments, the side surfaces of the laterally protruding bottom are in direct physical contact with the etch stop layer; and a side surface of the top portion directly physically contacts the second interlayer dielectric layer.

In some embodiments, the source/drain contacts and the first vias have different material compositions.

In some embodiments, the uppermost surface of the source/drain contact is wider than the lowermost surface of the first via.

An embodiment of the present invention relates to a semiconductor device. The semiconductor device includes: a source/drain on the substrate; a gate structure on the substrate; a first interlayer dielectric layer on the gate structure; an etch stop layer on the first interlayer dielectric layer; a second interlayer dielectric layer on the etch stop layer; a gate via over the gate structure, wherein the gate via extends vertically through the first interlayer dielectric, the etch stop layer, and the second interlayer dielectric; an adhesion layer between the gate via and the first interlayer dielectric layer, the etch stop layer, and the second interlayer dielectric layer; a source/drain contact on the source/drain, wherein the source/drain contact extends vertically through the first interlayer dielectric layer; and a source/drain via over the source/drain contact, wherein the source/drain via extends vertically through the second interlayer dielectric layer and the etch stop layer, and wherein a sidewall of the source/drain via is in direct physical contact with a sidewall of the etch stop layer and the second interlayer dielectric layer.

In some embodiments, the bottom sidewalls of the source/drain vias are in direct physical contact with the sidewalls of the etch stop layer; the top side wall of the source/drain through hole is directly in physical contact with the side wall of the second interlayer dielectric layer; and the bottom is substantially wider than the top.

In some embodiments, the source/drain vias and the gate via are offset from each other in both a first horizontal direction and a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

In some embodiments, the adhesion layer comprises titanium or titanium nitride.

Yet another embodiment of the present invention relates to a method of forming a semiconductor device. The method comprises the following steps: forming a source/drain and gate structure on the substrate; forming a first interlayer dielectric layer on the source/drain and gate structures; forming source/drain contacts on the source/drain, wherein the source/drain contacts extend vertically through the first interlayer dielectric layer; forming an etch stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etch stop layer; etching the second interlayer dielectric layer and the etch stop layer to form a first via hole exposing the source/drain contact; forming a source/drain via in the first via, wherein the source/drain via is in direct physical contact with the source/drain contact, the etch stop layer, and the second interlayer dielectric layer; after the source/drain through hole is formed, etching the second interlayer dielectric layer, the etching stop layer and the first interlayer dielectric layer to form a second through hole exposing the grid structure; and forming a gate through hole in the second through hole.

In some embodiments, the step of etching the second interlayer dielectric layer and the etch stop layer uses one or more etching processes, wherein the etch stop layer has an etch rate greater than an etch rate of the second interlayer dielectric layer.

In some embodiments, the method further comprises forming an adhesive layer on sidewalls of the second via hole and the gate structure after forming the second via hole and before forming the gate via hole, wherein the gate via hole is formed on the adhesive layer.

In some embodiments, the method further comprises performing one or more semiconductor fabrication processes after forming the source/drain vias using one or more chemicals having an etching characteristic, wherein the material composition of the source/drain vias is more resistant to the one or more chemicals than the material composition of the source/drain contacts.

In some embodiments, the step of forming the source/drain vias uses a selective metal growth process.

In some embodiments, the first through hole and the second through hole are offset from each other in both the first lateral direction and the second lateral direction, and the second lateral direction is perpendicular to the first lateral direction.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.