阅读说明：本技术 半导体装置及半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 村田大辅 于 2020-09-25 设计创作，主要内容包括：本发明涉及半导体装置及半导体装置的制造方法,其目的在于得到能够抑制键合导线的损伤的半导体装置及半导体装置的制造方法。本发明涉及的半导体装置具有：基座板；第1半导体芯片,其设置于该基座板之上；键合导线,其与该第1半导体芯片在第1接合部处接合,键合导线在比该第1接合部更靠上方处具有弯曲部；第1封装部件,其从该基座板的上表面起设置至比该第1接合部高且比该弯曲部低的高度,覆盖该第1接合部；以及第2封装部件,其设置于该第1封装部件之上,覆盖该弯曲部,第2封装部件与该第1封装部件相比弹性模量低。(The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and aims to obtain a semiconductor device and a method for manufacturing the semiconductor device, which can restrain damage of a bonding wire. The semiconductor device according to the present invention includes: a base plate; a 1 st semiconductor chip disposed on the base plate; a bonding wire bonded to the 1 st semiconductor chip at a 1 st bonding portion, the bonding wire having a bent portion above the 1 st bonding portion; a 1 st package member provided at a height higher than the 1 st bonding portion and lower than the bent portion from an upper surface of the base plate, and covering the 1 st bonding portion; and a 2 nd package member disposed on the 1 st package member to cover the bent portion, the 2 nd package member having a lower elastic modulus than the 1 st package member.)

1. A semiconductor device is characterized by comprising:

a base plate;

a 1 st semiconductor chip disposed on the base plate;

a bonding wire bonded to the 1 st semiconductor chip at a 1 st bonding portion, the bonding wire having a bent portion above the 1 st bonding portion;

a 1 st package member provided at a height higher than the 1 st bonding portion and lower than the bent portion from an upper surface of the base plate, and covering the 1 st bonding portion; and

and a 2 nd package member that is provided on the 1 st package member and covers the bent portion, the 2 nd package member having a lower elastic modulus than the 1 st package member.

2. The semiconductor device according to claim 1,

having a 1 st circuit pattern disposed on the base plate,

the 1 st semiconductor chip is bonded to the 1 st circuit pattern by a bonding material,

the 1 st encapsulation part covers the bonding material.

3. The semiconductor device according to claim 1 or 2,

having a 2 nd circuit pattern disposed on the base plate,

the bonding wire is bonded to the 2 nd circuit pattern at a 2 nd bonding portion,

the 1 st encapsulating member covers the 2 nd bonding portion.

4. The semiconductor device according to any one of claims 1 to 3,

the 1 st bonding portion is provided on an upper surface of the 1 st semiconductor chip,

an upper surface of the 1 st package component is disposed within a range of a wire diameter of the bonding wire from the upper surface of the 1 st semiconductor chip.

5. The semiconductor device according to any one of claims 1 to 4,

having a housing surrounding said base plate,

the housing has a recess having an open face at the level of the upper surface of the 1 st enclosure part,

the 1 st encapsulation part fills the recess.

6. The semiconductor device according to any one of claims 1 to 5,

has a 1 st bump arranged on the base plate,

the 1 st semiconductor chip is disposed over the 1 st bump.

7. The semiconductor device according to claim 6, comprising:

a 2 nd bump disposed on the base plate and having a height lower than that of the 1 st bump; and

a 2 nd semiconductor chip disposed over the 2 nd bump, thicker than the 1 st semiconductor chip,

the height of the upper surface of the 1 st semiconductor chip is consistent with that of the upper surface of the 2 nd semiconductor chip.

8. The semiconductor device according to claim 2, comprising:

a 2 nd circuit pattern which is provided on the base plate and is thinner than the 1 st circuit pattern; and

a 2 nd semiconductor chip disposed over the 2 nd circuit pattern, thicker than the 1 st semiconductor chip,

the height of the upper surface of the 1 st semiconductor chip is consistent with that of the upper surface of the 2 nd semiconductor chip.

9. The semiconductor device according to any one of claims 1 to 8,

the 1 st semiconductor chip is formed of a wide bandgap semiconductor.

10. The semiconductor device according to claim 9,

the wide band gap semiconductor is silicon carbide, gallium nitride based material or diamond.

11. A method for manufacturing a semiconductor device, characterized in that,

a semiconductor chip is disposed over the base plate,

bonding the semiconductor chip to a bonding wire where a bent portion is formed above a bonding portion with the semiconductor chip,

sealing the substrate with a 1 st sealing member from the upper surface of the base plate to a height higher than the bonding portion and lower than the bent portion, the bonding portion being covered with the 1 st sealing member,

the upper surface of the 1 st sealing member is sealed by a 2 nd sealing member having a lower elastic modulus than the 1 st sealing member, and the bent portion is covered by the 2 nd sealing member.

Technical Field

The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background

Patent document 1 discloses a power semiconductor device in which cracks are not easily generated in a sealing resin. The power semiconductor device includes: a semiconductor element substrate on which a surface electrode pattern is formed; and a power semiconductor element fixed to the surface electrode pattern via a bonding material. A partition wall is provided on the surface electrode pattern so as to surround the power semiconductor element. The inside of the partition is filled with the 1 st encapsulating resin covering the power semiconductor element and the surface electrode pattern in the partition. The partition wall, the 1 st encapsulating resin, and the semiconductor element substrate exposed to the outside from the partition wall are covered with the 2 nd encapsulating resin. The 2 nd encapsulating resin has a smaller elastic modulus than the 1 st encapsulating resin.

Patent document 1: international publication No. 2013/111276

In patent document 1, the bonding wire inside the partition wall is covered with a high elastic modulus potting material. In this case, thermal stress to the loop portion of the bonding wire increases, and there is a possibility that a crack may occur in the loop portion.

Disclosure of Invention

The present disclosure has been made to solve the above problems, and an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device, in which damage to a bonding wire can be suppressed.

The semiconductor device according to the present disclosure includes: a base plate; a 1 st semiconductor chip disposed on the base plate; a bonding wire bonded to the 1 st semiconductor chip at a 1 st bonding portion, the bonding wire having a bent portion above the 1 st bonding portion; a 1 st package member provided at a height higher than the 1 st bonding portion and lower than the bent portion from an upper surface of the base plate, and covering the 1 st bonding portion; and a 2 nd package member disposed on the 1 st package member to cover the bent portion, the 2 nd package member having a lower elastic modulus than the 1 st package member.

A method of manufacturing a semiconductor device according to the present disclosure includes providing a semiconductor chip on a base plate, bonding the semiconductor chip to a bonding wire, forming a bent portion on the bonding wire above a bonding portion with the semiconductor chip, encapsulating the semiconductor chip with a 1 st encapsulating member from an upper surface of the base plate to a height higher than the bonding portion and lower than the bent portion, covering the bonding portion with the 1 st encapsulating member, encapsulating an upper surface of the 1 st encapsulating member with a 2 nd encapsulating member having a lower elastic modulus than the 1 st encapsulating member, and covering the bent portion with the 2 nd encapsulating member.

ADVANTAGEOUS EFFECTS OF INVENTION

In the semiconductor device and the method of manufacturing the semiconductor device according to the present disclosure, the joint portion between the semiconductor chip and the bonding wire is covered with the 1 st package member having a high elastic modulus. In addition, the bent portion of the bonding wire is covered with the 2 nd encapsulating member of low elastic modulus. Therefore, damage of the bonding wire can be suppressed.

Drawings

Fig. 1 is a sectional view of a semiconductor device according to embodiment 1.

Fig. 2 is an enlarged view of the 1 st joint according to embodiment 1.

Fig. 3 is a sectional view of a semiconductor device according to modification 1 of embodiment 1.

Fig. 4 is a cross-sectional view of a semiconductor device according to modification 2 of embodiment 1.

Fig. 5 is a sectional view of a semiconductor device according to modification 3 of embodiment 1.

Fig. 6 is a flowchart showing a method for manufacturing a semiconductor device according to modification 1 of embodiment 1.

Fig. 7 is a diagram showing a state where bumps are formed on the circuit pattern.

Fig. 8 is a diagram showing a state in which the 1 st semiconductor chip and the 2 nd semiconductor chip are mounted on the bumps.

Fig. 9 is a diagram showing a state in which a case is mounted on an insulating substrate.

Fig. 10 is a diagram showing a state in which a bonding wire is formed.

Fig. 11 is a diagram showing a state where the 1 st package member is provided.

Fig. 12 is a diagram showing a state in which the 2 nd package member is provided.

Description of the reference numerals

10 an insulating substrate, 12 a base plate, 14 an insulating layer, 16a, 16b a circuit pattern, 20 a case, 21 an outer wall portion, 22 a recess, 23 a lap, 30 a bonding material, 40 a semiconductor chip, 50 bonding wire, 50a 1 st bonding portion, 50b 2 nd bonding portion, 50c bent portion, 61 st package part, 62 nd package part, 100, 200 semiconductor device, 210 an insulating substrate, 216a, 216b, 216c circuit pattern, 232 bump, 241 st semiconductor chip, 242 nd 2 semiconductor chip, 251 bonding wire, 251a 1 st bonding portion, 251b 2 nd bonding portion, 251c bent portion, 252 bonding wire, 252a 1 st bonding portion, 252b 2 nd bonding portion, 252c, 300 semiconductor device, 332a 1 st bump, 332b 2 nd bump, 341 st semiconductor chip, 342 nd semiconductor chip, 400 semiconductor device, 410 insulating substrate, 416a, 416b, 416c circuit pattern.

Detailed Description

A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and redundant description may be omitted.

Embodiment 1.

Fig. 1 is a sectional view of a semiconductor device 100 according to embodiment 1. The semiconductor device 100 is, for example, a power semiconductor device. The semiconductor device 100 includes an insulating substrate 10. The insulating substrate 10 is, for example, a resin insulating substrate. By using the resin insulating substrate, stress of the sealing member to the insulating substrate 10 can be relaxed. The insulating substrate 10 has a base plate 12, an insulating layer 14 provided on the base plate 12, and a circuit pattern 16 provided on the insulating layer 14. The insulating layer 14 is formed of, for example, resin. The circuit pattern 16 includes circuit patterns 16a, 16 b.

A semiconductor chip 40 is provided over the insulating substrate 10. The semiconductor chip 40 is, for example, a power chip. The semiconductor chip 40 may be an igbt (insulated Gate Bipolar transistor), for example. The semiconductor chip 40 is bonded to the circuit pattern 16a with the bonding material 30. The bonding material 30 is, for example, solder.

The semiconductor chip 40 and the circuit pattern 16b are connected by a bonding wire 50. The bonding wire 50 is bonded to the semiconductor chip 40 at the 1 st bonding portion 50 a. The 1 st bonding portion 50a is provided on the upper surface of the semiconductor chip 40. The bonding wire 50 is bonded to the circuit pattern 16b at the 2 nd bonding portion 50 b. In addition, the bonding wire 50 has a bent portion 50c above the 1 st bonding portion 50 a. The bent portion 50c is provided between the 1 st joint portion 50a and the 2 nd joint portion 50 b. The bent portion 50c is, for example, a portion of the bonding wire 50 disposed at the highest position. The bent portion 50c is not limited to this, and may be any bent portion of the bonding wire 50.

The semiconductor device 100 includes a case 20 surrounding an insulating substrate 10. The case 20 has an outer wall portion 21 surrounding the insulating substrate 10. The housing 20 has a mounting portion 23 projecting inward from the outer wall portion 21. The mounting portion 23 is mounted on the outer periphery of the insulating substrate 10. In the present embodiment, the mounting portion 23 is provided outside the circuit patterns 16a and 16 b. The placing portion 23 has a concave portion 22. The recess 22 opens upward.

The inside of the case 20 is enclosed by the 1 st enclosing part 61 and the 2 nd enclosing part 62. The 1 st encapsulating member 61 is provided to a height higher than the 1 st bonding portion 50a and lower than the bent portion 50c from the upper surface of the insulating layer 14. The 1 st packing member 61 fills the case 20 to a certain 1 st height. The 1 st encapsulating member 61 covers a part of the bonding wire 50, the semiconductor chip 40, the circuit patterns 16a, 16b, the insulating layer 14, and the bonding material 30. Specifically, the 1 st encapsulating member 61 covers the 1 st bonding portion 50a and the 2 nd bonding portion 50 b.

The recess 22 of the case 20 has an open surface at the level of the upper surface of the 1 st enclosing member 61. The 1 st encapsulating member 61 fills the inside of the recess 22.

The 2 nd package part 62 is disposed on the 1 st package part 61. The 2 nd encapsulating member 62 is filled to a certain 2 nd height in the case 20. The 2 nd encapsulating member 62 covers the bent portion 50 c. The 2 nd package part 62 has a lower elastic modulus than the 1 st package part 61.

Fig. 2 is an enlarged view of the 1 st engaging portion 50a according to embodiment 1. The upper surface of the 1 st package part 61 is set to be within the range of the wire diameter of the bonding wire 50 from the upper surface of the semiconductor chip 40. That is, the interface of the 1 st package component 61 and the 2 nd package component 62 is provided at a height between the bonding surfaces of the semiconductor chip 40 and the bonding wire 50 and the upper surface of the bonding wire 50.

In general, the bonding portion between the lead and the semiconductor chip and the bonding material between the semiconductor chip and the circuit pattern are covered with the encapsulating material having a high elastic modulus, and thereby the occurrence of cracks in the bonding portion or the bonding material can be suppressed. Here, the bonding wire wired from the semiconductor chip may be connected to the circuit pattern in consideration of heat dissipation. When the bonding wire is covered with a high elastic modulus sealing material, thermal stress to the wire loop portion may increase. At this time, cracks may be generated in the annular portion. In addition, it is possible to promote the development of cracks in the ring portion, and the bonding wire is broken. In particular, when the package is formed with an epoxy resin having a high elastic modulus, cracks are likely to occur not at the bonding surface between the bonding wire and the semiconductor chip but at the wire loop portion.

In addition, when the bonding material for bonding the semiconductor chip and the circuit pattern is covered with the encapsulating material having a low elastic modulus, thermal stress applied to the bonding material increases, and there is a possibility that deterioration of the bonding material is easily advanced.

In contrast, in the present embodiment, the 1 st bonding portion 50a between the bonding wire 50 and the semiconductor chip 40 is encapsulated by the 1 st encapsulating member 61 having a high elastic modulus, and the bent portion 50c of the bonding wire 50 is encapsulated by the 2 nd encapsulating member 62 having a low elastic modulus. Therefore, the 1 st bonding portion 50a can suppress the occurrence of damage such as cracks in the semiconductor chip 40 and the bonding wire 50. In addition, damage such as cracking at the bent portion 50c of the bonding wire 50 can be suppressed. In addition, the development of cracks can be suppressed. Therefore, the semiconductor device 100 can have a longer life.

In the present embodiment, the 2 nd bonding portion 50b is also sealed with the 1 st sealing member 61 having a high elastic modulus. In the present embodiment, all the bonding portions of the bonding wire 50 are covered with the 1 st encapsulating member 61. Therefore, the occurrence of damage such as cracking in the circuit pattern 16b and the bonding wire 50 at the 2 nd bonding portion 50b can be suppressed.

The bonding material 30 for bonding the semiconductor chip 40 and the circuit pattern 16a is covered with the 1 st encapsulating member 61 having a high elastic modulus. This can relax the stress applied to bonding material 30, and can suppress deterioration of bonding material 30.

In addition, the 1 st height of the upper surface of the 1 st package component 61 is set to be within a range of the wire diameter of the bonding wire 50 from the upper surface of the semiconductor chip 40. This allows the 1 st bonding portion 50a and the 2 nd bonding portion 50b to be sealed by the 1 st sealing member 61, while ensuring a large portion of the bonding wire 50 covered with the 2 nd sealing member 62. Therefore, stress applied to the bonding wire 50 which is provided in a bent state can be suppressed. Therefore, the occurrence of damage to the bonding wire 50 can be further suppressed.

In addition, as a comparative example of the present embodiment, it is conceivable that only the bonding portion with the semiconductor chip in the bonding wire is covered with a package member having a high elastic modulus. In such a configuration, particularly when a large number of semiconductor chips are provided in the case, it is considered that there are many locations where the package member having a high elastic modulus is provided. In this case, it is considered that a difference occurs between the package components in the time elapsed after the package components are set. This may cause a difference in the spread of the resin between the package members. Therefore, it is likely that control of the resin height becomes difficult.

In contrast, in the present embodiment, the 1 st package member 61 is provided at a fixed 1 st height from the upper surface of the insulating substrate 10. Therefore, the height of the 1 st package member 61 can be easily controlled. In addition, the 2 nd package member 62 is provided on the upper surface of the 1 st package member 61 which is provided flat. Therefore, the height of the 2 nd package member 62 can be easily controlled.

In the present embodiment, the housing 20 is provided with the recess 22. The recess 22 has an open face at a target height of the 1 st package component 61. The 1 st package member 61 can be set to the 1 st height by filling the 1 st package member 61 to the opening surface of the recess 22. Therefore, the height of the 1 st package member 61 can be easily confirmed. In addition, the height of the 1 st package part 61 can be accurately controlled.

In the present embodiment, the 1 st height of the upper surface of the 1 st package member 61 may be higher than the 1 st bonding portion 50a and lower than the bent portion 50 c. For example, the 1 st encapsulating member 61 may be provided up to a height covering most of the bonding wire 50 other than the bent portion 50 c.

In the present embodiment, the 2 nd joining portion 50b is provided below the 1 st joining portion 50 a. Therefore, in the case where the 1 st bonding portion 50a is covered with the 1 st sealing member 61, the 2 nd bonding portion 50b is naturally covered with the 1 st sealing member 61 as well. Without being limited thereto, the 2 nd engaging portion 50b may be provided at the same height as the 1 st engaging portion 50a or above the 1 st engaging portion 50 a. In this case, the 1 st height of the upper surface of the 1 st package member 61 may be higher than the 2 nd bonding portion 50b and lower than the bent portion 50 c.

The bonding wire 50 may be connected to an element other than the circuit pattern 16 b. For example, the semiconductor chip 40 may be connected to other semiconductor chips or electrodes by bonding wires 50. In this case, the 2 nd bonding portion 50b is provided to another chip or electrode.

In fig. 1, the dimples formed in the concave portions 22 are rectangular in cross-sectional view. The shape of the pit is not limited thereto. The dimples may also be triangular, polygonal, or semi-circular.

The height of the opening surface of the recess 22 may be set near the interface between the 1 st package member 61 and the 2 nd package member 62. The recess 22 may be a reference for filling the 1 st sealing member 61. The height of the opening surface of the recess 22 may be higher or lower than the target height of the 1 st packing member 61.

The 1 st package member 61 flows into the recess 22 over, for example, the side surface of the recess 22. A groove serving as a flow path of the 1 st package member 61 may be formed on a side surface of the recess 22. The opening surface of the concave portion 22 may not face upward. For example, the opening surface of the recess 22 may be oriented in the horizontal direction. The horizontal direction is a direction parallel to the upper surface of the base plate 12.

The 1 st package member 61 may have an elastic modulus of 10GPa or more. The 1 st package member 61 is preferably an epoxy resin of 10 to 30GPa, for example. The elastic modulus of the 2 nd package member 62 may be 10GPa or less. The 2 nd encapsulating member 62 may also be, for example, a silicone gel.

The semiconductor chip 40 may be formed of a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride based material or diamond. This can further improve the heat resistance of the semiconductor device 100.

Fig. 3 is a sectional view of a semiconductor device 200 according to modification 1 of embodiment 1. The semiconductor device 200 has an insulating substrate 210. The insulating substrate 210 has circuit patterns 216a to 216c as the circuit pattern 216. Bumps 232 are disposed on the circuit patterns 216a and 216b, respectively. The bump 232 is formed of an aluminum wire or the like.

A 1 st semiconductor chip 241 and a 2 nd semiconductor chip 242 are disposed over the insulating substrate 210. The 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 may be the same kind of semiconductor chip or different kinds of semiconductor chips. For example, one of the 1 st and 2 nd semiconductor chips 241 and 242 may be an IGBT and the other may be a diode.

The 1 st semiconductor chip 241 is disposed over the bump 232 on the circuit pattern 216 a. The 1 st semiconductor chip 241 is bonded to the circuit pattern 216a with the bonding material 30 in a state of being mounted on the bump 232. The 2 nd semiconductor chip 242 is disposed over the bump 232 on the circuit pattern 216 b. The 2 nd semiconductor chip 242 is bonded to the circuit pattern 216b with the bonding material 30 in a state of being mounted on the bump 232. The bonding material 30 is provided so as to surround the bump 232.

The 1 st semiconductor chip 241 and the circuit pattern 216b are connected by a bonding wire 251. The bonding wire 251 is bonded to the 1 st semiconductor chip 241 at the 1 st bonding portion 251 a. The bonding wire 251 is bonded to the circuit pattern 216b at the 2 nd bonding portion 251 b. In addition, the bonding wire 251 has a bent portion 251c above the 1 st bonding portion 251 a.

The 2 nd semiconductor chip 242 and the circuit pattern 216c are connected by a bonding wire 252. The bonding wire 252 is bonded to the 2 nd semiconductor chip 242 at the 1 st bonding portion 252 a. The bonding wire 252 is bonded to the circuit pattern 216c at the 2 nd bonding portion 252 b. In addition, the bonding wire 252 has a bent portion 252c above the 1 st bonding portion 252 a.

The 1 st semiconductor chip 241 is identical in height to the 2 nd semiconductor chip 242 in height. The 1 st encapsulating member 61 is provided to be higher than the 1 st bonding portions 251a and 252a and lower than the bent portions 251c and 252c from the upper surface of the insulating layer 14. The 1 st encapsulating member 61 covers the 1 st bonding portions 251a and 252a, the 2 nd bonding portions 251b and 252b, and the bonding material 30. The 2 nd encapsulating member 62 covers the bent portions 251c, 252 c.

With the semiconductor device 200, the heights of the 1 st and 2 nd semiconductor chips 241, 242 can be adjusted by the bumps 232. Therefore, for example, when the height of the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 with respect to the opening surface of the concave portion 22 is too low, the height of the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 can be secured by the bump 232.

In addition, the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 are each in contact with the bump 232. Therefore, the inclination of the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 can be made uniform. In addition, the completion of the bonding of the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 can be made uniform. This makes it possible to easily align the heights of the plurality of semiconductor chips.

Fig. 4 is a cross-sectional view of a semiconductor device 300 according to modification 2 of embodiment 1. In the semiconductor device 300, the 1 st bump 332a is disposed over the circuit pattern 216 a. The 1 st semiconductor chip 341 is disposed over the 1 st bump 332 a. In addition, a 2 nd bump 332b is disposed over the circuit pattern 216 b. The 2 nd bump 332b is lower in height than the 1 st bump 332 a. The 2 nd semiconductor chip 342 is disposed over the 2 nd bump 332 b. The 2 nd semiconductor chip 342 is thicker than the 1 st semiconductor chip 341. The upper surface of the 1 st semiconductor chip 341 coincides with the height of the upper surface of the 2 nd semiconductor chip 342.

Even when the semiconductor device 300 includes a plurality of semiconductor chips having different thicknesses, the heights of the semiconductor chips can be made uniform by the bumps having different heights. This allows the case 20 and the insulating substrate 210 to be standardized. In the present modification, the circuit patterns 216a to 216c are equal in thickness.

Here, an example in which the thickness of the semiconductor chip is 2 is shown. Without being limited thereto, the semiconductor device 300 may also have 3 or more kinds of semiconductor chips having different thicknesses from each other. In this case, the heights of the semiconductor chips may be made uniform by 3 or more kinds of bumps having different heights from each other.

Fig. 5 is a sectional view of a semiconductor device 400 according to modification 3 of embodiment 1. The semiconductor device 400 has an insulating substrate 410. On the insulating substrate 410, a circuit pattern 416 is provided on the base plate 12 with the insulating layer 14 interposed therebetween. The circuit pattern 416 includes circuit patterns 416a to 416 c. The circuit pattern 416b is thinner than the circuit pattern 416 a. Bumps 232 are disposed on the circuit patterns 416a, 416b, respectively. In the present modification, the bumps 232 have the same height.

The 1 st semiconductor chip 341 is disposed over the circuit pattern 416 a. The 2 nd semiconductor chip 342 is disposed over the circuit pattern 416 b. The 2 nd semiconductor chip 342 is thicker than the 1 st semiconductor chip 341. The upper surface of the 1 st semiconductor chip 341 coincides with the height of the upper surface of the 2 nd semiconductor chip 342.

In this way, the thickness of the circuit pattern 416 can be adjusted so that the heights of the upper surfaces of the plurality of semiconductor chips having different thicknesses are uniform. Here, an example in which the thickness of the semiconductor chip is 2 is shown. Without being limited thereto, the semiconductor device 400 may also have 3 or more kinds of semiconductor chips having different thicknesses from each other. In this case, the heights of the semiconductor chips can be made uniform by the circuit patterns 416 having different thicknesses from each other.

Fig. 6 is a flowchart showing a method for manufacturing the semiconductor device 200 according to modification 1 of embodiment 1. A method for manufacturing the semiconductor device 200 will be described with reference to fig. 6 to 12.

First, as step 1, a bump 232 is formed over an insulating substrate 210. Fig. 7 is a diagram showing a state in which bumps 232 are formed on the circuit pattern 216. The number of lugs 232 can be adjusted as desired. In a state where the semiconductor chip is mounted on the bump 232, the height of the bump 232 is adjusted so that the upper surface of the semiconductor chip is lower than the target height of the 1 st package component 61 and is within the range of the wire diameter from the target height. Further, the bump 232 may not be provided.

Next, as step 2, the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 are provided over the bump 232, and the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 are bonded. Fig. 8 is a diagram showing a state in which the 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 are mounted on the bump 232. The 1 st semiconductor chip 241 and the 2 nd semiconductor chip 242 are bonded to the circuit pattern 216 with the bonding material 30 in a state of being mounted on the bump 232.

Next, as step 3, the case mounting is performed. Fig. 9 is a diagram showing a state in which case 20 is mounted on insulating substrate 210. The case 20 is bonded to the insulating substrate 210 with an adhesive. The adhesive is, for example, a silicone adhesive or an epoxy adhesive.

Next, as step 4, wire bonding is performed. Fig. 10 is a diagram showing a state in which the bonding wires 251 and 252 are formed. Thereby, the 1 st semiconductor chip 241 is bonded to the bonding wire 251. At this time, a bent portion 251c is formed in the bonding wire 251 above the 1 st bonding portion 251a with the 1 st semiconductor chip 241. In addition, the 2 nd semiconductor chip 242 is bonded to the bonding wire 252. At this time, a bent portion 252c is formed in the bonding wire 252 above the 1 st bonding portion 252a with the 2 nd semiconductor chip 242.

Next, as step 5, the 1 st packaging is performed. Fig. 11 is a diagram showing a state where the 1 st package member 61 is provided. In the 1 st package, the 1 st package member 61 is packaged from the upper surface of the insulating substrate 210 to a height higher than the 1 st bonding portions 251a and 252a and lower than the bent portions 251c and 252 c. Thus, the 1 st bonding portions 251a and 252a, the 2 nd bonding portions 251b and 252b, and the bonding material 30 are covered with the 1 st encapsulating member 61. At this time, the 1 st sealing member 61 is filled with reference to the opening surface of the recess 22 of the case 20.

In addition, when the bent portions 251c and 252c have different heights, the first sealing member 61 may seal the bent portions 251c and 252c to a height lower than the lowest bent portion among the plurality of bent portions 251c and 252 c.

Next, as step 6, curing is performed.

Next, as step 7, the 2 nd packaging is performed. Fig. 12 is a diagram showing a state where the 2 nd encapsulating member 62 is provided. In the 2 nd package, the upper surface of the 1 st package member 61 is packaged by the 2 nd package member 62 having a lower elastic modulus than the 1 st package member 61. Thereby, the bent portions 251c and 252c are covered by the 2 nd encapsulating member 62.

Next, as step 8, curing is performed.

As described above, in the present embodiment, 2 kinds of package members may be set to a predetermined height. Therefore, in the sealing step, the resin may be poured into the case 20, and the semiconductor device 200 can be easily manufactured. In addition, the height of the package member can be stably controlled.

As a modification of the manufacturing method, the case may be mounted after the wire bonding is performed. In addition, the wire bonding process may be added by further performing wire bonding after the housing is mounted. In addition, instead of performing the curing in step 6, the curing may be performed collectively in step 8.

In addition, the technical features described in the present embodiment can also be used in combination as appropriate.