阅读说明：本技术 Tsv之上的大金属焊盘 (Large metal pad over TSV ) 是由 G·高 B·李 G·G·小方丹 C·E·尤佐 L·W·米卡里米 B·哈巴 R·卡特卡尔 于 2019-06-13 设计创作，主要内容包括：包括过程步骤的代表性技术和器件可以被采用,来减轻由于接合界面处的金属膨胀而导致接合的微电子衬底的分层的可能性。例如,当接触焊盘被定位在一个或两个衬底中的TSV之上时,可以使用具有较大直径或表面面积(例如,针对应用是尺寸过大的)的金属焊盘。(Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of the bonded microelectronic substrates due to metal expansion at the bonding interface. For example, when contact pads are positioned over TSVs in one or both substrates, metal pads having a larger diameter or surface area (e.g., oversized for the application) may be used.)

1. A method of forming a microelectronic assembly, comprising:

providing a first through-silicon via (TSV) in a first substrate having a first bonding surface, the first TSV being perpendicular to the first bonding surface;

forming a first metal contact pad at or slightly recessed from the first bonding surface, the first metal contact pad being electrically coupled to the first TSV, the first metal contact pad extending partially into the first substrate below the first bonding surface, and the first metal contact pad being aligned with the first TSV in a direction from the first bonding surface through the first substrate; and

planarizing the first bonding surface to have a predetermined maximum surface variation for direct bonding, and adjusting the recess of the first metal contact pad relative to the first bonding surface to compensate for thermal expansion of the TSV and first metal contact pad relative to the first bonding surface.

2. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: forming a second metal contact pad at or slightly recessed to the first bonding surface, the second metal contact pad being misaligned with the TSV in the direction from the first surface through the first substrate, wherein the first metal contact pad is more recessed than the second metal contact pad relative to the first bonding surface.

3. A method of forming a microelectronic assembly as claimed in claim 2, wherein the first metal contact pad has a greater surface area than the second metal contact pad at the first bonding surface.

4. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: the first TSV is exposed from a surface opposite the first bonding surface.

5. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: treating the surface opposite the first bonding surface to provide a second bonding surface.

6. A method of forming a microelectronic assembly as claimed in claim 1, further comprising:

providing a second substrate;

directly bonding the first bonding surface of the first substrate to the second substrate without an intervening adhesive.

7. The method of forming a microelectronic assembly as claimed in claim 4, wherein the second substrate further comprises: a conductive via extending at least partially through the second substrate.

8. A method of forming a microelectronic assembly as claimed in claim 1, further comprising: heating the bonded first and second substrates to provide an electrical path between the first metal contact pad and an electrical feature on the second substrate.

9. A method of forming a microelectronic assembly, comprising:

forming a first TSV provided within a first substrate having a first bonding surface, the first TSV extending into the first substrate in a direction perpendicular to the first bonding surface;

forming first and second metal contact pads at or slightly recessed from the first bonding surface, the first metal contact pad partially extending into the first substrate below the first bonding surface and aligned with the first TSV in a direction through the first substrate from the first bonding surface, the second metal contact pad at or slightly recessed from the first bonding surface, the second metal contact pad partially extending into the first substrate below the first bonding surface and misaligned with the first TSV in the direction through the first substrate from the first bonding surface; and

planarizing the first bonding surface to have a predetermined maximum surface variation for direct bonding, and adjusting the depression of the first and second metal contact pads relative to the first bonding surface such that the depression of the first metal contact pad compensates for thermal expansion of the TSV and first metal contact pad relative to the first bonding surface.

10. The method of forming a microelectronic assembly as claimed in claim 9, wherein the first metal contact pad has a greater surface area than the second metal contact pad.

11. A method of forming a microelectronic assembly as claimed in claim 9, further comprising: processing a side of the first substrate opposite the first bonding surface to form a second bonding surface.

12. A method of forming a microelectronic assembly as claimed in claim 11, wherein the processing includes: the first substrate is thinned and one or more layers are deposited to balance the stress induced in the first substrate by the first surface.

13. A method of forming a microelectronic assembly as claimed in claim 12, wherein thinning the first substrate exposes the first TSV, and the one or more layers are formed over the TSV, the method further comprising: the one or more layers are patterned to form an opening over the first TSV.

14. The method of forming a microelectronic assembly as claimed in claim 13, further comprising:

depositing a barrier layer on the exposed surface of the opening; and

depositing a conductive material on the barrier layer and within the opening.

15. The method of forming a microelectronic assembly as claimed in claim 11, further comprising: directly bonding the first substrate to a second substrate using a direct dielectric-to-dielectric non-adhesive bonding technique at the first bonding surface of the first substrate.

16. The method of forming a microelectronic assembly as claimed in claim 15, further comprising: transferring heat from the first substrate to the second substrate via the first TSV and one or more conductive structures embedded within the second substrate and exposed at a bonding surface of the second substrate.

17. A microelectronic assembly, comprising:

a first TSV provided within a first substrate having a first bonding surface, the first TSV extending into the first substrate in a direction perpendicular to the first bonding surface; and

a first metal contact pad and a second metal contact pad at the first bonding surface or slightly recessed from the first bonding surface, the first metal contact pad extends partially into the first substrate below the first bonding surface, and the first metal contact pad is aligned with the first TSV in a direction from the first bonding surface through the first substrate, the second metal contact pad is at or slightly recessed from the first bonding surface, the second metal contact pad extends partially into the first substrate below the first bonding surface, and the second metal contact pad is misaligned with the first TSV in the direction from the first bonding surface through the first substrate, the first metal contact pad has a larger surface area than the second metal contact pad.

18. The microelectronic assembly of claim 17, wherein the first substrate comprises: a second engagement surface on a side opposite the first engagement surface.

19. The microelectronic assembly as claimed in claim 17, the first substrate including a stress-balancing layer to compensate for stress induced in the first substrate by the first surface.

20. The microelectronic assembly of claim 17, wherein at the first bonding surface of the first substrate, the first substrate is directly bonded to a second substrate using a direct dielectric-to-dielectric non-adhesive bonding technique.

Technical Field

The following description relates to integrated circuits ("ICs"). More particularly, the following description relates to the fabrication of IC dies (die) and wafers.

Background

Microelectronic elements typically include thin planar sheets of semiconductor material (such as silicon or gallium arsenide), which are commonly referred to as semiconductor wafers. The wafer may be formed to include a plurality of integrated chips or dies on the wafer surface and/or partially embedded within the wafer. The die, which is separate from the wafer, is typically provided as a separate, pre-packaged unit. In some package designs, the die is mounted to a substrate or chip carrier, which in turn is mounted on a circuit panel such as a Printed Circuit Board (PCB). For example, many dies are provided in packages suitable for surface mounting.

Packaged semiconductor dies can also be provided in a "stacked" arrangement, where one package is provided on a circuit board or other carrier, for example, and the other package is mounted on top of the first package. These arrangements may allow several different dies and devices to be mounted within a single footprint (footprint) on a circuit board, and may further facilitate high speed operation by providing short interconnections between packages. Typically, the interconnect distance may be only slightly greater than the thickness of the die itself. To achieve interconnections within the stack of die packages, interconnect structures for mechanical and electrical connections may be provided on both sides (e.g., faces) of each die package (except for the topmost package).

Additionally, the die or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This may include: stacking layers of one or more dies, devices, and/or wafers on a larger base die, device, wafer, substrate, or the like: stacking multiple dies or wafers in a vertical or horizontal arrangement, as well as various combinations of the two.

The die or wafer may be bonded in a stacked arrangement using a variety of bonding techniques, including direct dielectric bonding, non-adhesive techniques (such as,) Or a hybrid bonding technique (such as,) Both are available from Invensas binding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi Inc. Bonding includes spontaneous processes that occur under ambient conditions when two prepared surfaces are brought together (see, e.g., U.S. patent nos. 6,864,585 and 7,485,968, the contents of which are incorporated herein in their entirety).

The respective mating surfaces of the bonded die or wafers typically include embedded conductive interconnect structures (which may be metal) or the like. In some examples, the bonding surfaces are arranged and aligned such that conductive interconnect structures from the respective surfaces are coupled during bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies or wafers.

Implementing stacked die and wafer arrangements can present various challenges. When bonding stacked dies using direct bonding or hybrid bonding techniques, it is often desirable that the surfaces of the dies to be bonded be extremely flat, smooth, and clean. For example, in general, these surfaces should have very low variation in surface topography (i.e., nanoscale variation) so that the surfaces can mate to form a durable bond.

Double-sided dies can be formed and prepared for stacking and bonding, where both sides of the die are to be bonded to other substrates or dies, such as in the case of multi-die-to-die or multi-die-to-wafer. Preparing both sides of the die includes processing (finish) both surfaces to meet the dielectric roughness specification and the metal layer (e.g., copper, etc.) recess specification. For example, the conductive interconnect structure at the bonding surface may be slightly recessed, just below the insulating material of the bonding surface. The amount of recess below the engagement surface may be determined by dimensional tolerances, specifications, or physical limitations of the device or application. The hybrid surface can be prepared to be bonded to another die, wafer, or other substrate using a Chemical Mechanical Polishing (CMP) process, or the like.

Typically, when direct bond surfaces comprising a combination of a dielectric layer and one or more metal features (e.g., embedded conductive interconnect structures) are bonded together, the dielectric surfaces are first bonded at a lower temperature and then the metal of the features expands as the metal is heated during annealing. The expansion of the metal causes the metal from the two bonding surfaces to bond into a unified conductive structure (metal-to-metal bond). Although both the substrate and the metal are heated during annealing, the Coefficient of Thermal Expansion (CTE) of the metal relative to the CTE of the substrate generally dictates that: at a certain temperature (e.g., -300 ℃), the metal expands much more than the substrate. For example, copper has a CTE of 16.7, while fused silica has a CTE of 0.55, and silicon has a CTE of 2.56.

In some cases, greater expansion of the metal relative to the substrate can be a problem for directly bonding stacked die or wafers. If the metal pad is positioned over a through-silicon via (TSV), the expansion of the TSV metal may contribute to the expansion of the pad metal. In some cases, as the expanding metal rises above the bonding surface, the combined metal expansion may cause local delamination of the bonding surface. For example, the expansion metal may separate the bonding dielectric surfaces of the stacked dies.

Disclosure of Invention

Representative techniques and devices are disclosed, including process steps for preparing various microelectronic devices for bonding, such as for direct bonding without the need for adhesives. In various embodiments, techniques may be employed to mitigate the potential for delamination due to metal expansion, particularly when TSVs or bond pads over TSVs are present at the bonding surface of one or both devices to be bonded. For example, in one embodiment, metal pads having a larger diameter or surface area (e.g., oversized for the application) may be used when the contact pad is positioned over the TSV. For example, the contact pad may be selected based on its material, its thickness, and the depression expected during processing, including the size of the contact pad (e.g., surface area, diameter, etc.) or the amount of oversize (oversize) of the contact pad.

When a surface preparation process such as CMP is used to prepare the bonding surface of the substrate, the metal pads on the bonding surface may become recessed relative to the dielectric due to the softer material of the pads relative to the material of the dielectric. Larger diameter metal pads may become recessed to a greater extent (e.g., deeper recess) than smaller diameter pads. In embodiments where the contact pad is positioned over the TSV, the deeper recess may compensate for the combined metal expansion of the pad and TSV, allowing more room for the expansion of the metal, which may reduce or eliminate delamination that may otherwise occur when the metal expands.

In various implementations, an example process includes: a first through-silicon via (TSV) is embedded in a first substrate having a first bonding surface, wherein the first TSV is perpendicular to the first bonding surface (i.e., vertical within a horizontally oriented substrate having an approximately horizontally oriented bonding surface). The process may include: based on the volume of the material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV, an amount by which the material of the first TSV will expand when heated to a preselected temperature is estimated. The process comprises the following steps: based on the estimate, or based on a volume of material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV, a first metal contact pad is formed at the first bonding surface and coupled to the first TSV.

The first metal contact pad is disposed at the first bonding surface (and may be disposed directly over the first TSV) and extends partially into the first substrate below the first bonding surface, thereby electrically coupling the first metal contact pad to the first TSV. In this embodiment, the process includes: the first bonding surface is planarized to have a predetermined maximum surface variation for direct bonding and the first metal contact pad is planarized to have a predetermined recess relative to the first bonding surface based on a volume of a material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV.

In various examples, selecting or forming a contact pad includes: the diameter or surface area of the first metal contact pad is selected. For example, the first metal contact pad may be selected or formed to have an oversized diameter, an oversized surface area, or the like, as compared to what would normally be the case for a similar application. In one embodiment, the process includes: based on the prediction, a desired recess of the first metal contact pad relative to the first bonding surface is determined to allow for expansion of the material of the first TSV, and the material of the first metal contact pad, and the first metal contact pad is selected to have a perimeter shape that is likely to result in the desired recess when the first metal contact pad is planarized. This may include: predicting an amount of dishing that may occur in a surface of the first metal contact pad as a result of the planarization. In another embodiment, the process includes: based on the above determination, a desired recess is formed in the surface of the first metal contact pad (prior to bonding).

In various embodiments, the process includes: by selecting the first metal contact pad, delamination of the bonded microelectronic components is reduced or eliminated. In an alternative implementation, the process includes: the material of the first bonding surface is recessed or etched directly around the first metal contact pad to allow for expansion of the material of the first TSV, and the material of the first metal contact pad, based on the volume of the material of the first TSV, and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV.

Additionally or alternatively, the backside of the first substrate may also be processed for bonding. One or more insulating layers of preselected materials may be deposited on the back side of the first substrate to provide stress relief when the back side of the first substrate is to be bonded directly.

Further, the first TSV and other TSVs within the first substrate may be used to direct or transfer heat within the first substrate and/or away from the first substrate. In some implementations, the thermal transfer TSV may extend partially or completely through the thickness of the first substrate and may include a thermally conductive barrier layer. In such an example, the barrier layer that tends to be thermally insulating, which is typically used around TSVs, may be replaced by a thermally conductive layer. In various implementations, some TSVs may be used for signal transfer and heat transfer.

In one embodiment, a microelectronic assembly includes a first substrate including a first bonding surface having a planarized topography with a first predetermined maximum surface variation. A first through-silicon via (TSV) is embedded in the first substrate, and a first metal contact pad is disposed at the first bonding surface and electrically coupled to the first TSV. For example, a first contact pad may be disposed over a first TSV. The first metal contact pad may be selected or formed based on an estimate of an amount that the material of the first TSV will expand when heated to a preselected temperature, and/or based on a volume of the material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV. A predetermined depression is provided in the surface of the first metal contact pad, the depression having a volume equal to or greater than: an amount of expansion of the material of the first TSV and an amount of expansion of the material of the first metal contact pad when heated to a preselected temperature.

In one implementation, a first metal contact pad is positioned over a first TSV, and has an oversized diameter, or an oversized surface area, as compared to pads typically used for similar applications.

Various embodiments and devices are discussed with reference to electrical and electronic components and varying carriers. Although specific components (i.e., die, wafer, Integrated Circuit (IC) chip die, substrate, etc.) are mentioned, this is not intended to be limiting, but is done for ease of discussion and illustration. The techniques and devices discussed with reference to wafers, dies, substrates, etc., are applicable to any type or number of electronic components, circuits (e.g., Integrated Circuits (ICs), hybrids, ASICs, memory devices, processors, etc.), groups of components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), etc., that may be coupled to interface with each other, with external circuits, systems, carriers, etc. Each of these various components, circuits, groups, packages, structures, etc. may be collectively referred to as "microelectronic components. For simplicity, a component that is bonded to another component will be referred to herein as a "die" unless otherwise specified.

This summary is not intended to give a complete description. Implementations are explained in more detail below using a number of examples. Although various implementations and examples are discussed herein and below, additional implementations and examples are possible by combining the features and elements of the various implementations and examples.

Drawings

The embodiments are explained with reference to the drawings. In the drawings, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference symbols in different drawings indicates similar or identical items.

For purposes of this discussion, the devices and systems shown in the figures are illustrated as having multiple components. As described herein, various implementations of devices and/or systems may include fewer components and still be within the scope of the present disclosure. Alternatively, other implementations of devices and/or systems may include additional components or various combinations of the described components and still be within the scope of the present disclosure.

Fig. 1A shows a cross-section of an example substrate with bond pads and TSVs.

FIG. 1B shows a top view of the example substrate of FIG. 1A.

Fig. 2 shows a cross-section of two example bonded substrates with bond pads and TSVs, and example resulting delamination.

Fig. 3A shows a cross-section of an example substrate having a larger bond pad positioned over a TSV, in accordance with one embodiment.

FIG. 3B illustrates a top view of the example substrate of FIG. 3A, according to one embodiment.

Fig. 4 shows a cross-section of two example bonded substrates having a larger bond pad positioned over a TSV according to an embodiment.

Fig. 5 shows a cross-section of an example substrate having a bond pad positioned over a TSV, illustrating an example recess of the bond pad.

Fig. 6 shows a cross-section of an example substrate with a larger bond pad positioned over a TSV illustrating an example recess of the bond pad, in accordance with one embodiment.

Fig. 7 shows cross-sections of two example bonded substrates with bond pads having non-planar bonding surfaces before and after annealing, according to one embodiment.

Fig. 8 shows a cross-section of an example substrate having a bond pad positioned over a TSV and having an etch or recess of dielectric around the bond pad, in accordance with one embodiment.

Fig. 9-13 show cross-sections of an example substrate with bond pads positioned over TSVs, illustrating an example backside process of the substrate, in accordance with one embodiment.

Fig. 14 shows a cross section of a front-to-back bonded substrate with two example bonds of TSVs and bond pads, in accordance with one embodiment.

Fig. 15 shows a cross section of a back-to-back bonded substrate with two example bonds of TSVs and bond pads, in accordance with one embodiment.

Fig. 16 shows a cross section of a substrate being bonded, with two example bonds of TSVs and bond pads, in accordance with one embodiment.

Fig. 17 shows a diagram of an example TSV for thermal management of a die, in accordance with various embodiments.

Fig. 18 is a text flow diagram illustrating an example process of forming a microelectronic assembly to reduce or eliminate delamination of a bonded substrate, according to one embodiment.

Detailed Description

SUMMARY

With reference to FIG. 1A (showing a cross-sectional profile view) and FIG. 1B (showing a top view), the patterned metal and oxide layers are often used as a hybrid junction, orThe surface layer is provided on a die, wafer, or other substrate (hereinafter "die 102"). The representative device die 102 may be formed using various techniques to include a base substrate 104 and one or more insulating or dielectric layers 106. The base substrate 104 may be composed of silicon, germanium, glass, quartz, a dielectric surface, a direct indirect bandgap semiconductor material, or an indirect bandgap semiconductor material or layer or other suitable material. The insulating layer 106 is deposited or formed over the substrate 104 and may be composed of a layer of inorganic dielectric material such as an oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond-like material, glass, ceramic, glass-ceramic, or the like.

The bonding surface 108 of the device wafer 102 may include conductive features 110, such as traces, pads, and other interconnect structures, for example, embedded in the insulating layer 106 and arranged such that the conductive features 110 from the corresponding bonding surface 108 of the opposing device may be mated and joined during bonding (if desired). The joined conductive features 110 may form a continuous conductive interconnect (for signals, power, etc.) between the stacked devices.

A damascene process (or the like) may be used to form the embedded conductive features 110 in the insulating layer 106. The conductive features 110 may be comprised of a metal (e.g., copper, etc.) or other conductive material or combination of materials, and include structures, traces, pads, patterns, and the like. In some examples, prior to depositing the material of the conductive feature 110, a barrier layer may be deposited in the cavity for the conductive feature 110 such that the barrier layer is disposed between the conductive feature 110 and the insulating layer 106. The barrier layer may be comprised of, for example, tantalum or another conductive material to prevent or reduce diffusion of the material of the conductive features 110 into the insulating layer 106. After forming the conductive features 110, the exposed surfaces of the device wafer 102, including the insulating layer 106 and the conductive features 110, may be planarized (e.g., via CMP) to form a planar bonding surface 108.

Forming the engagement surface 108 includes: the surface 108 is machined to meet dielectric roughness specifications and metal layer (e.g., copper, etc.) dishing specifications to prepare the surface 108 for direct bonding. In other words, the joining surface 108 is formed to be as flat and smooth as possible with very little surface topography variation. Various conventional processes such as Chemical Mechanical Polishing (CMP), dry etching, or wet etching may be used to achieve low surface roughness. This process provides a flat, smooth surface 108 that results in a reliable bond.

In the case of a double-sided die 102, a patterned metal and insulating layer 106 with prepared bonding surfaces 108 may be provided on both sides of the die 102. The insulating layer 106 is typically highly planar (typically to a nanometer-scale roughness) with a metal layer (e.g., embedded conductive features) at the bonding surface 108, or recessed just below the bonding surface 108. Typically, the amount of recess below the surface 108 of the insulating layer 106 is typically determined by dimensional tolerances, specifications, or physical limitations. The bonding surface 108 is typically prepared using a Chemical Mechanical Polishing (CMP) step and/or other preparation steps to directly bond with another die, wafer, or other substrate.

Some embedded conductive features or interconnect structures may include metal pads 110 or conductive traces 112 that extend partially into the dielectric substrate 106 below the prepared surface 108. For example, some patterned metal (e.g., copper) features 110 or 112 may be about 0.5 to 2 microns thick. The metal of these features 110 or 112 may expand as the metal is heated during annealing. Other conductive interconnect structures may include metal (e.g., copper) Through Silicon Vias (TSVs) 114 or the like, which extend perpendicular to the bonding surface 108, partially or completely through the substrate 102, and include a substantial amount of metal. For example, the TSV114 may extend approximately 50 microns depending on the thickness of the substrate 102. The metal of the TSV114 may also expand when heated. The pads 110 and/or traces 112 may or may not be electrically coupled to the TSVs 114, as shown in fig. 1A.

Referring to fig. 2, the die 102 may be bonded directly to other dies 102, e.g., without an adhesive, the other dies 102 having metal pads 110, traces 112, and/or TSVs 114. If the metal pad 110 is positioned over the TSV114 (electrically coupled to the TSV 114), the expansion of the TSV114 metal may contribute to the expansion of the pad 110 metal. In some cases, as the expanding metal rises above the bonding surface 108, the combined metal expansion may result in a local delamination 202 of the bonding surface at the location of the TSV114 (or TSV 114/pad 110 combination). For example, the expanded metal may separate the bonded dielectric surfaces 108 of the stacked dies 102.

Example embodiments

Referring to fig. 3A, 3B, and 4, in various embodiments, techniques may be employed to mitigate the possibility of delamination due to metal expansion. For example, in one embodiment, metal pads 302 having a larger diameter or surface area (e.g., oversized for the application) may be used in place of contact pads 110 when positioned over TSVs 114. For example, at the surface 108 of the die 102, the pad 302 may have a larger diameter than the other contact pads 110, such that for a given CMP process, the pad 302 will have a deeper recess than the other contact pads 110 that are not positioned over the TSV 114. Similar to contact pad 110, contact pad 302 may be embedded in dielectric layer 106, extend partially into dielectric layer 106 below bonding surface 106, and be electrically coupled to TSV 114. For example, the amount by which metal pad 302 is oversized may be selected based on the material of pad 302, its thickness, and the expected dishing during the CMP process.

As shown in fig. 3A (showing a cross-sectional profile view) and 3B (showing a top view), the pads 302 disposed over the TSVs 114 may be larger (in area, diameter, etc.) by a preselected amount than other pads 110 disposed elsewhere at the bonding surface 108 of the die 102 (e.g., not disposed over the TSVs 114). In one embodiment, the pads 302 are selected or formed by: the amount by which the material of the TSV114 will expand when heated to a preselected temperature (-300 deg.) is estimated based on the volume of the material of the TSV114 and the Coefficient of Thermal Expansion (CTE) of the material of the TSV114, and the amount by which the material of the contact pad 302 will expand when heated to the preselected temperature is predicted based on the volume of the material of the contact pad 302 and the CTE of the material of the contact pad.

The contact pad 302 is planarized along with the bonding surface 108 of the dielectric layer 106, including recessing the contact pad 302 to have a predetermined recess depth (or amount) relative to the bonding surface 108 based on estimating and predicting expansion of the TSV114 material and the contact pad 302 material at a preselected temperature.

Referring to fig. 4, after preparing the bonding surface 108 (e.g., by CMP), the die 102 may be bonded directly to other dies 102 without, for example, an adhesive, the other dies 102 having metal pads 110 and/or 302, traces 112, and/or TSVs 114. When the metal pad 302 is positioned over the TSV114 and recessed by a predetermined or predictable amount, the recess provides space for material expansion without delamination. The TSV114 material and the pad 302 material expand during the thermal anneal. The mating contact pads 302 (or 302 and 110 in some examples) of the opposing dies 102 are joined to form a single conductive interconnect. However, since the expanded metal does not exceed the volume formed by the depression(s) in the contact pad 302 (or 302 and 110 in some examples), the combined metal expansion does not result in delamination of the bonding surface. For example, if the volume of the recess (es) is sufficient, the expanded metal does not separate the bonded dielectric surfaces 108 of the stacked die 102, as shown in fig. 4.

Referring to fig. 5 and 6, details of contact pads 110 and 302 over TSV114 are illustrated. A portion of die 102 is shown with contact pad 110 over TSV114 (fig. 5), followed by contact pad 302 over TSV114 (fig. 6). When the bonding surface 108 of the die 102 is prepared using a surface preparation process such as CMP, the metal pads 110 or 302 on the bonding surface 108 may tend to become recessed relative to the dielectric 106 due to the softness of the contact pads 110 or 302 (which may comprise copper, for example) relative to the dielectric 106 (which may comprise oxide, for example).

In various embodiments, during a similar CMP process, a contact pad 302 having a larger diameter or surface area a2 (as shown at fig. 5 and 6, where a2> a1) may be recessed to a greater extent "d 2" (e.g., a deeper recess) than a recess "d 1" of a smaller diameter pad 110, as compared to a contact pad 110 having a smaller diameter or surface area a 1. The deeper recess "d 2" may compensate for the combined metal expansion of the pad 302 and TSV114, allowing more room for expansion of the metal, and may reduce or eliminate delamination. In some embodiments, the contact pad 302 may be intentionally recessed to a desired depth "d 2," and in other embodiments, the contact pad 302 may be selected based on the size (diameter and/or surface area), material composition, etc. of the pad 302 due to a predictable recess "d 2" created by CMP (or other process) preparation of the surface 108.

In various embodiments, the amount of dishing (e.g., d1, d2, etc.) of metal pads 110 or 302 may be predictable based on the surface preparation technique used (e.g., the chemical combination used, the speed of the polishing equipment, etc.), the materials of dielectric layer 106 and metal pads 110 and 302, the pitch or density of metal pads 110 and 302, and the size (e.g., area or diameter) of metal pads 110 and 302. In an embodiment, based on the recess prediction, and the expected metal expansion of the combination of the TSV114 and the metal pad 110 or 302, the area or diameter of the metal pads 110 and 302 (e.g., for a particular metal thickness) may be selected to avoid delamination of the bonded die 102. For example, larger sized pads 302 may be used over the TSVs 114, and smaller sized pads 110 may be used over the dielectric 106 (to avoid excessive recessing of these pads 110). This technique may result in reduced or eliminated delamination, as well as reliable mechanical coupling of the dielectric 106 to the metal structures (110, 302, 112, and/or 114) on the bonding surface 108, and reliable electrical continuity of the bonded metal structures (110, 302, 112, and/or 114).

In one embodiment, the metal pads 110, 302 may be selectively etched (via acid etching, plasma oxidation, etc.) to provide a desired recess depth (to accommodate predicted metal expansion). In another embodiment, the pads 110, 302 or corresponding TSVs 114 may be selected, formed, or processed to have a non-uniform top surface as an expansion buffer. For example, referring to fig. 7, the top surface of the pad 302 (or in some cases, the TSV 114) may be formed or selectively etched to be rounded, hemispherical, convex, concave, irregular, or otherwise non-planar to allow space for material expansion.

As shown at a of fig. 7, the top surface or bonding surface of the contact pad 302 is selected, formed or treated to have a non-uniform surface. As shown at B, the pads 302 make contact and are bonded after the material expands due to the thermal anneal. However, with sufficient space provided by the non-uniform top surface of the pad 302 for expansion, the material does not exceed the space provided, and thus delamination of the bonded die 102 does not occur.

Additionally or alternatively, as shown in fig. 8, the dielectric 106 around the metal pad 110 or 302 may be formed or shaped to allow space for metal expansion for the pad 110 or 302 (and TSV 114). In one example, a CMP process may be used to shape the surface 108 of the dielectric 106 around the metal pad 302, or in other examples, other processes may be used such that the dielectric 106 around the pad 302 includes a recess 802 or other gap that provides space for metal expansion.

In one embodiment, the dielectric 106 may be recessed (e.g., using CMP) when the bonding surface 108 is prepared. In this embodiment, metal pad 110 or 302 and dielectric 106 may be recessed simultaneously (but at different rates). For example, the process may form an etch 802 in the dielectric 106 around the edge of the metal pad 110 or 302 while recessing the metal pad 110 or 302.

In various embodiments, the pads 110 or 302 and/or the TSVs 114 are composed of copper, copper alloys, or the like. In further embodiments, the material of the pad 110 or 302 and/or the TSV114 may be varied to control the likelihood of metal expansion and delamination. For example, in some embodiments, the pads 110 or 302 and/or the TSVs 114 may be composed of different conductive materials, which may have a lower CTE. In some embodiments, TSV114 may be composed of a different conductive material (with a lower CTE) than contact pad 110 or 302. For example, the TSV114 may be composed of tungsten, an alloy, or the like.

In other embodiments, the volume of the material of the TSV114 may be varied to control the likelihood of metal expansion and delamination. For example, in some embodiments, a TSV114 with a preselected material volume (e.g., a smaller material volume) may be used to control delamination when allowed within design specifications. The pre-selection of the volume of the TSV114 may be based on a predicted material expansion (of the TSV114 and contact pad 110 or 302, where applicable).

In alternative embodiments, the metal contact pad 110 or 302 may be offset or repositioned from the TSV114, rather than positioned directly over the TSV 114. For example, metal pad 110 or 302 may be positioned such that metal pad 110 or 302 is not directly over TSV114 and is coupled to TSV114 through metal trace 112 or the like, if desired. If the contact pad 110 or 302 is offset from the TSV114, a cavity may be created to allow the TSV114 to expand in the z-direction without affecting the bonding interface. The cavity may remain open or may be filled with a material such as a compliant material.

Alternatively, the top surface of the TSV114 may be arranged to be exposed at the bonding surface 108 and to serve as a contact pad. These arrangements may avoid the expansion of the metal pad 110 or 302 in combination with the expansion of the TSV114 and thus minimize or eliminate delamination.

In further embodiments, the TSVs 114 may be formed such that the TSVs 114 extend partially (but not entirely) through the thickness of the substrate 102, terminating below the bonding surface 108. A gap or recess may be provided in the bonding surface 108 above the TSV114 to provide room for the metal of the TSV114 to expand without causing delamination. For example, the gap may be formed by etching the dielectric layer 106. The gap may or may not expose the TSV 114. Based on the volume of the particular metal of the TSV114, the gap may be tuned to, for example, the volume of the TSV114 using a prediction of the expansion of the TSV 114.

Additional embodiments

Fig. 9-13 illustrate examples of backside die 102 processing according to various embodiments. In some implementations, where the dies 102 are stacked and directly bonded without an adhesive, the back side 902 of the dies 102 may receive a different preparation than the top side bonding surface 108 when the back side 902 is prepared for direct bonding. Instead of forming the dielectric layer 106 on the back side 902 of the die 102, the back side 902 may be prepared differently to reduce process steps, reduce manufacturing costs, or for other reasons.

In one implementation, the backside 902 is prepared such that the back end of the TSV114 is exposed to serve as a contact surface for bonding to a conductive pad, interconnect, or other conductive bonding surface. The preparation may include: the base substrate 104 is thinned and selectively etched to expose the TSV114 with the liner/barrier layer 904 intact, one or more layers of insulating material are deposited, and the backside 902 is planarized (e.g., via CMP) to expose the TSV 114. However, in some cases, expansion of the material of the TSV114 during the thermal anneal may cause the insulating material and/or the substrate 104 to deform and rise above the planarized surface.

In one embodiment, as shown in fig. 9-13, one or more layers of material may be deposited on the back side 902 to cover the raised areas so that the new surface may be re-planarized for good dielectric-to-dielectric bonding. Another important function of the multilayer structure is to balance the stress between the front and back sides of the die 102 to minimize die warpage prior to bonding. The balanced die 102 is easier to bond and less prone to creating bond voids. The layer of added material may be planarized and may be otherwise prepared as a bonding surface on the back side 902 of the die 102.

As shown at fig. 9, the TSVs 114 are disposed within the die 102, transverse to the bonding surface 108 of the die 102. After selectively etching the base substrate 104, the TSVs 114 may extend beyond the surface of the base substrate 104. A diffusion barrier and oxide liner 904 surrounds the TSVs 114 to prevent diffusion of the metal (e.g., copper) of the TSVs 114 into the material (e.g., silicon) of the base substrate 104. In one embodiment, as shown at fig. 9, another diffusion barrier layer 906 is deposited on the surface of the backside of the die 102. In one example, diffusion barrier 906 comprises a dielectric such as a nitride.

In various embodiments, one or more inorganic dielectric layers having different residual stress characteristics may then be deposited onto the back side 902 of the die 102 to enable proper exposure of the TSVs 114 and to balance the stress on the device side (front side) of the die 102 to minimize wafer warpage after singulation. For example, a first layer 908 comprising a first low temperature dielectric such as oxide may be deposited over the backside 902 comprising the diffusion layer 906.

In some embodiments, a second layer 910 comprising a second low temperature dielectric, such as a second oxide, may be deposited over the backside 902 comprising the first layer 908. Second oxide layer 910 may have similar or different residual stress characteristics than first layer 908 (e.g., first layer 908 may be compressive and second layer 910 may be tensile, or vice versa, or both layers 908 and 910 may be compressive or tensile, having similar or different values). In various implementations, the first layer 908 and the second layer 910 are composed of similar or identical materials (thickness variation). In other implementations, the first layer 908 and the second layer 910 are composed of different materials. In alternative implementations, additional dielectric layers may also be deposited over the first 908 and second 910 layers.

As shown at fig. 10, the backside 902 (including the one or more stress layers 908 and 910) is planarized (e.g., via CMP) to form a planar, smooth bonding surface for direct bonding. A portion of the second layer 910 may be left on the backside 902 to help mitigate damage such as oxide ring effects. Additionally, the remaining portion of the second layer 910 may assist in warpage control based on the residual stress characteristics of the second layer 910.

In another embodiment, as shown in fig. 11-12, the contact pads 1204 may be coupled to the TSVs 114 on the back side 902 of the die 102. As shown at fig. 11, after depositing a first dielectric layer (e.g., low temperature oxide stress layer 908, which in some implementations also includes a bonding layer), the TSV114 is fully exposed and planarized by a process such as CMP. A second dielectric layer 910 (which may comprise an oxide) may be deposited over the first layer 908 and planarized. No barrier or adhesion layer is required between the two oxide layers (908 and 910). After planarization, the backside 902 is patterned and opened (e.g., etched, etc.) for deposition of the conductive pads. As shown in fig. 11, opening 1102 in oxide layers 908 and 910 may have a diameter that is larger than the diameter of TSV 114.

In one embodiment, the opening 1102 for the contact pad 1204 extends through the second layer 910 and partially (10 to 1000nm) into the first layer 908. As shown at fig. 12, a barrier/adhesion layer 1202 (comprising titanium/titanium nitride, tantalum/tantalum nitride, etc.) may be deposited into the opening 1102 (and may cover the entire surface of the opening 1102). Deposition/plating (e.g., damascene process) of copper (or the like) fills the openings 1102, the openings 1102 are planarized (e.g., via CMP) to remove excess copper, and the resulting contact pads 1204 are recessed to a specified depth. At this point, the surface of the back side 902 is prepared for bonding.

In an alternative embodiment, as shown in fig. 13, a dual damascene process may be used to form contact pads 1204. In this embodiment, after depositing the second dielectric layer 910 (which may comprise an oxide) onto the first layer 908 (without a barrier layer or adhesion layer), the resulting backside 902 surface is patterned twice in a dual damascene process to form the only opening 1302 for the contact pad 1204. First, a small opening having a diameter smaller than the diameter of TSV114 is etched partially through layer 908, and then a large opening (a diameter larger than the diameter of TSV 114) over the small opening is patterned and etched, resulting in a smaller opening extending to TSV114, and a larger opening partially through layer 910. For example, in some cases, design rules specify the presence of a via layer.

The thickness of the second dielectric layer 910 (top layer) and the thickness of the contact pads 1204 may be adjusted to minimize thin die warpage and achieve the desired annealing temperature. In other embodiments, alternative techniques may be used to reduce or eliminate delamination due to expansion of metal features and still be within the scope of the present disclosure.

Fig. 14-16 illustrate example stacked arrangements of the dies 102 (and similar structures) formed with respect to fig. 9-13, with interconnectivity of the front side 108 and the back side 902. For example, at fig. 14, an example "front-to-back" die 102 stacking arrangement is shown. This bonds the front side bonding surface 108 of the first die 102 to the back side 902 bonding surface of the second die 102, including bonding the contact pad 110 or 302 of the first die 102 to the contact pad 1204 of the second die 102. In one example, as discussed above, the contact pads 1204 of the second die 102 penetrate into the second dielectric layer 910 and the first dielectric layer 908 of the second die 102 below the bonding interface 1402.

At fig. 15, an example "back-to-back" die 102 stacking arrangement is shown. This bonds the back side 902 bonding surface of the first die 102 to the back side 902 bonding surface of the second die 102, including bonding contact pads 1204 of the first die 102 to contact pads 1204 of the second die 102. In one example, as discussed above, the contact pads 1204 of the first die 102 and the contact pads 1204 of the second die 102 penetrate into the second dielectric layer 910 and the first dielectric layer 908 of the first die and the second die 102 below the bonding interface 1402.

At fig. 16, an example "front-to-front" die 102 stacking arrangement is shown. This bonds the front-side bonding surface 108 of the first die 102 to the front-side bonding surface 108 of the second die 102, including bonding the contact pad 110 or 302 of the first die 102 to the contact pad 110 or 302 of the second die 102, at the bonding interface 1402. In the example shown, the contact pad 110 or 302 is electrically coupled to the TSV114 of the respective die 102.

In various embodiments, as illustrated at fig. 17, one or more TSVs of the TSVs 114 of a set of stacked dies 102 may be used to conduct heat in addition to or instead of electrical signals. For example, in some cases, it may not be practical or possible to attach a heat sink (or other heat transfer device) to the die 102 in a set of stacked dies 102 to mitigate the heat generated by the die 102. In this case, other techniques may be sought (if desired) to transfer heat.

In embodiments, as shown at fig. 17, various configurations of TSVs (including TSVs 114 that extend partially or fully through the die 102) may be employed to conduct heat away from the die 102 (or away from a heat generating portion of the die 102). The TSVs 114 of one die 102 may be used in conjunction with the TSVs 114 of a second die 102, contact pads 110 and 302, traces 112, etc., to accomplish heat transfer from one die 102 to the other die 102, and so on. For high performance thermal conductivity, the TSVs 114 of the first die 102 may be directly bonded (e.g., DBI) to the TSVs 114, contact pads 110 and 302, traces 112, etc. of the second die 102.

In one implementation, some of the TSV114, contact pads 110 and 302, trace 112, etc. are floating or "dummy" structures, which may be used for heat transfer. These structures may conduct heat from the high power die 102 to another die 102 or substrate (as desired). Dummy contact pads 110 or 302 may be coupled to last via (via last) or intermediate via (via mid) thermal TSVs 114 for thermal conduction.

In an embodiment, diffusion barrier layer 704/oxide liner layer 904 surround TSV114 and may be thermally confined or thermally blocked, and diffusion barrier layer 704 may be replaced by a diffusion barrier/oxide liner of a different material (such as a metal or alloy barrier, etc.) that has some thermal conductivity.

Example procedure

Fig. 18 illustrates a representative process 18000 for preparing various microelectronic components (e.g., such as die 102) for bonding (such as for direct bonding without an adhesive) while reducing or eliminating the possibility of delamination due to metal expansion of embedded structures at the bonding surface. For example, Through Silicon Vias (TSVs) at the bonding surface may cause delamination, especially when coupled to contact pads, because the materials of the TSVs and contact pads may expand during the thermal anneal. The process refers to fig. 1 to 18.

The order in which the processes are described is not intended to be construed as a limitation, and any number of the described process blocks in a process may be combined in any order to implement a process, or an alternative process. Additionally, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. Further, the processes may be implemented in any suitable hardware, software, firmware, or combination thereof, without departing from the scope of the subject matter described herein. In alternative implementations, other techniques may be included in the process in various combinations and still be within the scope of the present disclosure.

In one implementation, a die, wafer, or other substrate ("substrate") is formed using various techniques to include a base substrate and one or more dielectric layers. In this implementation, at block 1802, process 1800 includes: a first through-silicon via (TSV) (e.g., such as TSV 114) is embedded in a first substrate (e.g., such as die 102) having a first bonding surface (e.g., such as bonding surface 108), the first TSV being perpendicular to the first bonding surface.

In this implementation, at block 1804, the process includes: a first metal contact pad (e.g., such as contact pad 302) is formed at the first bonding surface based on a volume of material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV, and the first metal contact pad is electrically coupled to the first TSV. In one embodiment, the first metal contact pad extends partially into the first substrate below the first bonding surface.

At block 1806, the process includes: the first bonding surface is planarized to have a predetermined maximum surface variation for direct bonding and the first metal contact pad is planarized to have a predetermined recess relative to the first bonding surface based on a volume of a material of the first TSV and a Coefficient of Thermal Expansion (CTE) of the material of the first TSV. In one implementation, the process includes: predicting an amount by which the material of the first metal contact pad will expand when heated to a preselected temperature based on the volume of the material of the first metal contact pad and the CTE of the material of the first metal contact pad, and determining the size of the first metal contact pad based on an estimate combined with the above prediction. In one implementation, the process includes: the diameter or surface area of the first metal contact pad is selected.

In one implementation, the process includes: a first metal contact pad is electrically coupled to the first TSV.

In one implementation, the process includes: determining, based on the estimating and predicting, a desired recess for the first metal contact pad relative to the first bonding surface to allow for expansion of the material of the first TSV and the material of the first metal contact pad; and selecting the first metal contact pad to have a perimeter shape that results in a desired depression when the first metal contact pad is planarized.

In another implementation, the process includes: based on the prediction, determining a desired recess of the first metal contact pad relative to the first bonding surface to allow for expansion of the material of the first TSV and the material of the first metal contact pad; and forming a desired recess in the surface of the first metal contact pad.

In another implementation, the process includes: the first metal contact pad is selected to have an oversized diameter, or an oversized surface area, as compared to what would normally be the case for a similar application.

In further implementations, the process includes: predicting an amount of dishing that may occur in a surface of the first metal contact pad as a result of the planarizing.

In another implementation, the process includes: based on the estimation, the material of the first bonding surface is directly recessed or eroded around the first metal contact pad to allow for expansion of the material of the first TSV, as well as the material of the first metal contact pad.

In one implementation, the process includes: delamination of the bonded microelectronic components is reduced or eliminated by offsetting the position of the first metal contact pad relative to the first TSV such that the first metal contact pad is not disposed directly over the first TSV. In another implementation, the process includes: a recess is formed in the first bonding surface over the first TSV to allow for expansion of the material of the first TSV. In another implementation, the process includes: based on the estimation, the volume of the recess in the first engagement surface is tuned (tune).

In one implementation, the process includes: delamination of the bonded microelectronic components is reduced or eliminated by extending the first TSV to the first bonding surface and using a top surface of the first TSV as a contact pad at the first bonding surface.

In various embodiments, some process steps may be modified or eliminated as compared to those described herein.

The techniques, components, and devices described herein are not limited to the illustrations of fig. 1A-15, and may be applied to other designs, types, apparatuses, and configurations, including having other electronic components, without departing from the scope of the present disclosure. In some cases, the techniques described herein may be implemented using additional or alternative components, techniques, sequences, or processes. Moreover, the components and/or techniques may be arranged and/or combined in various combinations while producing similar or substantially the same results.

Conclusion

Although implementations of the present disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing the example devices and techniques.