阅读说明：本技术 基板及封装结构 (Substrate and packaging structure ) 是由 淳于江民 于 2020-03-20 设计创作，主要内容包括：本发明涉及一种基板及封装结构。一种基板,所述基板用于半导体器件的封装,所述基板包括绝缘板和设于所述绝缘板第一表面的至少一个第一导电层图形,一个所述第一导电层图形用于与所述半导体器件的一个器件电极相连接,且通过所述第一导电层图形将其所连接的所述器件电极与半导体器件封装的对应电极连接；当所述第一导电层图形的数量大于等于2时,不同的所述第一导电层图形之间相互分离。基板上第一导电层图形与半导体器件的至少一个器件电极一一对应连接,半导体器件运行过程中产生的热量同时通过第一导电层图形散发出去,降低器件运行过程中的结温,从而提高半导体器件的使用寿命和可靠性。(The invention relates to a substrate and a packaging structure. A substrate is used for packaging a semiconductor device and comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, wherein the first conducting layer pattern is used for being connected with one device electrode of the semiconductor device, and the device electrode connected with the first conducting layer pattern is connected with a corresponding electrode of the semiconductor device package through the first conducting layer pattern; when the number of the first conductive layer patterns is greater than or equal to 2, different first conductive layer patterns are separated from each other. The first conducting layer patterns on the substrate are connected with at least one device electrode of the semiconductor device in a one-to-one correspondence mode, heat generated in the operation process of the semiconductor device is dissipated through the first conducting layer patterns, junction temperature in the operation process of the device is reduced, and therefore the service life of the semiconductor device is prolonged, and reliability of the semiconductor device is improved.)

1. A substrate for packaging a semiconductor device, the substrate comprising an insulating plate and at least one first conductive layer pattern disposed on a first surface of the insulating plate, one first conductive layer pattern being for connection to a device electrode of the semiconductor device and the device electrode connected thereto being connected to a corresponding electrode of a semiconductor device package via the first conductive layer pattern; when the number of the first conductive layer patterns is greater than or equal to 2, different first conductive layer patterns are separated from each other.

2. The substrate according to claim 1, wherein the first conductive layer pattern comprises at least one of a control terminal pattern for connecting a control electrode of the semiconductor device, an input terminal pattern for connecting an input electrode of the semiconductor device, and an output terminal pattern for connecting an output electrode of the semiconductor device.

3. The substrate of claim 1, wherein the first conductive layer pattern connects the connected device electrode and a corresponding electrode of the semiconductor device package through an electrical connection structure.

4. The substrate of claim 3, wherein the electrical connection structure is a metal connection pillar or a solder ball or a solder.

5. The substrate of claim 1, wherein the insulating plate defines at least one through hole extending through the insulating plate, the through hole extending to or through the first conductive layer pattern, and the through hole is filled with a conductive material or a heat conductive material.

6. The substrate according to claim 1, further comprising at least one second conductive layer pattern provided on a second surface of the insulating plate opposite to the first surface of the insulating plate, wherein when the number of the second conductive layer patterns is 2 or more, different second conductive layer patterns are separated from each other; and a through hole penetrating through the insulating plate is arranged between the first conducting layer pattern and the second conducting layer pattern, and a conducting material or a conducting material is filled in the through hole.

7. A package structure, comprising:

the semiconductor device comprises a first surface and a second surface which are opposite, wherein the first surface is provided with at least one device electrode, and the second surface is provided with at least one device electrode;

the first substrate comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, and the first conducting layer pattern is used for being connected with one device electrode arranged on the first surface of the semiconductor device;

the first electrical connection structure is arranged between the first surface of the semiconductor device and the first conducting layer pattern and is used for correspondingly connecting the device electrodes arranged on the first surface of the semiconductor device with the first conducting layer pattern one by one;

a second electrical connection structure for connecting the first conductive layer pattern to a corresponding electrode of a device package;

the third electrical connection structure is arranged on the second surface of the semiconductor device and used for connecting the device electrode arranged on the second surface of the semiconductor device to the corresponding electrode of the device package, and the thickness of the second electrical connection structure is larger than the sum of the thicknesses of the first electrical connection structure and the third electrical connection structure;

when the number of the first conductive layer patterns is 2 or more, different first conductive layer patterns are separated from each other.

8. The package structure of claim 7, wherein the first conductive layer pattern comprises at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, the control electrode of the first surface of the semiconductor device is connected to the control terminal pattern, and the output electrode of the first surface of the semiconductor device is connected to the output terminal pattern; the control terminal pattern and the output terminal pattern are connected to a control terminal and an output terminal of a semiconductor device package, respectively.

9. The package structure of claim 8, wherein the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the input electrode of the second surface of the semiconductor device is connected to the input terminal of the device package through the third electrical connection structure;

or the packaging structure further comprises a second substrate positioned between the third electrical connection structure and the corresponding electrode of the device package, the second substrate comprises a second insulating plate and at least one second conducting layer pattern arranged on the second surface of the second insulating plate, and when the number of the second conducting layer patterns is greater than or equal to 2, different second conducting layer patterns are separated from each other; the second surface of the second insulating plate is a surface facing the semiconductor device, an input electrode on the second surface of the semiconductor device is connected with the second conductive layer pattern through the third electrical connection structure, the second substrate further comprises an input end pattern arranged on the first surface of the second insulating plate opposite to the second surface of the second insulating plate, and the second conductive layer pattern and the input end pattern are connected through a heat conduction material or a conductive material in a through hole penetrating through the second insulating plate; the package structure further includes a fourth electrical connection structure disposed on the first surface of the second insulating plate for connecting the input end pattern with an input end of a device package.

10. The package structure of claim 7, wherein the first conductive layer pattern comprises at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, wherein the input electrode of the first surface of the semiconductor device is connected to the input terminal pattern of the input terminal pattern, and wherein the input terminal pattern is connected to the input terminal of the device package.

11. The package structure of claim 10, wherein the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the control electrode and the output electrode of the second surface of the semiconductor device are connected to the control terminal and the output terminal of the device package through the third electrical connection structure, respectively;

or the package structure further comprises a fifth substrate located between the third electrical connection structure and the control electrode and the output electrode of the device package, the fifth substrate comprises a fifth insulating plate and at least one second conductive layer pattern arranged on the second surface of the fifth insulating plate, when the number of the second conductive layer patterns is greater than or equal to 2, different second conductive layer patterns are separated from each other, the second surface of the fifth insulating plate faces the semiconductor device, the control electrode and the output electrode on the second surface of the semiconductor device are respectively connected with the second conductive layer patterns through the third electrical connection structure, the fifth substrate further comprises a control end pattern and an output end pattern which are arranged on the first surface of the fifth insulating plate opposite to the second surface of the fifth insulating plate, and the second conductive layer patterns are respectively connected with the control end pattern and the output end pattern through a heat conduction material or a conductive material penetrating through a through hole of the fifth insulating plate; the packaging structure further comprises a fifth electrical connection structure arranged on the first surface of the fifth insulating plate and used for connecting the control end graph and the output end graph with a control end and an output end of a device package respectively; the second conductive layer pattern is in a shape designed for heat dissipation and connection.

12. The package structure of any one of claims 7-11, wherein the second electrical connection structure comprises a metal connection pillar or a solder ball or a solder.

13. The package structure according to any one of claims 7 to 11, wherein the first substrate further comprises at least one second conductive layer pattern provided on a second surface of the insulating sheet opposite to the first surface of the insulating sheet, and when the number of the second conductive layer patterns is 2 or more, different second conductive layer patterns are separated from each other; a through hole penetrating through the insulating plate is arranged between the second conducting layer pattern and the first conducting layer pattern, the second conducting layer pattern is a heat dissipation layer of the first conducting layer pattern, and the second conducting layer pattern is in a shape designed according to heat dissipation and connection.

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a substrate and a package structure.

Background

With conventional surface mount device packages, even with the addition of a heat sink, heat generated during device operation is primarily dissipated through a metal frame located at the bottom of the device and then through a Printed Circuit Board (PCB). The heat dissipation efficiency is low, the junction temperature in the operation process of the device is high, and the service life and the reliability of the device are influenced.

Disclosure of Invention

In view of the above, it is necessary to provide a new substrate and a new package structure for solving the above problems.

A substrate is used for packaging a semiconductor device and comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, wherein the first conducting layer pattern is used for being connected with one device electrode of the semiconductor device, and the device electrode connected with the first conducting layer pattern is connected with a corresponding electrode of the semiconductor device package through the first conducting layer pattern; when the number of the first conductive layer patterns is greater than or equal to 2, different first conductive layer patterns are separated from each other.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern for connecting a control electrode of the semiconductor device, an input terminal pattern for connecting an input electrode of the semiconductor device, and an output terminal pattern for connecting an output electrode of the semiconductor device.

In one embodiment, the first conductive layer pattern connects the connected device electrode with a corresponding electrode of the device package through an electrical connection structure.

In one embodiment, the insulating plate is provided with at least one through hole penetrating through the insulating plate, the through hole extends to or penetrates through the first conductive layer pattern, and the through hole is a heat dissipation hole of the first conductive layer pattern.

In one embodiment, the substrate further includes at least one second conductive layer pattern disposed on a second surface of the insulating plate opposite to the first surface of the insulating plate, and when the number of the second conductive layer patterns is greater than or equal to 2, different second conductive layer patterns are separated from each other; a through hole penetrating through the insulating plate is arranged between the first conducting layer graph and the second conducting layer graph, the second conducting layer graph is a heat dissipation layer of the first conducting layer graph, and the second conducting layer graph is in a shape designed according to heat dissipation and connection.

In one embodiment, the electrical connection structure is a metal connection pillar, or the electrical connection structure is a solder ball, or the electrical connection structure is a solder.

The substrate is used for packaging a semiconductor device, and comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, wherein one first conducting layer pattern is used for being connected with one device electrode of the semiconductor device, and the connected device electrode is connected with a corresponding electrode of the semiconductor device package by the first conducting layer pattern; the first conducting layer patterns are in shapes designed according to heat dissipation and connection, and when the number of the first conducting layer patterns is larger than or equal to 2, different first conducting layer patterns are separated from each other. The first conducting layer patterns designed according to heat dissipation and connection on the substrate are connected with at least one device electrode of the semiconductor device in a one-to-one correspondence mode, heat generated in the operation process of the semiconductor device is dissipated through the first conducting layer patterns, junction temperature in the operation process of the device is reduced, and therefore the service life and reliability of the semiconductor device are prolonged.

A package structure, comprising:

the semiconductor device comprises a first surface and a second surface which are opposite, wherein the first surface is provided with at least one device electrode, and the second surface is provided with at least one device electrode;

the first substrate comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, and the first conducting layer pattern is used for being connected with one device electrode arranged on the first surface of the semiconductor device; when the number of the first conducting layer patterns is more than or equal to 2, different first conducting layer patterns are mutually separated;

the first electrical connection structure is arranged between the first surface of the semiconductor device and the first conducting layer pattern and is used for correspondingly connecting the device electrodes arranged on the first surface of the semiconductor device with the first conducting layer pattern one by one;

a second electrical connection structure for connecting the first conductive layer pattern to a corresponding electrode of a device package;

and the third electrical connection structure is arranged on the second surface of the semiconductor device and used for connecting the device electrode arranged on the second surface of the semiconductor device to the corresponding electrode of the device package, and the thickness of the second electrical connection structure is greater than the sum of the thicknesses of the first electrical connection structure and the third electrical connection structure.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, the control electrode of the first surface of the semiconductor device is connected to the control terminal pattern of the control terminal pattern, and the output electrode of the first surface of the semiconductor device is connected to the output terminal pattern of the output terminal pattern; the control end graph and the output end graph are respectively connected with a control end and an output end of the device package.

In one embodiment, the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the input electrode of the second surface of the semiconductor device is connected with the input end of the device package through the third electrical connection structure;

or the packaging structure further comprises a second substrate positioned between the third electrical connection structure and the corresponding electrode of the device package, the second substrate comprises a second insulating plate and at least one second conducting layer pattern arranged on the second surface of the second insulating plate, and when the number of the second conducting layer patterns is greater than or equal to 2, different second conducting layer patterns are separated from each other; the second surface of the second insulating plate is a surface facing the semiconductor device, an input electrode on the second surface of the semiconductor device is connected with the second conductive layer pattern through the third electrical connection structure, the second substrate further comprises an input end pattern arranged on the first surface of the second insulating plate opposite to the second surface of the second insulating plate, and the second conductive layer pattern and the input end pattern are connected through a heat conduction material or a conductive material in a through hole penetrating through the second insulating plate; the packaging structure further comprises a fourth electrical connection structure arranged on the first surface of the second insulating plate and used for connecting the input end graph with the input end of the device package; the second conductive layer pattern is in a shape designed for heat dissipation and connection.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, the input electrode of the first surface of the semiconductor device is connected to the input terminal pattern of the input terminal pattern, and the input terminal pattern is connected to the input terminal of the device package.

In one embodiment, the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the control electrode and the output electrode of the second surface of the semiconductor device are respectively connected with the control terminal and the output terminal of the device package through the third electrical connection structure;

or the package structure further comprises a fifth substrate between the third electrical connection structure and the control electrode and the output electrode of the device package, the fifth substrate comprises a fifth insulating plate and at least one second conducting layer pattern arranged on the second surface of the fifth insulating plate, when the number of the second conductive layer patterns is 2 or more, different second conductive layer patterns are separated from each other, the second surface of the fifth insulating plate is a surface facing the semiconductor device, the control electrode and the output electrode on the second surface of the semiconductor device are respectively connected with the second conductive layer pattern through the third electrical connection structure, the fifth substrate further comprises a control end graph, an output end graph and a second conducting layer graph which are arranged on the first surface of the fifth insulating plate opposite to the second surface of the fifth insulating plate, and the control end graph, the output end graph and the second conducting layer graph are respectively connected with the control end graph and the output end graph through heat conducting materials or conducting materials in through holes penetrating through the fifth insulating plate; the packaging structure further comprises a fifth electrical connection structure arranged on the first surface of the fifth insulating plate and used for connecting the control end graph and the output end graph with a control end and an output end of a device package respectively; the second conductive layer pattern is in a shape designed for heat dissipation and connection.

In one embodiment, the first electrical connection structure is a metal connection pillar or a solder ball.

In one embodiment, the second electrical connection structure is a metal connection pillar or a solder ball or a solder.

In one embodiment, the third electrical connection structure is a metal connection pillar or a solder ball or a solder.

In one embodiment, the fourth electrical connection structure is a metal connection pillar or a solder ball or a solder.

In one embodiment, the first substrate further includes at least one second conductive layer pattern disposed on a second surface of the insulating plate opposite to the first surface of the insulating plate, and when the number of the second conductive layer patterns is greater than or equal to 2, different second conductive layer patterns are separated from each other; a through hole penetrating through the insulating plate is arranged between the second conducting layer pattern and the first conducting layer pattern, the second conducting layer pattern is a heat dissipation layer of the first conducting layer pattern, and the second conducting layer pattern is in a shape designed according to heat dissipation and connection.

In one embodiment, a through hole penetrating through the insulating plate is formed between the second conductive layer pattern and the first conductive layer pattern, and no filling material is filled in the through hole.

In one embodiment, a through hole penetrating through the insulating plate is formed between the second conductive layer pattern and the first conductive layer pattern, and the through hole is filled with an insulating material.

A package structure, the package structure comprising: the semiconductor device comprises a first surface and a second surface which are opposite, wherein the first surface is provided with at least one device electrode, the second surface is provided with at least one device electrode, the first substrate comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, and the first conducting layer pattern is used for being connected with one device electrode arranged on the first surface of the semiconductor device; the first electrical connection structure is arranged between the first surface of the semiconductor device and the first conducting layer pattern and is used for correspondingly connecting the device electrodes arranged on the first surface of the semiconductor device with the first conducting layer pattern one by one; a second electrical connection structure for connecting the first conductive layer pattern to a corresponding electrode of a device package; the third electrical connection structure is arranged on the second surface of the semiconductor device and used for connecting the device electrode arranged on the second surface of the semiconductor device to the corresponding electrode of the device package, and the thickness of the second electrical connection structure is larger than the sum of the thicknesses of the first electrical connection structure and the third electrical connection structure; the first conducting layer patterns are in shapes designed according to heat dissipation and connection, and when the number of the first conducting layer patterns is larger than or equal to 2, different first conducting layer patterns are separated from each other. The first substrate comprises an insulating plate and at least one first conducting layer pattern which is arranged on the first surface of the insulating plate and designed according to heat dissipation and connection, device electrodes arranged on the first surface of the semiconductor device are connected with the first conducting layer pattern on the first surface of the insulating plate in a one-to-one correspondence mode, and device electrodes arranged on the second surface of the semiconductor device are connected with corresponding electrodes of a device package, so that heat generated in the operation process of the semiconductor device is dissipated through the first conducting layer pattern connected with the first surface of the semiconductor device and the corresponding electrodes of the device package connected with the second surface of the semiconductor device at the same time, junction temperature in the operation process of the device is reduced, and the service life and reliability of the semiconductor device are prolonged.

Drawings

FIG. 1 is a front view of a substrate according to one embodiment;

FIG. 2a is a schematic diagram of a first conductive layer pattern in an embodiment;

FIG. 2b is a schematic diagram of a first conductive layer pattern in another embodiment;

FIG. 3 is a diagram of a package structure according to a first embodiment;

fig. 4 is a right side view of the package structure shown in fig. 3 (with the semiconductor device 304, the first electrical connection structure 306, and the first electrical connection structure 308 omitted);

FIG. 5 is a diagram of a package structure in a second embodiment;

FIG. 6 is a diagram of a package structure in a third embodiment;

FIG. 7 is a diagram of a package structure in a fourth embodiment;

FIG. 8 is a diagram of a package structure in a fifth embodiment;

FIG. 9 is a diagram of a package structure in a sixth embodiment;

FIG. 10 is a diagram of a package structure in a seventh embodiment;

FIG. 11 is a diagram illustrating a package structure according to an eighth embodiment;

fig. 12 is a schematic diagram of a package structure in the ninth embodiment.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

As shown in fig. 1, in an embodiment, a substrate 100 for packaging a semiconductor device is provided, the substrate comprising an insulating board 102 and at least one first conductive layer pattern 104 disposed on a first surface of the insulating board, one first conductive layer pattern 104 for connecting to one device electrode of the semiconductor device, and the first conductive layer pattern 104 connecting the connected device electrode to a corresponding electrode of the semiconductor device package; the first conductive layer patterns 104 are in a shape designed for heat dissipation and connection, and when the number of the first conductive layer patterns is 2 or more, different first conductive layer patterns are separated from each other.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern for connecting a control electrode of the semiconductor device, an input terminal pattern for connecting an input electrode of the semiconductor device, and an output terminal pattern for connecting an output electrode of the semiconductor device.

As shown in fig. 2a, in one embodiment, the first conductive layer pattern includes a control terminal pattern 202 and an output terminal pattern 204.

In one embodiment, the first conductive layer pattern includes an input terminal pattern 206, as shown in fig. 2 b.

In one embodiment, the insulating plate is provided with at least one through hole penetrating through the insulating plate, the through hole extends to or penetrates through the first conducting layer pattern, and the through hole is a heat dissipation hole of the first conducting layer pattern.

In one embodiment, the insulating plate is provided with at least one through hole penetrating through the insulating plate, the through hole extends to or penetrates through the first conductive layer pattern, and the through hole is filled with a conductive material, such as metal materials of gold, copper, aluminum and the like.

As shown in fig. 1, in one embodiment, the substrate 100 further includes at least one second conductive layer pattern 106 disposed on a second surface of the insulating plate opposite to the first surface of the insulating plate, and when the number of the second conductive layer patterns 106 is 2 or more, different second conductive layer patterns 106 are separated from each other; a through hole 108 penetrating through the insulating board is provided between the first conductive layer pattern 104 and the second conductive layer pattern 106, the second conductive layer pattern 106 is a heat dissipation layer of the first conductive layer pattern 108, and the second conductive layer pattern 106 is in a shape designed for heat dissipation and connection. In one embodiment, the vias 108 are devoid of filler material. In another embodiment, the vias 108 are filled with a thermally conductive material.

In one embodiment, at least one of the second conductive layer patterns and the first conductive layer patterns has the same shape.

In one embodiment, the shapes of the patterns in the second conductive layer pattern and the first conductive layer pattern are different from each other.

In one embodiment, the first conductive layer pattern connects the connected device electrode and a corresponding electrode of the semiconductor device package through an electrical connection structure.

In one embodiment, the electrical connection structure is a metal connection post or the electrical connection structure is a solder ball or the electrical connection structure is a solder. In one embodiment, the metal connecting struts are made of the same metal material, and in other embodiments, the metal connecting struts are made of different metal materials which are connected into a whole through connecting materials. The height of the electrical connection structure is adjustable, which on the one hand improves the processability and on the other hand provides sufficient space for integrating various functions, such as electrical currents, temperature sensors, etc.

In one embodiment, the first conductive layer pattern is connected to the electrical connection structure by solder.

In one embodiment, the first conductive layer pattern and/or the first conductive layer pattern is shaped according to a heat dissipation, electrical isolation, and connection design.

The substrate is used for packaging a semiconductor device, and comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, wherein one first conducting layer pattern is used for being connected with one device electrode of the semiconductor device, and the connected device electrode is connected with a corresponding electrode of the semiconductor device package by the first conducting layer pattern; the first conducting layer patterns are in shapes designed according to heat dissipation and connection, and when the number of the first conducting layer patterns is larger than or equal to 2, different first conducting layer patterns are separated from each other. The first conducting layer patterns designed according to heat dissipation and connection on the substrate are connected with at least one device electrode of the semiconductor device in a one-to-one correspondence mode, heat generated in the operation process of the semiconductor device is dissipated through the first conducting layer patterns, junction temperature in the operation process of the device is reduced, and therefore the service life and reliability of the semiconductor device are prolonged.

In one embodiment, there is provided a package structure, including:

the semiconductor device comprises a first surface and a second surface which are opposite, wherein the first surface is provided with at least one device electrode, and the second surface is provided with at least one device electrode.

The first substrate comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, when the number of the first conducting layer patterns is more than or equal to 2, different first conducting layer patterns are separated from each other, one first conducting layer pattern is used for being connected with one device electrode arranged on the first surface of the semiconductor device, and the first conducting layer patterns are in shapes designed according to heat dissipation and connection.

In one embodiment, the first substrate further includes at least one second conductive layer pattern disposed on a second surface of the insulating plate opposite to the first surface of the insulating plate, and when the number of the second conductive layer patterns is greater than or equal to 2, different second conductive layer patterns are separated from each other; a through hole penetrating through the insulating plate is arranged between the second conducting layer pattern and the first conducting layer pattern, the second conducting layer pattern is a heat dissipation layer of the first conducting layer pattern, and the second conducting layer pattern is in a shape designed according to heat dissipation and connection. In one embodiment, the through-holes are devoid of filler material. In another embodiment, the through hole is filled with an insulating material or a conductive material or a heat conductive material.

In one embodiment, at least one of the second conductive layer patterns and the first conductive layer patterns has the same shape.

In one embodiment, the shapes of the patterns in the second conductive layer pattern and the first conductive layer pattern are different from each other.

The packaging structure further comprises a first electrical connection structure, wherein the first electrical connection structure is arranged between the first surface of the semiconductor device and the first conducting layer pattern and used for connecting the device electrode arranged on the first surface of the semiconductor device and the first conducting layer pattern in a one-to-one correspondence manner.

In one embodiment, the first electrical connection structure comprises at least one of a solder ball, a metal connection line, and a solder.

In one embodiment, the first electrical connection structure is a metal connection post. In one embodiment, the metal connecting struts are made of the same metal material, and in other embodiments, the metal connecting struts are made of different metal materials which are connected into a whole through connecting materials.

The package structure further includes a second electrical connection structure for connecting the first conductive layer pattern to a corresponding electrode of a device package.

In one embodiment, the second electrical connection structure comprises a metal connection post or a solder ball or a solder. For thinner semiconductor devices, solder can be directly used as the second electrical connection structure; for thicker semiconductor devices, metal connection pillars may be provided as the second electrical connection structures. In one embodiment, the metal connecting struts are made of the same metal material, and in other embodiments, the metal connecting struts are made of different metal materials which are connected into a whole through connecting materials.

The packaging structure further comprises a third electrical connection structure arranged on the second surface of the semiconductor device and used for connecting the device electrode arranged on the second surface of the semiconductor device to the corresponding electrode of the device package, and the thickness of the second electrical connection structure is larger than the sum of the thicknesses of the first electrical connection structure and the third electrical connection structure.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, the control electrode of the first surface of the semiconductor device is connected to the control terminal pattern X of the control terminal pattern, and the output electrode of the first surface of the semiconductor device is connected to the output terminal pattern Y of the output terminal pattern; and the control end graph X and the output end graph Y are respectively connected with a control end and an output end of the device package.

In one embodiment, the semiconductor device is a Die (Die), such as a MOSFET Die. The input electrode of the semiconductor device is a drain, the output electrode is a source, and the control electrode is a gate.

In one embodiment, the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the input electrode of the second surface of the semiconductor device and the input terminal of the device package are connected through the third electrical connection structure. In one embodiment, the metal connecting struts are made of the same metal material, and in other embodiments, the metal connecting struts are made of different metal materials which are connected into a whole through connecting materials.

In one embodiment, the package structure further includes a second substrate positioned between the third electrical connection structure and a corresponding electrode of the device package, the second substrate includes a second insulating plate and at least one second conductive layer pattern provided on a second surface of the second insulating plate, different second conductive layer patterns are separated from each other when the number of the second conductive layer patterns is 2 or more, the second surface of the second insulating plate is a surface facing the semiconductor device, the second conductive layer pattern includes a second conductive layer pattern Z, an input electrode of the second surface of the semiconductor device is connected to the second conductive layer pattern Z through the third electrical connection structure, the second substrate further includes an input terminal pattern Z 'provided on the first surface of the second insulating plate opposite to the second surface of the second insulating plate, the second conductive layer pattern Z and the input terminal pattern Z' pass through holes penetrating the second insulating plate A thermally or electrically conductive material connection; the packaging structure further comprises a fourth electrical connection structure arranged on the first surface of the second insulating plate, and the fourth electrical connection structure is used for connecting the input end graph Z' with the input end of the device package; the second conductive layer pattern is in a shape designed for heat dissipation and connection.

In one embodiment, the fourth electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire or a metal connection post. In other embodiments, the fourth electrical connection structure is another structure that can realize the electrical connection between the input terminal pattern and the input terminal. In one embodiment, the metal connecting struts are made of the same metal material, and in other embodiments, the metal connecting struts are made of different metal materials which are connected into a whole through connecting materials. The height of the electrical connection structure is adjustable, which on the one hand improves the processability and on the other hand provides sufficient space for integrating various functions, such as electrical currents, temperature sensors, etc.

As shown in fig. 3, 4, 5, and 6, the first conductive layer pattern 302 at least includes a control terminal pattern and an output terminal pattern, and the control electrode of the first surface of the semiconductor device 304 and the control terminal pattern X of the control terminal pattern and the output electrode of the first surface of the semiconductor device 304 and the output terminal pattern Y of the output terminal pattern are respectively connected by different first electrical connection structures 306; the control terminal pattern X and the control terminal of the device package, and the output terminal pattern Y and the output terminal of the device package are connected through different second electrical connection structures 310, respectively.

In one embodiment, as shown in fig. 3, the third electrical connection structure 316 is a solder ball or solder or metal connection line, and the input electrode of the second surface of the semiconductor device is connected to the input terminal of the device package through the solder ball or solder or metal connection line 316.

As shown in fig. 4, which is a side view in the direction of an arrow in fig. 3, the second electrical connection structure connecting the control terminal pattern X with the control terminal of the device package and the second electrical connection structure connecting the output terminal pattern Y with the output terminal of the device package are different second electrical connection structures.

As shown in fig. 5, in one embodiment, the third electrical connection structure is a metal frame 318, and the input electrode on the second surface of the semiconductor device and the input terminal of the device package are connected through the metal frame 318. In one embodiment, the metal frame 318 is a copper leadframe.

As shown in fig. 6, in one embodiment, the package structure further includes a second substrate 404 positioned between the third electrical connection structure 402 and a corresponding electrode of the device package, the second substrate 404 includes a second insulating plate 406 and at least one second conductive layer pattern 408 provided on a second surface of the second insulating plate, different second conductive layer patterns 408 are separated from each other when the number of the second conductive layer patterns 408 is 2 or more, the second surface of the second insulating plate is a surface facing the semiconductor device 304, the second conductive layer pattern 408 includes a second conductive layer pattern Z, an input electrode of the second surface of the semiconductor device is connected to the second conductive layer pattern Z through the third electrical connection structure 402, the second substrate 404 further includes an input terminal pattern Z' provided on a first surface of the second insulating plate opposite to the second surface of the second insulating plate, that is, an input terminal pattern of the first conductive layer pattern 412 on the first surface of the second insulating plate, the second conductive layer pattern Z and the input terminal pattern Z' are connected by a conductive material or a conductive material in the through hole 410 penetrating the second insulating plate 406; the package structure further comprises a fourth electrical connection structure (not shown in fig. 6) provided on the first surface of the second insulating plate 406 for connecting the input pattern Z' with the input of the device package; the second conductive layer pattern 408 is shaped according to a heat dissipation and connection design.

As shown in fig. 7, the first conductive layer pattern 502 includes at least a control terminal pattern and an output terminal pattern, the package structure further comprises a third substrate 512 positioned between the third electrical connection structure 510 and a corresponding electrode of the device package, the third substrate 512 comprising a third insulating plate 514, at least one second conductive layer pattern 516 provided on a second surface of the third insulating plate 514, and a control terminal pattern F, an output terminal pattern G, an input terminal pattern H provided on a first surface of the third insulating plate opposite to the second surface of the third insulating plate, when the number of the second conductive layer patterns 516 is 2 or more, different second conductive layer patterns 516 are separated from each other, the second surface of the third insulating plate is a surface facing the semiconductor device 504, and the second conductive layer pattern 516 includes a second conductive layer pattern F ', a second conductive layer pattern G ', and a second conductive layer pattern H '; the control electrode on the first surface of the semiconductor device 504 is connected with a control terminal pattern X 'in the control terminal patterns through a first electrical connection structure 506, and the output electrode on the first surface of the semiconductor device 504 is connected with an output terminal pattern Y' in the output terminal patterns through a first electrical connection structure 506; the control terminal pattern X 'and the output terminal pattern Y' are respectively connected to a second conductive layer pattern F 'and a second conductive layer pattern G' in the second conductive layer pattern 516, the input electrode on the second surface of the semiconductor device is connected to the second conductive layer pattern H 'through a third electrical connection structure 510, and the second conductive layer pattern F', the second conductive layer pattern G 'and the second conductive layer pattern H' are respectively connected to the control terminal pattern F, the output terminal pattern G and the input terminal pattern H through a heat conductive material or a conductive material in a through hole penetrating through the third insulating plate 514; the control end graph F, the output end graph G and the input end graph H are respectively connected with a control end, an output end and an input end of the device package through solder balls or metal frames or solder balls or metal connecting lines; the second conductive layer pattern 516 is shaped according to a heat dissipation and connection design.

As shown in fig. 8, the first conductive layer patterns 602 at least include a control terminal pattern and an output terminal pattern, the package structure further includes a fourth substrate 612 disposed between the third electrical connection structure 610 and the corresponding electrode of the device package, the fourth substrate 612 includes a fourth insulating board 614 and at least one first conductive layer pattern 616 disposed on a first surface of the fourth insulating board, when the number of the first conductive layer patterns 606 is greater than or equal to 2, different first conductive layer patterns 606 are separated from each other, the first conductive layer patterns 616 include a control terminal pattern I, an output terminal pattern J and an input terminal pattern K, the first surface of the fourth insulating board is a surface connected to the corresponding electrode of the device package, the control electrode on the first surface of the semiconductor device 604 is connected to the control terminal pattern X2 in the control terminal pattern through the first electrical connection structure 606, and the output electrode on the first surface of the semiconductor device 604 is connected to the output terminal pattern Y2 in the output terminal pattern through the first electrical connection structure 606 Connecting; the control terminal pattern X2 and the output terminal pattern Y2 are connected to the control terminal pattern I and the output terminal pattern J of the first conductive layer pattern 616, respectively, and the input electrode of the second surface of the semiconductor device is connected to the input terminal pattern K through the third electrical connection structure 610; and the control end graph I, the output end graph J and the input end graph K are respectively connected with the control end, the output end and the input end of the device package through a fourth electrical connection structure.

In one embodiment, the first conductive layer pattern includes at least one of a control terminal pattern, an input terminal pattern, and an output terminal pattern, the input electrode of the first surface of the semiconductor device is connected to an input terminal pattern M of the input terminal pattern, and the input terminal pattern M is connected to an input terminal of the device package.

In one embodiment, the third electrical connection structure comprises a solder ball or a metal frame or a solder or a metal wire, and the control electrode and the output electrode of the second surface of the semiconductor device are respectively connected with the control terminal and the output terminal of the device package through the third electrical connection structure.

In one embodiment, the package structure further includes a fifth substrate located between the third electrical connection structure and the control electrode and the output electrode of the device package, the fifth substrate includes a fifth insulating plate and at least one second conductive layer pattern disposed on a second surface of the fifth insulating plate, when the number of the second conductive layer patterns is greater than or equal to 2, different second conductive layer patterns are separated from each other, the second surface of the fifth insulating plate is a surface facing the semiconductor device, the second conductive layer patterns include a second conductive layer pattern L1 ', a second conductive layer pattern L2', the control electrode and the output electrode of the second surface of the semiconductor device are respectively connected to the second conductive layer pattern L1 'and the second conductive layer pattern L2' through the third electrical connection structure, and the fifth substrate further includes a control terminal pattern L1, a control terminal pattern L1 ', a control terminal pattern L2' disposed on a first surface of the fifth insulating plate opposite to the second surface of the fifth insulating plate, An output terminal pattern L2, the second conductive layer pattern L1 'and the second conductive layer pattern L2' being connected to the control terminal pattern L1 and the output terminal pattern L2, respectively, through the conductive material in the through-hole penetrating the fifth insulating plate; the package structure further includes a fifth electrical connection structure disposed on the first surface of the fifth insulating plate, and configured to connect the control terminal pattern L1 and the output terminal pattern L2 to a control terminal and an output terminal of the device package, respectively; the second conductive layer pattern is in a shape designed for heat dissipation and connection.

As shown in fig. 9 and 10, the first conductive layer pattern 702 includes at least an input terminal pattern, the input electrode of the first surface of the semiconductor device 704 is connected to the input terminal pattern M1 of the input terminal pattern through the first electrical connection structure 706, and the input terminal pattern M1 is connected to the input terminal of the device package through the second electrical connection structure 708.

As shown in fig. 9, in one embodiment, the control electrodes on the second surface of the semiconductor device 704 are connected to the control terminals of the device package by solder balls or solder or metal connecting lines 710, and the output electrodes on the second surface of the semiconductor device are connected to the output terminals of the device package by solder balls or solder or metal connecting lines 710.

As shown in fig. 10, in an embodiment, the package structure further includes a fifth substrate 804 located between the third electrical connection structure and a corresponding electrode of the device package, the fifth substrate 804 includes a fifth insulating plate 806, at least one second conductive layer pattern 808 disposed on a second surface of the fifth insulating plate, and a first conductive layer pattern 812 disposed on a first surface of the fifth insulating plate opposite to the second surface of the fifth insulating plate, when the number of the second conductive layer patterns 808 is greater than or equal to 2, different second conductive layer patterns 808 are separated from each other, the first conductive layer pattern 812 includes a control terminal pattern L1 and an output terminal pattern L2, the second surface of the fifth insulating plate is a surface facing the semiconductor device 704, and the second conductive layer patterns 808 includes a second conductive layer pattern L1 'and a second conductive layer pattern L2', the control electrode and the output electrode of the second surface of the semiconductor device are respectively connected to the second conductive layer pattern L2 through different third electrical connection structures 802 The layer pattern L1 'and the second conductive layer pattern L2', the second conductive layer pattern L1 'and the second conductive layer pattern L2' are respectively connected to the control terminal pattern L1 and the output terminal pattern L2 through conductive materials in through holes penetrating through the fifth insulating plate 806, the package structure further includes a fifth electrical connection structure disposed on the first surface of the fifth insulating plate, and the control terminal pattern L1 and the output terminal pattern L2 are respectively connected to the control terminal and the output terminal of the device package through the fifth electrical connection structure; the first conductive layer pattern 812 and the second conductive layer pattern 808 are shaped according to a heat dissipation and connection design. In one embodiment, the fifth electrical connection structure is a solder ball or a metal frame or a solder or a metal connection line.

In one embodiment, the first substrate may be a metal substrate, and the input electrode on the first surface of the semiconductor device 704 is connected to the metal substrate through the first electrical connection structure 706.

As shown in fig. 11, the first conductive layer pattern 902 includes at least an input terminal pattern, the package structure further includes a sixth substrate 904 disposed between the third electrical connection structure and a corresponding electrode of the device package, the sixth substrate 904 includes a sixth insulating plate 906, at least one second conductive layer pattern 908 disposed on a second surface of the sixth insulating plate, and a first conductive layer pattern 910 disposed on a first surface of the sixth insulating plate opposite to the second surface of the sixth insulating plate, when the number of the second conductive layer patterns 908 is 2 or more, different second conductive layer patterns 908 are separated from each other, the first conductive layer pattern 910 includes a control terminal pattern N1, an output terminal pattern N2, and an input terminal pattern N3, the sixth insulating plate second surface is a surface facing the semiconductor device 912, the second conductive layer pattern 908 includes a second conductive layer pattern N1 ', a second conductive layer pattern N2'), A second conductive layer pattern N3 ', an input electrode of the first surface of the semiconductor device 912 being connected to the input terminal pattern N4 of the input terminal patterns through a first electrical connection structure 914, the input terminal pattern N4 being connected to the second conductive layer pattern N3' of the second conductive layer pattern 908, a control electrode and an output electrode of the second surface of the semiconductor device being connected to the second conductive layer pattern N1 'and the second conductive layer pattern N2' through different third electrical connection structures 916, respectively; the second conducting layer pattern N1 ', the second conducting layer pattern N2 ' and the second conducting layer pattern N3 ' are respectively connected with a control terminal pattern N1, an output terminal pattern N2 and an input terminal pattern N3 through conducting materials in through holes penetrating through the sixth insulating plate 906, and the control terminal pattern N1, the output terminal pattern N2 and the input terminal pattern N3 are respectively connected with a control terminal, an output terminal and an input terminal of the device package through solder balls or metal frames or solder balls or metal connecting wires; the second conductive layer pattern 908 is shaped according to a heat dissipation and connection design.

As shown in fig. 12, the first conductive layer patterns 930 include at least input terminal patterns, the package structure further includes a seventh substrate 932 positioned between the third electrical connection structure and the corresponding electrodes of the device package, the seventh substrate 932 includes a seventh insulating layer 934, and at least one first conductive layer pattern 936 disposed on a first surface of the seventh insulating layer, different first conductive layer patterns 936 are separated from each other when the number of the first conductive layer patterns 936 is equal to or greater than 2, the first conductive layer patterns 936 include a control terminal pattern P1, an output terminal pattern P2, and an input terminal pattern P3, the first surface of the seventh insulating layer is a surface connected to the corresponding electrodes of the device package, an input electrode on the first surface of the semiconductor device 938 is connected to an input terminal pattern P4 in the input terminal patterns through the first electrical connection structure 940, the input terminal pattern P4 is connected to an input terminal pattern P3 in the first conductive layer patterns 936, the control electrode and the output electrode of the second surface of the semiconductor device are connected to the control terminal pattern P1 and the output terminal pattern P2 through different third electrical connection structures 942, respectively; the control terminal pattern P1, the output terminal pattern P2, and the input terminal pattern P3 are connected to the control terminal, the output terminal, and the input terminal of the device package through solder balls or metal frames or solder balls or metal connecting lines, respectively.

In one embodiment, the package structure is a flip chip package structure, and the first substrate is a metal substrate.

In one embodiment, the package structure may be a via package structure, a surface mount package structure.

In one embodiment, the package structure may be used for module packaging of power semiconductor devices, integrated circuit chips, discrete devices, and multiple chips.

In one embodiment, the first conductive layer pattern and/or the first conductive layer pattern is shaped according to a heat dissipation, electrical isolation, and connection design.

A package structure, the package structure comprising: the semiconductor device comprises a first surface and a second surface which are opposite, wherein the first surface is provided with at least one device electrode, the second surface is provided with at least one device electrode, the first substrate comprises an insulating plate and at least one first conducting layer pattern arranged on the first surface of the insulating plate, and the first conducting layer pattern is used for being connected with one device electrode arranged on the first surface of the semiconductor device; the first electrical connection structure is arranged between the first surface of the semiconductor device and the first conducting layer pattern and is used for correspondingly connecting the device electrodes arranged on the first surface of the semiconductor device with the first conducting layer pattern one by one; a second electrical connection structure for connecting the first conductive layer pattern to a corresponding electrode of a device package; the third electrical connection structure is arranged on the second surface of the semiconductor device and used for connecting the device electrode arranged on the second surface of the semiconductor device to the corresponding electrode of the device package, and the thickness of the second electrical connection structure is larger than the sum of the thicknesses of the first electrical connection structure and the third electrical connection structure; the first conducting layer patterns are in shapes designed according to heat dissipation and connection, and when the number of the first conducting layer patterns is larger than or equal to 2, different first conducting layer patterns are separated from each other. The first substrate comprises an insulating plate and at least one first conducting layer pattern which is arranged on the first surface of the insulating plate and designed according to heat dissipation and connection, device electrodes arranged on the first surface of the semiconductor device are connected with the first conducting layer pattern on the first surface of the insulating plate in a one-to-one correspondence mode, and device electrodes arranged on the second surface of the semiconductor device are connected with corresponding electrodes of a device package, so that heat generated in the operation process of the semiconductor device is dissipated through the first conducting layer pattern connected with the first surface of the semiconductor device and the corresponding electrodes of the device package connected with the second surface of the semiconductor device at the same time, junction temperature in the operation process of the device is reduced, and the service life and reliability of the semiconductor device are prolonged.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.