阅读说明：本技术 具有用于顶侧冷却的多级传导夹的半导体封装 (Semiconductor package with multilevel conductive clip for top side cooling ) 是由 方炽胜 邱威翰 I·尼基廷 戴秋莉 于 2020-04-30 设计创作，主要内容包括：一种半导体封装包括：具有管芯附接表面的管芯焊盘；被安装在管芯附接表面上的半导体管芯,并且所述半导体管芯在背离所述管芯附接表面的上表面处具有第一接合焊盘；互连夹,所述互连夹包括至少部分地包围中央开口的第一区段、在垂直方向上从第一区段偏移并且与第一区段隔开的第二区段、以及在第一区段和第二区段之间延伸的支撑部。所述封装还包括覆盖半导体管芯的电绝缘的包封物。互连夹的第一区段的上表面从包封物的平面表面暴露。第二区段的下表面与半导体管芯的上表面齐平,并且第二区段的下表面传导连接至第一接合焊盘。(A semiconductor package includes: a die pad having a die attach surface; a semiconductor die mounted on a die attach surface and having first bond pads at an upper surface facing away from the die attach surface; an interconnect clip including a first section at least partially surrounding a central opening, a second section vertically offset from and spaced apart from the first section, and a support extending between the first section and the second section. The package also includes an electrically insulative encapsulant covering the semiconductor die. An upper surface of the first section of the interconnect clip is exposed from the planar surface of the enclosure. The lower surface of the second segment is flush with the upper surface of the semiconductor die, and the lower surface of the second segment is conductively connected to the first bond pad.)

1. A semiconductor package, comprising:

a die pad comprising a die attach surface;

a semiconductor die mounted on the die attach surface and including a first bond pad at an upper surface facing away from the die attach surface;

an interconnect clip, the interconnect clip comprising:

a first section at least partially surrounding a central opening;

a second section vertically offset from and spaced apart from the first section; and

a support extending between the first section and the second section; and

an electrically insulating encapsulant covering the semiconductor die,

wherein an upper surface of the first section of the interconnect clip is exposed from a planar surface of the enclosure, and

wherein a lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bond pad.

2. The semiconductor package of claim 1, wherein the second section is a planar pad having a closed shape geometry, and wherein the support wraps around a perimeter of the second section from a plan view perspective of the interconnect clip.

3. The semiconductor package of claim 2, wherein the second segment has a rectangular geometry, and wherein the support wraps around at least one corner of the second segment from the plan view perspective of the interconnect clip.

4. A semiconductor package according to claim 2, wherein the support forms a complete closed loop extending between an outer edge side of the second section and an inner edge side of the first section facing the central opening.

5. The semiconductor package of claim 1, wherein the interconnect clip has an L-shaped geometry from a plan view perspective of the interconnect clip, wherein the semiconductor die further comprises a second bond pad at the upper surface, and wherein the second bond pad is outside a footprint of the interconnect clip.

6. A method of packaging a semiconductor device, the method comprising:

providing a die pad comprising a die attach surface;

providing a semiconductor die comprising a first bond pad on an upper surface of the semiconductor die;

mounting the semiconductor die on the die pad such that the first bond pad faces away from the die attach surface;

providing an interconnect clip, the interconnect clip comprising:

a first section at least partially surrounding a central opening;

a second section vertically offset from and spaced apart from the first section; and

a support extending between the first section and the second section; so as to;

mounting the interconnect clip on the semiconductor die such that a lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bond pad; and

forming an electrically insulating encapsulant such that the semiconductor die is covered by the encapsulant and such that an upper surface of the first section of the interconnect clip is exposed from an upper surface of the encapsulant.

7. The method of claim 6, wherein the second segment is a planar pad having a closed shape geometry, and wherein the support wraps around a perimeter of the second segment from a plan view perspective of the interconnect clip.

8. The method of claim 6, wherein the encapsulant is formed such that the upper surface of the first section of the interconnect clip is substantially coplanar with a planar surface of the encapsulant, and wherein forming the encapsulant comprises completely covering the interconnect clip with the encapsulant and then planarizing the encapsulant until the upper surface of the first section is exposed from the planar surface of the encapsulant.

9. An interconnect clip, comprising:

a first section at least partially surrounding a central opening;

a second section vertically offset from and spaced apart from the first section; and

one or more supports extending between the first section and the second section.

10. The interconnect clip of claim 9, wherein the first section forms a closed shape around the central opening.

11. The interconnect clip of claim 10, wherein the first section completely surrounds the central opening.

12. The interconnect clip of claim 9, wherein the one or more supports extend diagonally opposite between an outer edge side of the second section and an inner edge side of the first section facing the central opening.

13. The interconnect clip of claim 9, wherein the interconnect clip includes a plurality of supports extending between the first and second segments, each of the supports being separated from each other by a lateral gap.

14. The interconnect clip of claim 9, wherein the interconnect clip includes only one of the supports extending between the first segment and the second segment.

15. The interconnect clip of claim 14, wherein the second segment is a planar pad having a closed shape geometry, and wherein the support wraps around a perimeter of the second segment from a plan view perspective of the interconnect clip.

16. The interconnect clip of claim 15, wherein the second segment has a rectangular geometry, and wherein the support portion wraps around at least one corner of the second segment from the perspective of the plan view of the interconnect clip.

17. The interconnect clip of claim 15, wherein the support portion forms a complete closed loop extending between an outer edge side of the second segment and an inner edge side of the first segment facing the central opening.

Technical Field

Embodiments of the present invention relate generally to semiconductor packages and, more particularly, to cooling and interconnect features of semiconductor packages.

Background

Semiconductor packages are designed to provide connection compatibility between a semiconductor die and external devices, such as a Printed Circuit Board (PCB), and to protect the semiconductor die from potentially damaging environmental conditions (e.g., temperature variations, humidity, dust particles, etc.). In many semiconductor packages, an important design consideration is the cooling capacity of the package. Many semiconductor dies generate a significant amount of heat during typical operation. One example of such a device is a power semiconductor device, which is required to block a substantial voltage, e.g., 200 volts or more, during normal operation. Cooling features are often required to ensure that the semiconductor die operates within a safe temperature range.

The package of the bottom side cooling arrangement is designed to carry heat away from the semiconductor die toward the bottom side of the package. In one example of such a configuration, the semiconductor die is mounted on a metal substrate with the load terminals (e.g., source, anode, etc.) facing the metal substrate. The lower surface of the metal substrate is exposed at the bottom side of the package. The package may be mounted on a circuit board and mated with a heat sink that carries heat away from the package substrate during operation.

Double-sided cooling packages seek to provide improved heat dissipation capabilities compared to packages of bottom-side cooling configurations. The double-sided cooling package includes features that provide conductive paths between the bottom side of the die and the lower side of the package (e.g., as described above) and the upper side of the die and the upper side of the package. A double-sided cooling package may be mounted on the circuit board with a second heat sink mounted on top of the package to draw heat away from the upper side of the package. In general, a double-sided cooling package should preferably extract heat relatively uniformly in both directions (i.e., toward the bottom side and toward the top side) away from the semiconductor die. However, known topside cooling features do not achieve this balance. Furthermore, they require costly and time consuming processing steps, such as soldering, fusing, etc., to incorporate known top side cooling features into the semiconductor package.

Disclosure of Invention

A semiconductor package is disclosed. According to an embodiment, the semiconductor package comprises: a die pad comprising a die attach surface; a semiconductor die mounted on the die attach surface, the semiconductor die including first bond pads at an upper surface facing away from the die attach surface; an interconnect clip including a first section at least partially surrounding a central opening, a second section vertically offset from and spaced apart from the first section, and one or more supports connected between the first section and the second section; and an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first section of the interconnect clip is exposed from an upper surface of the enclosure. The lower surface of the second section is flush with the first bond pad.

Individually or in combination, an upper surface of the first section exposed from the upper surface of the encapsulant extends laterally in each direction across the outer edge side of the semiconductor die.

Individually or in combination, the central portion of the enclosure interfaces directly with the inner edge side of the first section and extends to the upper surface of the enclosure.

Individually or in combination, the semiconductor package further includes a metal heat pillar attached to the upper surface of the second section and extending to the upper surface of the encapsulant, wherein a central portion of the encapsulant fills a region between the heat pillar and the inner edge side of the first section.

Individually or in combination, the first section forms a closed shape around the central opening.

The semiconductor package also includes, either alone or in combination, a first lead spaced apart from the die pad, and an interconnect clip electrically connects the first bond pad to the first lead.

Individually or in combination, the interconnect clip further comprises a tip connector extending from the first segment toward the first lead and an outer end of the tip connector is in direct electrical contact with the first lead.

The connection point between the support and the first section is offset in the lateral direction from the connection point between the support and the second section, either alone or in combination.

Individually or in combination, each of the supports extends diagonally opposite between an outer edge side of the second section and an inner edge side of the first section facing the central opening.

Individually or in combination, the interconnect clip comprises two pairs of supports, the supports of each pair extending away from each other in opposite directions, each of the supports being mutually spaced apart by a transverse gap, and the encapsulant filling the transverse gap.

Individually or in combination, the upper surface of the first section and the lower surface of the second section are substantially parallel to each other and the upper surface of the first section is substantially coplanar with the upper surface of the enclosure.

Individually or in combination, the first section, the second section and the support are integrally formed parts of a planar metal sheet.

A method of packaging a semiconductor device is disclosed. According to an embodiment, the method comprises: providing a die pad comprising a die attach surface; providing a semiconductor die comprising a first bond pad on an upper surface of the semiconductor die; mounting a semiconductor die on a die pad such that a first bond pad faces away from the die attach surface; providing an interconnect clip comprising a first section at least partially surrounding a central opening, a second section vertically offset from and spaced apart from the first section, and one or more supports connected between the first section and the second section; mounting the interconnect clip on the semiconductor die such that the lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bond pad; and forming an electrically insulating encapsulant such that the semiconductor die is covered by the encapsulant and such that an upper surface of the first section of the interconnect clip is exposed from an upper surface of the encapsulant.

Separately or in combination, after forming the encapsulant, an upper surface of the first section exposed from an upper surface of the encapsulant extends laterally in each direction beyond an outer edge side of the semiconductor die.

Separately or in combination, after forming the enclosure, a central portion of the enclosure interfaces directly with the inner edge side of the first section and extends to an upper surface of the enclosure.

Separately or in combination, the method further includes providing a first lead spaced from the die pad and electrically connecting the first bond pad to the first lead using an interconnect clip.

Individually or in combination, the interconnect clip includes a plurality of supports, each of which is laterally spaced by a gap, and the liquefied molding material flows through each of the gaps during formation of the encapsulant.

Separately or in combination, the liquefied molding material flowing through each of the gaps flows in a lateral direction directed toward the central opening.

Separately or in combination, providing the interconnect clip includes selecting an area of the second section to correlate to an area of the semiconductor die.

Separately or in combination, providing the interconnect clip includes providing a planar sheet of metal, and forming a unitary structure from the planar sheet of metal that includes the first section, the second section, and the support portion.

A semiconductor package is disclosed. According to an embodiment, the semiconductor package comprises: a die pad comprising a die attach surface; a semiconductor die mounted on the die attach surface and including first bond pads at an upper surface facing away from the die attach surface; and an interconnect clip. The interconnect clip includes: a first section at least partially surrounding the central opening; a second section vertically offset from and spaced apart from the first section; and a support extending between the first section and the second section. The semiconductor package also includes an electrically insulative encapsulant covering the semiconductor die. An upper surface of the first section of the interconnect clip is exposed from the planar surface of the enclosure. The lower surface of the second segment is flush with the upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bond pad.

Separately or in combination, the second section is a planar pad having a closed shape geometry and the support portion wraps around a perimeter of the second section from a plan view perspective of the interconnect clip.

Individually or in combination, the second section has a rectangular geometry and the support portion wraps around at least one corner of the second section from a plan view perspective of the interconnect clip.

The support, alone or in combination, forms a complete closed ring extending between the outer edge side of the second section and the inner edge side of the first section facing the central opening.

Either alone or in combination, the interconnect clip has an L-shaped geometry from a plan view perspective of the interconnect clip, the semiconductor die further includes a second bond pad at the upper surface, and the second bond pad is outside a footprint of the interconnect clip.

A method of packaging a semiconductor device is disclosed. According to an embodiment, the method comprises: providing a die pad comprising a die attach surface; providing a semiconductor die comprising a first bond pad on an upper surface of the semiconductor die; mounting a semiconductor die on a die pad such that a first bond pad faces away from the die attach surface; and providing an interconnect clip. The interconnect clip includes: a first section at least partially surrounding the central opening; a second section vertically offset from and spaced apart from the first section; and a support extending between the first section and the second section. The method further comprises the following steps: mounting an interconnect clip on the semiconductor die such that a lower surface of the second segment is flush with an upper surface of the semiconductor die and the lower surface of the second segment is conductively connected to the first bond pad; and forming an electrically insulating encapsulant such that the semiconductor die is covered by the encapsulant and such that an upper surface of the first section of the interconnect clip is exposed from an upper surface of the encapsulant.

Separately or in combination, the second section is a planar pad having a closed shape geometry and the support portion wraps around a perimeter of the second section from a plan view perspective of the interconnect clip.

Separately or in combination, forming the encapsulant such that an upper surface of the first section of the interconnect clip is substantially coplanar with a planar surface of the encapsulant, and forming the encapsulant includes completely covering the interconnect clip with the encapsulant and then planarizing the encapsulant until the upper surface of the first section is exposed from the planar surface of the encapsulant.

An interconnect clip is disclosed. According to an embodiment, the interconnect clip comprises: a first section at least partially surrounding the central opening; a second section vertically offset from and spaced apart from the first section; and one or more supports extending between the first and second sections.

Individually or in combination, the first section forms a closed shape around the central opening.

Individually or in combination, the first section completely surrounds the central opening.

Individually or in combination, the one or more supports extend diagonally opposite between an outer edge side of the second section and an inner edge side of the first section facing the central opening.

Individually or in combination, the interconnect clip includes a plurality of supports extending between the first and second sections, each of the supports being separated from each other by a lateral gap.

Individually or in combination, the interconnect clip includes only one of the supports extending between the first and second sections.

Separately or in combination, the second section is a planar pad having a closed shape geometry, and wherein the support portion wraps around a perimeter of the second section from a plan view perspective of the interconnect clip.

Individually or in combination, the second section has a rectangular geometry and the support portion wraps around at least one corner of the second section from a plan view perspective of the interconnect clip.

The support, alone or in combination, forms a complete closed ring extending between the outer edge side of the second section and the inner edge side of the first section facing the central opening.

Drawings

The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Embodiments are depicted in the drawings and will be described in detail in the following description.

FIG. 1, which includes FIG. 1A, FIG. 1B, and FIG. 1C, depicts an interconnect clip according to an embodiment. Fig. 1A depicts a plan view of the interconnect clip, fig. 1B depicts a cross-sectional view of the interconnect clip along a cross-sectional plane a-a' indicated in fig. 1A, and fig. 1C depicts an isometric view of the interconnect clip.

Fig. 2 depicts an isometric view of an interconnect clip according to another embodiment.

Fig. 3, which includes fig. 3A and 3B, depicts an interconnect clip mounted on an assembly of a leadframe and a semiconductor die, in accordance with an embodiment. Fig. 3A depicts a plan view of the assembly, and fig. 3B depicts a cross-sectional view of the assembly.

Fig. 4 depicts a flow of molding material liquefied during an encapsulation process in an assembly with an interconnect clip installed, according to an embodiment.

Fig. 5, which includes fig. 5A, 5B, and 5C, depicts a semiconductor package including an interconnect clip according to an embodiment. Fig. 5A depicts an isometric view of an upper side of the semiconductor package, fig. 5B depicts an isometric view of a lower side of the semiconductor package, and fig. 5C depicts a cross-sectional view of the semiconductor package.

Fig. 6, which includes fig. 6A and 6B, depicts a semiconductor package including an interconnect clip according to another embodiment. Fig. 6A depicts an isometric view of an upper side of the semiconductor package, and fig. 6B depicts a cross-sectional view of the semiconductor package.

Fig. 7, which includes fig. 7A and 7B, depicts a semiconductor package including an interconnect clip according to another embodiment. Fig. 7A depicts an isometric view of an upper side of the semiconductor package, and fig. 7B depicts an isometric view of a lower side of the semiconductor package.

Fig. 8, which includes fig. 8A and 8B, depicts an interconnect clip according to an embodiment. Fig. 8A depicts a plan view of the interconnect clip, and fig. 8B depicts a cross-sectional view of the interconnect clip along the section plane B-B' indicated in fig. 8A.

Fig. 9, including fig. 9A, 9B, 9C, and 9D, depicts a semiconductor package including the interconnect clip of fig. 8 according to an embodiment. Fig. 9A depicts a plan view of an upper side of the semiconductor package, fig. 9B depicts a side view of the semiconductor package, fig. 9C depicts an isometric view of the upper side of the semiconductor package, and fig. 9D depicts a close-up isometric view of an interface connection between an interconnect clip and a semiconductor die.

Fig. 10 depicts an isometric view of a semiconductor package including the interconnect clip of fig. 8 according to an embodiment.

Detailed Description

Embodiments of an interconnect clip that provides advantageous top-side cooling capability in a semiconductor package and is easily incorporated into a semiconductor package are described herein. The interconnect clip has a multi-level configuration in which the first planar section and the second planar section are offset from each other in a vertical direction. In an embodiment, the first planar section forms a closed shape (e.g. a ring shape) around the central opening, the second planar section is arranged below the central opening, and a discrete support structure extends between the first planar section and the second planar section, wherein a lateral gap is provided between the support structures. The interconnect clip is incorporated into a semiconductor package, wherein the second section is mounted flush with the upper surface of the semiconductor die and the first section is exposed at an upper side of the package encapsulation body. For example, the exposed first section may provide an interface connection that transfers heat away from the top side of the package via a heat sink. In addition, the interconnect clip may provide electrical connections between bond pads on the upper surface of the semiconductor die and package leads or contacts.

The multi-level design of the interconnect clip advantageously allows for a large exposed surface area of the conductive metal at the upper surface of the package. The interconnect clip may accommodate the large sized first section when mounted on the semiconductor die due to the lateral stability provided by the second planar section in combination with the cradle configuration of the support structure. Thus, a semiconductor package including the interconnect clip may have an exposed conductive surface on the upper side of the package that extends beyond the die footprint in each direction and near the outside of the package.

In addition, various features of the interconnect clip are configured to interact with the liquefied molding material during encapsulation in a manner that maintains stability of the interconnect clip. In particular, the interconnecting clip is designed such that the liquefied molding material flows uniformly through the lateral gaps between the support structures. This liquefied molding material accumulates in the central region of the package and interacts with the inner edge side of the central opening in the first section. Thus, the interconnect clip remains horizontal and flush with the semiconductor die during encapsulation, and the first section remains aligned with the upper surface of the package. Thus, costly and time-consuming measures for fixing the interconnection clip, such as welding, are avoided.

Referring to fig. 1, an interconnect clip 100 is depicted in accordance with an embodiment. Interconnect clip 100 includes a first section 102 and a second section 104. The first and second sections 102, 104 each include oppositely facing upper and lower surfaces 106, 108. According to an embodiment, the first section 102 and the second section 104 are planar pads having a substantially uniform thickness. The second section 104 is vertically spaced from the first section 102. This means that at least some separation distance is provided between the lower surface 108 of the first section 102 and the upper surface 106 of the second section 104.

According to an embodiment, the first section 102 at least partially surrounds the central opening 110. This means that an open channel is provided between the upper surface 106 and the lower surface 108 of the first section 102 at a location within the outer perimeter 112 of the first section 102. The inner edge side 114 of the first section 102 faces the central opening 110. These inner edge sides 114 extend between the upper surface 106 and the lower surface 108 of the first section 102, and the inner edge sides 114 are opposite the outer edge sides 116 of the first section 102, the outer edge sides 116 of the first section 102 defining the outer perimeter 112 of the first section 102.

According to the depicted embodiment, the first section 102 completely surrounds the central opening 110. That is, the first section 102 forms a closed shape around the central opening 110 such that a lateral portion of the first pad separates an inner edge side 114 of the first section 102 from an outer perimeter 112 in each direction. Alternatively, the first section 102 may have a variety of open shape configurations, wherein at least one set of inner edge sides 114 extends to the outer perimeter 112 of the first section 102. Examples of such open shape configurations include C-shaped, U-shaped, and the like.

According to an embodiment, the second section 104 is a continuous pad with a closed shape geometry. For example, as shown, the second section 104 has a rectangular geometry. More generally, the geometry of the second section 104 may include curved shapes, elongated shapes, etc., and may be interrelated with different die and/or bond pad geometries. Further, embodiments of the interconnect clip 100 may include a plurality of discrete second segments 104.

According to the depicted embodiment, the second section 104 is disposed directly below the central opening 110. Further, the second section 104 is smaller than the central opening 110. Thus, the outer edge side 118 of the second section 104 is laterally spaced from the inner edge side 114 of the first section 102 in each direction, as shown in fig. 1A. Alternatively, the second section 104 may be larger than the central opening 110, and/or the second section 104 is laterally offset from the central opening 110. In general, the second section 104 may be located proximate to the lateral center of mass of the interconnect clip 100. In this manner, when interconnect clip 100 is mounted on a planar surface, second section 104 maintains the lateral stability of the clip by relieving the leverage exerted by first planar section 102.

Interconnect clip 100 includes a support 120 connected between first segment 102 and second segment 104. The support 120 mechanically couples the first section 102 to the second section 104. Furthermore, the support 120 provides a thermally and electrically conductive connection between the first section 102 and the second section 104.

According to an embodiment, the interconnect clip 100 includes four supports 120. More specifically, as shown in fig. 1, the interconnect clip 100 may include two pairs of supports 120, the supports 120 of each pair extending away from each other in opposite directions. This is just one example of a design well suited for achieving mechanical support of the first section 102.

According to an embodiment, the connection point between the support 120 and the first section 102 is laterally offset from the connection point between the support 120 and the second section 104. In other words, the support 120 does not extend solely in the vertical direction between the first section 102 and the second section 104. Rather, the support 120 is oriented to connect at a location laterally closer to the outer edge side 116 of the first section 102 than its connection point with the second section 104. For example, in the depicted embodiment, each of the vertical supports 120 extends diagonally opposite between the second section 104 and the first section 102. Alternatively, the vertical supports 120 may have one or more angular bends to achieve laterally offset connection points. In either configuration, as the support 120 moves away from the second segment 104 and toward the first segment 102, the outward extension of the support 120 will enhance structural support and stability by providing a cradle-type configuration.

According to an embodiment, the supports 120 are separated from each other by a lateral gap 122. This means that at least a certain separation distance is provided between the defined edge sides of the support 120 extending vertically between the second section 104 and the first section 102. Thus, from a side view perspective of the interconnect clip 100 (e.g., as shown in fig. 1B), the lateral gap 122 provides an open channel between a region directly below the lower surface 108 of the first segment 102 and a region directly above the upper surface 106 of the second segment 104. The size, shape and sizing of these lateral gaps 122 may be different than that shown. In general, the arrangement, number, and size of the lateral gaps 122 may be customized to meet a wide variety of design factors. These design factors include facilitating the flow of the liquefied mold material through the transverse gap 122 and sizing requirements for the support 120. Instead of the depicted configuration, the lateral gap 122 may be implemented as a narrow slit and/or a circular opening provided between the relatively large support structures 120.

According to an embodiment, the interconnect clip 100 includes a tip connector 124. The tip connector 124 is directly connected to the first section 102 and extends away from the lower surface 108 of the first section 102 toward the outer end 126. The outer end 126 of the tip connector 124 is disposed on the same side of the first section 102 as the second section 104. As shown, the tip connector 124 and the first section 102 can be portions of a continuous planar structure that are bent downward at one end. Alternatively, the tip connector 124 may be part of a separate structure that is attached to the first section 102.

Each of the above-discussed features of the interconnect clip 100 is formed of a thermally and electrically conductive material. Exemplary materials for the interconnect clip 100 include copper, aluminum, nickel, iron, zinc, and the like, and alloys thereof. In any case, the material used to form the interconnect clip 100 may be selected to provide a thermally conductive connection between the lower surface 108 of the second segment 104 and the upper surface 106 of the first segment 102. In this manner, the interconnect clip 100 is configured to provide topside cooling capability. In addition, the material used to form the interconnect clip 100 can be selected to provide an electrically conductive connection between the lower surface 108 of the second segment 104 and the outer ends 126 of the end connectors 124. In this manner, the interconnect clip 100 is configured to provide electrical interconnect capability.

According to an embodiment, the interconnect clip 100 is integrally formed from a planar sheet of metal. For example, an interconnect clip 100 having the features discussed above may be provided by initially providing an undisturbed conductive sheet of metal (e.g., a flat sheet of metal such as copper, aluminum, alloys thereof, etc., which is similar or identical to the sheet of metal used to form the package lead frame). The planar sheet metal can then be processed to form the first and second segments 102, 104 and the central opening 110 offset in the vertical direction. In one embodiment, this is accomplished by stamping or punching a flat piece of sheet metal. The lateral gaps 122 may be formed simultaneously or separately using an embossing, stamping, or etching process. Thus, the first section 102, the second section 104 and the support 120 are integrally formed portions of a single piece of planar sheet metal. In an embodiment, the end connectors 124 are formed by bending a planar portion of a metal sheet before, during, or after the above steps. Alternatively, the interconnect clip 100 may be formed by connecting two discrete conductive structures together using known techniques (e.g., soldering, welding, riveting, etc.).

Advantageously, the features of the interconnect clip 100 may be customized to match specific characteristics of the semiconductor die and/or package design. For example, according to an embodiment, the interconnect clip 100 is formed by selecting the area of the second section 104 to correlate in the completed semiconductor package with the particular semiconductor die to which it is to be attached. This means that the second section 104 has the same general shape as the semiconductor die, e.g., square, rectangular, etc., and the lateral surface area of the second section 104 is the same as or close to (e.g., within +/-10%) the surface area of the semiconductor die. In this manner, a manufacturer of the semiconductor package may provide an interconnect clip 100 that is preferably configured to achieve mechanical stability and heat transfer with respect to a particular semiconductor die. Further, this customization may be achieved using simple processing steps, for example, by appropriately selecting the stamping/coining dimensions according to the techniques described above for forming the interconnect clip 100. As another example, the outer perimeter 112 of the first section 102 may be sized to be close to or slightly smaller than the desired package size (e.g., about 90% of its lateral surface area).

Referring to fig. 2, an interconnect clip 100 is shown according to another embodiment. The interconnect clip 100 of fig. 2 is identical to the interconnect clip 100 described with reference to fig. 1, except that the support portion 120 is configured differently. In the embodiment of fig. 2, the interconnect clip 100 also includes two pairs of supports 120, wherein the supports 120 of each pair extend away from each other in opposite directions. However, the support portion 120 is provided at the corner position of the second pad and the central opening 110 instead of the central connection point configuration shown in fig. 1. Further, the support portion 120 has a larger cross-sectional diameter than the support portion 120 of the interconnect clip 100 of fig. 1. Such a configuration may be desirable to achieve higher mechanical strength and conductivity.

More generally, the configuration of the vertical supports 120 may differ from the particular embodiment of fig. 1-2. The arrangement, number, and size of the supports 120 may be optimized with respect to a variety of design factors, such as the mechanical strength of the supports 120, the conductive capabilities (both thermally and electrically conductive) of the supports 120, and/or the sizing of the lateral gaps 122 between the supports 120.

Referring to fig. 3, selected method steps for packaging a semiconductor device using an interconnect clip 100 are illustrated, in accordance with an embodiment. In this method step, a lead frame 128 is provided. The lead frame 128 includes an electrically and thermally conductive material, for example, an electrically conductive material such as copper, aluminum, nickel, iron, zinc, and the like, and alloys thereof. The lead frame 128 includes a die pad 130 having a die attach surface 132. In addition, the lead frame 128 includes conductive leads 134 that extend away from the die pad 130. In the depicted embodiment, the leads 134 of the first group 136 are directly connected to the die pad 130, and the leads 134 of the second group 138 are separated from the die pad 130. Leads 134 may be bent wherein the outermost ends of leads 134 extend substantially parallel to the bottom side of the package, wherein the leads may include positive or negative bumps (stand-off).

In this method step, a semiconductor die 140 is mounted on the die attach surface 132 of the die pad 130. In general, the semiconductor die 140 may have a wide variety of device configurations, such as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction field effect transistors), diodes, and the like. In general, semiconductor die 140 may comprise any of a wide variety of semiconductor materials, including type IV semiconductors such as silicon, silicon germanium, silicon carbide, and the like, as well as type III-V semiconductors such as gallium nitride, gallium arsenide, and the like. In general, the semiconductor die 140 may be configured as a vertical device configured to control current flow between oppositely facing upper and lower surfaces, or the semiconductor die 140 may be configured as a lateral device configured to control current flow parallel to the major surfaces.

According to an embodiment, the semiconductor die 140 includes first bond pads 142 disposed on an upper surface of the semiconductor die 140 facing away from the die attachment surface 132 and second bond pads 144 disposed on a rear surface of the semiconductor die 140 facing toward the die attachment surface 132. These first bond pads 142 and second bond pads 144 provide terminal connections to the semiconductor die 140. For example, the first and second bonding pads 142 and 144 may be load terminals, e.g., anode and cathode terminals in the case of a diode, or collector/emitter terminals in the case of a switching device. For purposes of brevity, only two bond pads are shown. In practice, the semiconductor die 140 may include additional bond pads, e.g., control terminals, such as gates, bases, etc. in the case of a three-terminal switching device. These additional bond pads may be connected to leads 134 using known techniques.

In this method step, the interconnect clip 100 is mounted on top of the semiconductor die 140. According to an embodiment, the interconnect clip 100 is mounted such that the lower surface 108 of the second section 104 is flush with the upper surface of the semiconductor die 140. This means that the lower surface 108 of the second section 104 is substantially parallel to the upper surface of the semiconductor die 140, and the two surfaces are mechanically coupled to each other, e.g., by direct contact or through an intermediary (e.g., solder, sintering agent, adhesive, etc.).

According to an embodiment, the interconnect clip 100 is mounted such that the lower surface 108 of the second segment 104 is conductively connected (electrically and thermally) to the first bond pad 142. This conductive connection may be made by direct physical contact between the two surfaces, or may be made by a conductive joining material (e.g., solder, sintering agent, conductive glue, etc.).

According to an embodiment, the interconnect clip 100 is mounted such that the outer ends 126 of the end connectors 124 are in direct electrical contact with the first leads 134 from the lead frame 128. This conductive connection may be made by direct physical contact between the two surfaces, or may be made by a conductive joining material (e.g., solder, sintering agent, conductive glue, etc.). As a result of this connection and the connection between second segment 104 and first bond pad 142 as described above, interconnect clip 100 provides a direct electrical connection between first bond pad 142 and first lead 134.

According to an embodiment, when mounted, the interconnect clip 100 overhangs laterally in each direction beyond the outer edge sides 146 of the semiconductor die 140. This means that the outer edge side 146 of the semiconductor die 140 is located entirely within the lateral footprint of the first section 102 (as defined by the outer perimeter 112 of the first section 102). This configuration differs from conventional interconnect clip 100 configurations in that the clip provides a direct point-to-point connection between two terminals (e.g., bond pads and wires) and thus extends over only one edge side of the semiconductor die. While mounted interconnect clip 100 may provide a similar point-to-point connection between first bond pad 142 and first lead 134, with portions of first segment 102 disposed outside of the current path between first bond pad 142 and first lead 134. For example, the leftmost portion of the first segment 102 in fig. 3 is disposed outside of the current path.

Referring to fig. 4, selected method steps for packaging a semiconductor device using an interconnect clip 100 are illustrated, in accordance with an embodiment. In this method step, the assembly of fig. 3 is encapsulated with an electrically insulating material using a molding process. Exemplary techniques for such molding processes include, for example, injection molding, compression molding, transfer molding. In these techniques, the assembly is placed within the cavity 148 of the molding tool and the cavity is filled with liquefied molding material. Examples of such molding materials include ceramics, epoxy materials, thermosets, for example. The liquefied molding material fills the cavity 148, thereby forming the desired shape of the package body. Subsequently, the liquefied molding material hardens, and the package is removed from the molding cavity 148.

According to an embodiment, the liquefied molding material flows through each of the lateral gaps 122 during formation of the encapsulant. More specifically, the liquefied molding material may flow in a lateral direction directed toward the central opening 110. This directional flow of liquefied molding material is depicted by the arrows in fig. 4. As the liquefied molding material continues to flow, it covers the second section 104 and eventually reaches the inner edge side 114 of the first section 102 until the central portion of the enclosure previously described is formed.

Advantageously, the features of the interconnect clip 100 are designed to maintain the stability of the interconnect clip 100 and to cause the liquefied molding material to flow uniformly and consistently during the molding process described above. Specifically, the lateral gap 122 enables a relatively uniform flow of molding material over the second section 104. Once covered by the molding material, the second section 104 acts as a footing that maintains the interconnect clip 100 in place. Further, the inner edge side 114 of the first section 102 provides a contact surface that engages the liquefied molding material when accumulated in the central opening 110. This allows for uniform filling of the molding material and maintains the first section 102 in a relatively flat position parallel to the upper surface of the semiconductor die 140.

Referring to fig. 5, a completed semiconductor package 200 is depicted, in accordance with an embodiment. The semiconductor package 200 includes a body of an encapsulant 202 formed in accordance with the techniques described above. The encapsulant 202 is formed to completely cover the semiconductor die 140 with the outer ends of the leads 134 exposed from the encapsulant 202 in a generally known manner.

According to an embodiment, encapsulant 202 is formed such that upper surface 106 of first section 102 of interconnect clip 100 is exposed from upper surface 204 of encapsulant 202. This means that at least a portion of the upper surface 106 of the first section 102 is not covered by the encapsulant 202 material and thus is available for contact with a heat dissipation mechanism (e.g., a heat sink and/or thermal interface material). As shown, the upper surface 106 of the first segment 102 is completely uncovered such that the complete shape of the first segment 102 (in this case a closed loop) is exposed from the enclosure 202. Such a configuration may be achieved by appropriately sizing the molding cavity in the molding technique described above. Alternatively, such a configuration may be achieved by a two-step process in which the encapsulant 202 is initially formed to completely cover the interconnect clip 100, and the upper surface 204 of the encapsulant 202 is subsequently planarized (e.g., by polishing or grinding) until the upper surface 106 of the first segment 102 is exposed from the encapsulant 202.

According to an embodiment, the enclosure 202 is formed such that the upper surface 106 of the first section 102 is substantially coplanar with the upper surface 204 of the enclosure 202. This means that the upper surface 106 of the first section 102 and the upper surface 204 of the encapsulant 202 together form a continuous planar surface providing the upper side of the packaged device. In other embodiments, the interconnect clip 100 may extend from the enclosure 202 such that the upper surface 106 of the first segment 102 is vertically offset from the upper surface 204 of the enclosure 202.

According to an embodiment, the upper surface 106 of the first section 102 is substantially parallel to the lower surface 108 of the second section 104. This configuration orients the upper surface 106 of the first segment 102 along a lateral plane parallel to and spaced apart from the upper surface of the semiconductor die 140 when the interconnect clip 100 is mounted, as shown in fig. 3. Thus, when the enclosure 202 is formed, as shown, for example, in fig. 4, the upper surface 106 of the first segment 102 is positioned coplanar with the upper surface 204 of the enclosure 202.

According to an embodiment, the upper surface 106 of the first section 102 exposed from the encapsulant 202 extends laterally in each direction across the outer edge side 146 of the semiconductor die 140. This means that the outer edge side 146 of the semiconductor die 140 is laterally contained within the perimeter of the exposed conductive material of the first section 102.

According to an embodiment, the enclosure 202 includes a central portion 206 that directly interfaces with the inner edge side 114 of the first section 102. The central portion 106 of the enclosure 202 extends to an upper surface 204 of the enclosure 202, and the upper surface 204 of the enclosure 202 may be coplanar with the upper surface 106 of the first section 102 and/or with the upper surface 204 of the enclosure 202 outside the perimeter of the first section 102. According to an embodiment, the central portion 206 of the enclosure 202 completely covers the upper surface 106 of the second section 104.

The semiconductor package 200 of fig. 5 may be mounted on a carrier (e.g., a printed circuit board) in a generally known manner. The carrier may include a socket with a heat sink that receives the semiconductor package 200 and interfaces with the die pad 130 when mounted. A second heat sink may be mounted on top of the semiconductor package 200. The interconnect clip 100 provides a conductive transmission path to remove heat from the top of the package via the second heat sink. Due to the advantageously large exposed surface area of the interconnect clip 100 as described above, efficient heat transfer may occur.

Referring to fig. 6, a semiconductor package 200 including an interconnect clip 100 is depicted according to another embodiment. The semiconductor package 200 in the embodiment of fig. 6 is configured identically to the semiconductor package 200 of fig. 5, except that the semiconductor package 200 additionally includes a thermal plug 208. The heat column 208 is a discrete piece of thermally conductive material, which may be, for example, a metal such as copper, aluminum, alloys, and the like, and alloys thereof. The bottom surface of the heat pillar 208 is attached to the upper surface 106 of the second section 104, for example, by a conductive adhesive such as solder, a sintering agent, a tape, and the like. The heat pillar 208 extends to the upper surface of the enclosure 202 such that the upper surface of the heat pillar 208 is exposed within the central opening 110. According to an embodiment, an upper surface of heat pillar 208 is substantially coplanar with upper surface 204 of enclosure 202 and/or substantially coplanar with upper surface 106 of first planar section 102. In this example, the central portion 206 of the enclosure 202 fills the area between the heat pillar 208 and the inner edge side 114 of the first section 102. The described combination of the heat post 208 and the interconnect clip 100 may be preferred in some applications to provide even further heat dissipation.

Referring to fig. 7, a semiconductor package 200 is depicted according to another embodiment. The semiconductor package 200 is identical to the semiconductor package 200 described with reference to fig. 5 except for the lead configuration. The semiconductor package 200 of fig. 7 is configured as a "leadless" or "zero lead" package. According to this design, the package includes contacts 210 that are coplanar with the surface of the encapsulant 202 material, instead of leads 134 that extend from the package body. These contacts 210 are electrically connected to the terminals of the semiconductor die 140 in a similar manner as described above in connection with the leads 134, and thus provide package-level connection terminals. The interconnect clip 100 described herein may be used to provide a connection with one of the contacts 210. Alternatively, the interconnect clip 100 described herein may be provided solely as a heat dissipation feature.

Referring to fig. 8, an interconnect clip 100 is depicted in accordance with another embodiment. The interconnect clip 100 of fig. 8 includes a first section 102 surrounding a central opening 110, and a second section 104 below the central opening 110 and vertically separated from the first section 102 by a support 120. Each of these features may have the same properties (e.g., geometry, arrangement, material composition, etc.) as the correspondingly labeled features in the previously discussed embodiments, except for the differences that will be discussed below.

With a first difference from the previously discussed embodiments, the interconnect clip 100 of fig. 8 includes only a single support 120 connected between the first segment 102 and the second segment 104. The support 120 at least partially surrounds the second section 104 when viewed from the perspective of the plan view of fig. 8A. That is, the support 120 is a continuous structure that surrounds the perimeter of the second segment 104. Thus, unlike the previously described embodiments, the interconnect clip 100 does not include a plurality of lateral gaps 122 between a plurality of discrete supports 120.

According to the depicted embodiment, the support 120 surrounds the entire perimeter of the second section 104. That is, the support 120 forms a complete closed loop completely around and abutting the second segment 104. Furthermore, the support 120 completely reaches and abuts the inner edge side 114 of the first section 102 facing the central opening 110. Thus, the second section 104 and the support 120 are collectively configured as a closed depression extending downwardly from the first section 102.

In other embodiments, the support 120 may have a variety of open shape configurations, e.g., C-shaped, U-shaped, etc. In any case, the support 120 may continuously wrap around a majority percentage of the perimeter of the second segment 104. For example, the support 120 may continuously contact at least 50%, 75%, 95%, or more of the total length of the perimeter of the second section 104. In terms of perspective, the support 120 may encompass at least 180 °, 270 °, 330 °, or more of the second segments as viewed from the center of the second segments 104. Where the second section 104 has acute corners, for example in the case of a rectangle, the support portion may wrap around at least one of these corners.

With a second difference from the previously discussed embodiments, the first section 102 of the interconnect clip 100 of fig. 8 has a different geometry when viewed from the perspective of the plan view of fig. 8. In the depicted example, the first segment 102 has an L-shaped geometry, meaning a geometry having two rectangular portions that intersect each other. More generally, the first section 102 may have a wide variety of geometries. For example, the first section 102 may include a rounded portion. In another example, the first section 102 may have a substantially square geometry, as depicted in the embodiment of fig. 1. The selection of a particular geometry for the first section 102 may depend on design considerations, such as package type, die size, lead configuration, and the like.

The interconnect clip 100 of fig. 8 may be formed according to the techniques below. Initially, a planar metal sheet, e.g., a flat metal plate such as copper, aluminum, alloys thereof, or the like, is provided. The planar sheet metal is then shaped to form the desired geometry of the first planar portion, e.g., the L-shaped geometry in the depicted example. This is done, for example, using cutting and/or trimming techniques. Subsequently, an embossing process is performed. The embossing process shifts the portion of the planar metal sheet that corresponds to the desired shape of the second section 104. The offset portion of the planar metal sheet extending to the second section 104 corresponds to the support 120. This embossing process may be performed using known stamping or punching techniques, for example. In general, the depth of the relief can be selected to ensure a sufficient vertical separation distance between the upper surface 106 of the second section 104 and the upper surface 106 of the first section 102. More particularly, embossing may be performed to ensure that the upper surface 106 of the second section 104 remains covered, for example, during polishing or grinding of the enclosure in accordance with techniques to be described below. An example value of this offset in the vertical direction may be in the range of 200 μm-1000 μm. Alternatively, the interconnect clip 100 of fig. 8 may be formed by initially performing a relief process and then shaping the metal sheet (e.g., by cutting and/or trimming).

As shown, the location of the relief is selected such that a single point location (in this case, a corner) of the central opening 114 meets an inside corner 150 of the L-shaped first section 102. More generally, the location and size of the embossment can be selected to meet a variety of design considerations, such as chip size, bond pad configuration, and the like.

One advantage of the interconnect clip 100 of fig. 8 is enhanced heat transfer between the second segment 104 and the first segment 102. In any of the embodiments described herein, the support(s) 120 represent bottleneck points in the thermally conductive path of the interconnect clip 100. Accordingly, during operation, the highest temperatures may occur within the support 120 and/or near the transition between the support 120 and the first and second sections 102, 104. The design of the support 120 in the interconnect clip 100 of fig. 8 advantageously expands this bottleneck point across a large cross-sectional diameter. By comparison, while the plurality of discrete standoff structures 120 in the previously described embodiments of interconnect clip 100 are advantageous for other considerations (e.g., enhanced mold adhesion), they limit the thermal conduction path to a narrower cross-sectional diameter, thereby limiting heat transfer.

Another advantage of the interconnect clip 100 of fig. 8 is that it is easy to manufacture. Because the second section 104, the first section 102, and the support 120 can be formed as an integral part of a single piece of sheet metal, minimal processing steps are required. In particular, only the embossing step described above (e.g. stamping or embossing) is necessary to form the second section 104 and the support 120 with the described geometry and relationship to the first section 102. This embossing step can easily form contact pads that can make full or near full contact with the die surface. Any burrs resulting from the trim process do not contact the die due to the creation of the depression (i.e., the second segment 104). Further, the cutting and/or trimming techniques used to reshape the interconnect clip may readily produce interconnect clips 100 of any desired geometry.

Referring to fig. 9, a semiconductor package 200 including the interconnect clip 100 from the embodiment of fig. 8 is depicted, in accordance with an embodiment. In fig. 9, the encapsulant 202 is depicted as being translucent so that the internal features of the semiconductor package 200 can be seen. Semiconductor package 200 includes die pad 130, conductive leads 134, and semiconductor die 140. Each of these features may be similar or identical to the features with corresponding designations in the semiconductor package 200 described with reference to fig. 5. The semiconductor die 140 is mounted on the die attachment surface 132 of the die pad 130 in a manner similar to that previously described, with the first bond pad 142 facing away from the die attachment surface 132.

The interconnect clip 100 is mounted in a similar manner as previously described, with the second segment 104 flush with the semiconductor die 140 and the second segment 104 electrically connected to the first bond pad 142. The interconnect clip 100 contacts a pad segment of the lead frame 128 at an opposite end in the first segment 102, the pad segment of the lead frame 128 being connected to a plurality of leads 134. In both connections, a conductive joint material, such as solder, sintering agent, conductive glue, etc., may be provided between the two surfaces to form a reliable mechanical and electrical connection. Unlike the embodiment of fig. 5, the leads 134 of the package of fig. 9 are offset from the die pad 130 in the vertical direction. Accordingly, the interconnect clip 100 may directly contact these offset leads at the lower surface 108 of the first planar portion 102. Alternatively, if a vertical drop is required to make such an electrical connection, the end of the first section 102 may include a structure similar or identical to the end connector 124 previously described.

As shown in fig. 9C and 9D, the geometry of the second planar portion 104 reflects the geometry of the first bond pad 142 of the semiconductor chip, i.e., a substantially rectangular shape with small notches in the lower corners. Since the first bond pads 142 occupy a substantial portion (e.g., at least 90% of the total area) of the upper surface area of the semiconductor die 140, the geometry of the second planar portion 104 is adapted for maximized heat extraction capability. At the same time, the semiconductor die 140 includes a second bond pad 152 that is outside the footprint of the interconnect clip 100. The second bond pad 152 may be a control terminal of the semiconductor die, e.g., a gate terminal, a base terminal, etc. Second bond pad 152 may be electrically connected to a separate one of leads 134, which is isolated from the lead to which interconnect clip 100 is connected, by an electrically conductive bond wire 154. The L-shaped configuration of the interconnect clip 100 enables access to the second bond pads 152 to make this electrical connection either before or after the interconnect clip 100 is installed.

Unlike the embodiment described with reference to fig. 5, the semiconductor package 200 of fig. 9 is configured such that the interconnect clip 100 is exposed at an underside 212 of the encapsulant 202 (as labeled in fig. 9D) corresponding to the interfacing side of the package 200. The interfacing side refers to the side where the leads 134 extend at least to the plane of the encapsulant, thereby enabling the package to be mounted to and electrically connected to a substrate (e.g., PCB). In this arrangement, the interconnect clip 100 acts as a bottom side cooling feature that can cooperate with a heat sink mechanism in the substrate. At the same time, the die pad 130 is exposed at the upper surface 204 of the encapsulant (as labeled in fig. 9D) and may mate with a second topside connected heat sink structure. Thus, the cooling side of the interconnect clip 100 is inverted as compared to the embodiment of FIG. 5.

Referring to fig. 10, the semiconductor package 200 of fig. 9 is depicted as the encapsulant 202 being opaque. The encapsulant 202 has a configuration similar to the previously described embodiments, wherein the encapsulant 202 completely covers the semiconductor die 140 and the upper surface 106 of the first section 102 of the interconnect clip 100 is exposed from the upper surface 204 of the encapsulant 202. The upper surface 106 of the first section 102 is exposed from the enclosure 202. In the depicted embodiment, the upper surface 106 of the first segment 102 is substantially coplanar with the underside 212 of the enclosure 202.

According to an embodiment, the encapsulant 202 of the semiconductor package of fig. 10 is formed by a two-step process, wherein the encapsulant 202 is initially formed to completely cover the interconnect clip 100, and the underside 212 of the encapsulant 202 is subsequently planarized (e.g., by polishing or grinding) until the upper surface 106 of the first segment 102 is exposed from the encapsulant 202 and is substantially coplanar with the encapsulant 202.

Similar to the previously described embodiments, the interconnect clip 100 in the package of fig. 10 provides a highly conductive transmission path between the semiconductor die 140 and the leads 134. At the same time, the interconnect clip 100 provides a highly thermally conductive transmission path at the exposed upper surface 106 of the first section 102, which allows for efficient heat extraction.

More generally, the principles described herein may be applied to a wide variety of package configurations. In general, these package configurations include any package design in which it is desirable to achieve heat dissipation at the upper surface of the semiconductor die, and/or in which the semiconductor die includes at least one bond pad that is face up and requires electrical connection. Examples of such package configurations include leaded packages, leadless packages, chip carrier packages, surface mount packages, stacked die packages, molded packages, cavity packages, and the like.

As used herein, the term "substantially" encompasses absolute compliance with a particular requirement and minor deviations from an absolute compliance requirement due to manufacturing process variations, assembly, and other factors that may cause deviation from a design target. The term "substantially" is intended to encompass any of these deviations, provided that the deviations are within process tolerances to achieve substantial compliance and that the components described herein are capable of functioning as required by the application.

The terms "electrically connected," "directly electrically connected," and the like, as used herein, describe a permanent low impedance connection between electrically connected elements, e.g., a direct contact between related elements or a low impedance connection achieved via a metal and/or highly doped semiconductor.

Spatially relative terms such as "below … …," "below … …," "below," "over," "upper," and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Furthermore, terms such as "first," "second," and the like, are also used to describe various elements, regions, segments, etc., and are not intended to be limiting. Like reference numerals refer to like elements throughout this specification.

As used herein, the terms "having," "including," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. As used herein, the singular articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Rather, the invention is limited only by the claims and their legal equivalents.