阅读说明：本技术 基于圆片重构工艺的三维堆叠封装散热结构及其制作方法 (Three-dimensional stacked package heat dissipation structure based on wafer reconstruction process and manufacturing method thereof ) 是由 朱思雄 李祝安 王成迁 于 2020-08-31 设计创作，主要内容包括：本发明公开一种基于圆片重构工艺的三维堆叠封装散热结构及其制作方法,属于微电子封装领域。基于圆片重构工艺的三维堆叠封装散热结构包括上层封装散热结构、下层封装散热结构和PCB；所述下层封装散热结构与所述PCB电连；所述上层封装散热结构与所述下层封装散热结构电连。本发明通过圆片重构工艺,构建了芯片到自然环境和芯片到PCB的双向散热通道,能有效解决三维堆叠结构的散热问题；采用塑封圆片重构工艺,不仅可以实现各层芯片封装的批量化生产,降低制造成本,而且可以实现各层封装结构的微型化,满足市场对系统三维堆叠封装结构的微型化要求。(The invention discloses a three-dimensional stacked package heat dissipation structure based on a wafer reconstruction process and a manufacturing method thereof, and belongs to the field of microelectronic packaging. The three-dimensional stacked packaging heat dissipation structure based on the wafer reconstruction process comprises an upper-layer packaging heat dissipation structure, a lower-layer packaging heat dissipation structure and a PCB; the lower-layer packaging heat dissipation structure is electrically connected with the PCB; the upper-layer packaging heat dissipation structure is electrically connected with the lower-layer packaging heat dissipation structure. According to the invention, through a wafer reconstruction process, bidirectional heat dissipation channels from a chip to a natural environment and from the chip to a PCB are constructed, so that the heat dissipation problem of a three-dimensional stacked structure can be effectively solved; by adopting the plastic package wafer reconstruction process, not only can the batch production of chip packages of all layers be realized, the manufacturing cost be reduced, but also the miniaturization of the packaging structures of all layers can be realized, and the miniaturization requirement of the market on the three-dimensional stacking packaging structure of the system can be met.)

1. A three-dimensional stacked package heat dissipation structure based on a wafer reconstruction process is characterized by comprising an upper-layer package heat dissipation structure, a lower-layer package heat dissipation structure and a PCB;

the lower-layer packaging heat dissipation structure is electrically connected with the PCB; the upper-layer packaging heat dissipation structure is electrically connected with the lower-layer packaging heat dissipation structure.

2. The three-dimensional stacked package heat dissipation structure based on wafer reconfiguration process as claimed in claim 1, wherein the upper package heat dissipation structure comprises a plurality of upper chips (101), the upper chips (101) are encapsulated by an upper molding compound (102) to form a first molding compound;

an upper RDL layer (103) is arranged on the front surface of the first plastic package body, and an upper solder ball (104) is manufactured on the UBM on the corresponding position of the upper RDL layer (103); the upper chip (101) is connected with the upper solder balls (104) through the upper RDL layer (103);

the back surface of the first plastic package body is provided with a first radiating fin (106) through a first heat conduction adhesive (105), and the first heat conduction adhesive (105) and the first radiating fin (106) cover the whole back surface of the first plastic package body.

3. The three-dimensional package-on-package heat dissipation structure based on wafer reconfiguration process as claimed in claim 2, wherein the curing temperature of the first thermal conductive adhesive glue (105) is higher than that of the upper layer molding compound (102).

4. The three-dimensional stacked package heat dissipation structure based on the wafer reconfiguration process as claimed in claim 1, wherein the lower package heat dissipation structure comprises a plurality of lower chips (201), the back surfaces of the lower chips (201) are attached with second heat dissipation fins (206) through second heat conductive adhesive glue (205), and are encapsulated by lower molding compound (202) to form a second molding body;

a lower RDL layer (203) is arranged on the front surface of the second plastic package body, and a lower solder ball (204) is manufactured on the UBM on the corresponding position of the lower RDL layer (203); the lower chip (201) is connected with the lower solder balls (204) through the lower RDL layer (203);

TMV through holes (207) are formed in the periphery of the second plastic package body, and copper (208) is filled in the TMV through holes through electroplating.

5. The three-dimensional package-on-package heat dissipation structure based on wafer reconfiguration process as claimed in claim 4, wherein the curing temperature of the second thermal adhesive glue (205) is higher than that of the lower layer molding compound (202).

6. A manufacturing method of a three-dimensional stacked package heat dissipation structure based on a wafer reconstruction process is characterized by comprising the following steps:

manufacturing an upper-layer packaging heat dissipation structure and a lower-layer packaging heat dissipation structure;

providing a PCB, carrying out reflow treatment on a lower solder ball in a lower-layer packaging heat dissipation structure corresponding to a pad of the PCB, and then carrying out reflow treatment on an upper solder ball in an upper-layer packaging heat dissipation structure corresponding to the pad of the lower-layer packaging structure.

7. The method for manufacturing a three-dimensional stacked package heat dissipation structure based on wafer reconfiguration process as claimed in claim 6, wherein the manufacturing of the upper package heat dissipation structure comprises:

curing and encapsulating the upper chips by using the upper-layer plastic package material to form a first plastic package body;

thinning the back of the first plastic package body until the back of the upper chip is exposed;

performing a series of electroplating, photoetching, developing and photoresist removing processes on the front surface of the first plastic package body by adopting a Fan-out process, and leading a power supply and a signal of an upper chip to an upper RDL layer;

carrying out reflow ball mounting on the UBM at the corresponding position of the upper RDL layer to form an upper solder ball;

and coating first heat conduction adhesive glue on the back surface of the first plastic package body, and then attaching the first radiating fin to the first heat conduction adhesive glue to obtain the upper-layer packaging radiating structure.

8. The method for fabricating a three-dimensional stacked package heat dissipation structure based on wafer reconstitution process as claimed in claim 6, wherein fabricating the lower package heat dissipation structure comprises:

coating second heat-conducting adhesive on the back surfaces of the lower-layer chips, and attaching second cooling fins to the second heat-conducting adhesive;

curing and encapsulating the lower-layer plastic package material to form a second plastic package body;

thinning the back of the second plastic package body until the back of the second radiating fin is exposed;

carrying out through hole forming treatment on the periphery of the second plastic package body to form a TMV through hole;

carrying out seed layer sputtering on the TMV through hole, and then electroplating and filling copper;

performing a series of electroplating, photoetching, developing and photoresist removing processes on the front surface of the second plastic package body by adopting a Fan-out process, and leading a power supply and a signal of a lower chip to a lower RDL layer;

and performing backflow ball planting on the UBM at the corresponding position of the lower RDL layer to form a lower solder ball, so as to obtain a lower packaging heat dissipation structure.

Technical Field

The invention relates to the technical field of microelectronic packaging, in particular to a three-dimensional stacked packaging heat dissipation structure based on a wafer reconstruction process and a manufacturing method thereof.

Background

The three-dimensional stacking packaging mode can obviously reduce the delay of each interconnection signal in the circuit, improve the high integration level of the system, meet the requirements of the market on the multifunction, the low processing cost and the like of the chip, and is the development direction of the future microelectronic packaging field. However, the miniaturization of the system-in-package structure will lead to a sharp increase in power density, so that each chip in the package structure generates a large amount of heat during stable operation, and is difficult to effectively dissipate, which is one of the main reasons for restricting the development of the miniaturized three-dimensional stacked package.

In view of the heat dissipation problem of the three-dimensional stacked package, the invention patent of patent application No. 201610810942.5 proposes a three-dimensional stacked package structure using air-cooling heat dissipation for heat dissipation. The packaging structure can realize better heat dissipation, but has the following problems:

(1) the chip is switched through a substrate form, so that the miniaturization of the size (length, width and thickness) of the package is limited, and the goal of a system for carrying out the miniaturization of a three-dimensional packaging structure cannot be achieved;

(2) the strength of the three-dimensional stacked packaging body is weakened, and the overall strength of the structure is reduced due to the fact that the substrates of all layers are provided with more through holes along the central line area, so that the structure is easy to bend under the actual working condition, and even breaks and fails;

(3) the traditional substrate type carrier plate is adopted, so that the assembly process of the three-dimensional stacking structure is complicated, and the production efficiency is low.

Disclosure of Invention

The invention aims to provide a three-dimensional stacked package heat dissipation structure based on a wafer reconstruction process and a manufacturing method thereof, so as to solve the heat dissipation problem of the traditional three-dimensional stacked structure.

In order to solve the technical problem, the invention provides a three-dimensional stacked package heat dissipation structure based on a wafer reconstruction process, which comprises an upper-layer package heat dissipation structure, a lower-layer package heat dissipation structure and a PCB (printed circuit board);

the lower-layer packaging heat dissipation structure is electrically connected with the PCB; the upper-layer packaging heat dissipation structure is electrically connected with the lower-layer packaging heat dissipation structure.

Optionally, the upper package heat dissipation structure includes a plurality of upper chips, and the upper chips are encapsulated by an upper molding compound to form a first molding compound;

an upper RDL layer is arranged on the front surface of the first plastic package body, and an upper solder ball is manufactured on a UBM (bump metallurgy) on the position corresponding to the upper RDL layer; the upper chip is connected with the upper solder balls through the upper RDL layer;

the back of the first plastic package body is provided with a first radiating fin in a sticking mode through a first heat conduction adhesive, and the first heat conduction adhesive and the first radiating fin cover the whole back of the first plastic package body.

Optionally, the curing temperature of the first heat-conducting adhesive is higher than that of the upper-layer molding compound.

Optionally, the lower-layer package heat dissipation structure includes a plurality of lower-layer chips, the back of the lower-layer chips is attached with second heat dissipation fins through second heat-conducting adhesive, and a second plastic package body is formed by encapsulating the lower-layer plastic package material;

a lower RDL layer is arranged on the front surface of the second plastic package body, and a lower solder ball is manufactured on a UBM on the corresponding position of the lower RDL layer; the lower chip is connected with the lower solder balls through the lower RDL layer;

TMV through holes are formed in the periphery of the second plastic package body, and copper is filled in the TMV through holes through electroplating.

Optionally, the curing temperature of the second heat-conducting adhesive is higher than that of the lower-layer molding compound.

The invention also provides a manufacturing method of the three-dimensional stacked package heat dissipation structure based on the wafer reconstruction process, which comprises the following steps:

manufacturing an upper-layer packaging heat dissipation structure and a lower-layer packaging heat dissipation structure;

providing a PCB, carrying out reflow treatment on a lower solder ball in a lower-layer packaging heat dissipation structure corresponding to a pad of the PCB, and then carrying out reflow treatment on an upper solder ball in an upper-layer packaging heat dissipation structure corresponding to the pad of the lower-layer packaging structure.

Optionally, the manufacturing of the upper package heat dissipation structure includes:

curing and encapsulating the upper chips by using the upper-layer plastic package material to form a first plastic package body;

thinning the back of the first plastic package body until the back of the upper chip is exposed;

performing a series of electroplating, photoetching, developing and photoresist removing processes on the front surface of the first plastic package body by adopting a Fan-out process, and leading a power supply and a signal of an upper chip to an upper RDL layer;

carrying out reflow ball mounting on the UBM at the corresponding position of the upper RDL layer to form an upper solder ball;

and coating first heat conduction adhesive glue on the back surface of the first plastic package body, and then attaching the first radiating fin to the first heat conduction adhesive glue to obtain the upper-layer packaging radiating structure.

Optionally, the manufacturing of the lower package heat dissipation structure includes:

coating second heat-conducting adhesive on the back surfaces of the lower-layer chips, and attaching second cooling fins to the second heat-conducting adhesive;

curing and encapsulating the lower-layer plastic package material to form a second plastic package body;

thinning the back of the second plastic package body until the back of the second radiating fin is exposed;

carrying out through hole forming treatment on the periphery of the second plastic package body to form a TMV through hole;

carrying out seed layer sputtering on the TMV through hole, and then electroplating and filling copper;

performing a series of electroplating, photoetching, developing and photoresist removing processes on the front surface of the second plastic package body by adopting a Fan-out process, and leading a power supply and a signal of a lower chip to a lower RDL layer;

and performing backflow ball planting on the UBM at the corresponding position of the lower RDL layer to form a lower solder ball, so as to obtain a lower packaging heat dissipation structure.

The three-dimensional stacked package heat dissipation structure based on the wafer reconstruction process and the manufacturing method thereof comprise an upper-layer package heat dissipation structure, a lower-layer package heat dissipation structure and a PCB; the lower-layer packaging heat dissipation structure is electrically connected with the PCB; the upper-layer packaging heat dissipation structure is electrically connected with the lower-layer packaging heat dissipation structure.

The invention has the following advantages:

(1) the vertical heat dissipation structure from the upper layer package to the lower layer package is realized, and the gaps between the layers can dissipate part of chip heat through natural convection; the redundant heat of the upper chip is transferred to the PCB through the lower package, so that double-channel heat dissipation from heat to air and the PCB is realized, and the heat dissipation effect is more obvious;

(2) the plastic package wafer reconstruction process is adopted, so that the existing process can be better compatible, and the practicability is high;

(3) the adopted wafer reconstruction process can simultaneously process a plurality of sets of chips by a plurality of processes, so the cost is lower.

Drawings

FIG. 1 is a schematic diagram of a three-dimensional stacked package heat dissipation structure based on a wafer reconfiguration process according to the present invention;

FIG. 2 is a schematic diagram of an upper layer molding compound encapsulating an upper layer chip to form a first molding compound;

FIG. 3 is a schematic view of thinning the back side of the first plastic package body;

FIG. 4 is a schematic diagram of the power and signals of the upper chip being directed to the upper RDL layer;

FIG. 5 is a schematic diagram of forming upper solder balls by performing reflow ball-mounting on UBMs at corresponding positions on the upper RDL layer;

FIG. 6 is a schematic view of a first thermally conductive adhesive applied to the back surface of a first molded body;

FIG. 7 is a schematic diagram of an upper package heat dissipation structure;

FIG. 8 is a schematic view of a second heat conducting adhesive applied to the backside of the lower chip and a second heat spreader attached thereto;

FIG. 9 is a schematic view of a second molding compound encapsulated with an underlying molding compound;

fig. 10 is a schematic view of thinning the back side of the second plastic package body;

FIG. 11 is a schematic view of a TMV via formed by a via molding process performed on the periphery of the second plastic package body;

FIG. 12 is a schematic of seed layer sputtering of a TMV via followed by an electroplated fill of copper;

FIG. 13 is a schematic drawing showing the power and signals of the lower chip being routed to the lower RDL layer;

fig. 14 is a schematic diagram of a heat dissipation structure of a lower package.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be embodied in other specific forms than those described herein, and it will be apparent to those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the present invention.

Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, three-dimensional dimensions of length, width and depth should be included in the implementation.