阅读说明：本技术 电子封装件及其承载基板与制法 (Electronic package, bearing substrate thereof and manufacturing method ) 是由 何祈庆 马伯豪 于 2019-05-16 设计创作，主要内容包括：一种电子封装件及其承载基板与制法,该制法包括设置至少一线路构件于第一线路结构上,再形成包覆层于该第一线路结构上以包覆该线路构件,之后形成第二线路结构于该包覆层上,且令该第二线路结构电性连接该线路构件,以经由现有封装制程将该线路构件嵌埋于该包覆层中,以增加布线区,故对于大尺寸板面的封装基板的需求,不仅具有量产性且制程成本低。(An electronic package, its bearing substrate and its making method, the making method includes setting at least a line member on the first line structure, forming a coating layer on the first line structure to coat the line member, then forming the second line structure on the coating layer, and making the second line structure electrically connected with the line member, so that the line member is embedded in the coating layer by the existing packaging process to increase the wiring area, therefore, the requirement of the packaging substrate with large-size plate surface is not only mass production but also low process cost.)

1. A carrier substrate, comprising:

a first circuit structure having a first side and a second side opposite to each other;

at least one line member disposed on a first side of the first line structure;

a cladding layer formed on the first side of the first circuit structure to clad the circuit member; and

a second circuit structure formed on the cladding layer and electrically connected to the circuit member.

2. The carrier substrate of claim 1, wherein the circuit member is electrically connected to the second circuit structure via a plurality of electrical conductors.

3. The carrier substrate of claim 1, further comprising conductive pillars formed in the cladding layer for electrically connecting the first circuit structures and the second circuit structures.

4. The carrier substrate of claim 1, further comprising a plurality of conductive elements formed on the second side of the first circuit structure.

5. The carrier substrate of claim 1, further comprising a plurality of conductive bumps formed on the second circuit structure.

6. The carrier substrate of claim 1, wherein the cladding layer covers at least four of the circuit members.

7. The carrier substrate according to claim 1, wherein the circuit member is a package substrate.

8. The carrier substrate of claim 1, wherein the circuit member is a coreless circuit structure.

9. The carrier substrate of claim 1, wherein the circuit member has a through-silicon via structure.

10. An electronic package, comprising:

a carrier substrate according to any one of claims 1 to 9; and

at least one electronic element arranged on the second circuit structure.

11. The electronic package according to claim 10, wherein the electronic component is an active component, a passive component or a combination thereof.

12. The electronic package according to claim 10, wherein the electronic component is electrically connected to the second circuit structure.

13. The electronic package of claim 10, further comprising a heat spreader disposed on the second circuit structure.

14. The electronic package of claim 13, wherein the heat spreader contacts the electronic component.

15. A method for fabricating a carrier substrate, comprising:

providing a first circuit structure with a first side and a second side which are opposite;

disposing at least one circuit member on a first side of the first circuit structure;

forming a cladding layer on a first side of the first circuit structure such that the cladding layer wraps the circuit member; and

forming a second circuit structure on the cladding layer, and electrically connecting the second circuit structure to the circuit member.

16. The method of claim 15, wherein the circuit member is electrically connected to the second circuit structure via a plurality of electrical conductors.

17. The method as claimed in claim 15, further comprising forming a conductive pillar on the first side of the first circuit structure, and covering the conductive pillar with the coating layer to electrically connect the first circuit structure and the second circuit structure through the conductive pillar.

18. The method of claim 15, further comprising forming a plurality of conductive elements on the second side of the first circuit structure.

19. The method for fabricating a carrier substrate according to claim 15, further comprising forming a plurality of conductive bumps on the second circuit structure.

20. The method of claim 15, wherein the cladding layer covers at least four of the circuit members.

21. The method of claim 15, wherein the circuit member is a package substrate.

22. The method of claim 15, wherein the circuit member is a coreless circuit structure.

23. The method of claim 15, wherein the circuit member has a through-silicon via structure.

24. A method of fabricating an electronic package, comprising:

providing a carrier substrate according to any one of claims 1 to 9; and

at least one electronic element is disposed on the second circuit structure.

25. The method of claim 24, wherein the electronic device is an active device, a passive device or a combination thereof.

26. The method of claim 24, wherein the electronic component is electrically connected to the second circuit structure.

27. The method of claim 24, further comprising disposing a heat spreader over the second circuit structure.

28. The method of claim 27, wherein the heat spreader contacts the electronic component.

Technical Field

The present invention relates to a package structure, and more particularly, to an electronic package, a carrier substrate thereof and a method for fabricating the same.

Background

With the increasing demand for Electronic products in terms of functions and processing speed, the semiconductor chip, which is the core component of the Electronic product, needs to have higher density circuit Components (Electronic Components) and Electronic circuits (Electronic circuits), so that the semiconductor chip will generate a large amount of heat energy during operation, and the encapsulant covering the semiconductor chip is a poor heat-transfer material with a thermal conductivity of only 0.8Wm-1k-1 (i.e., the dissipation efficiency of heat energy is not good), so that the generated heat energy cannot be effectively dissipated, which may cause damage to the semiconductor chip or cause product reliability problems.

In order to dissipate Heat energy into the atmosphere, a Heat Sink (Heat Sink or Heat Spreader) is usually disposed in the semiconductor package structure, and the Heat Sink is bonded to the back surface of the semiconductor chip via a Heat dissipation adhesive, such as a Thermal Interface Material (TIM), so as to dissipate the Heat generated by the semiconductor chip via the Heat dissipation adhesive and the Heat Sink.

As shown in fig. 1, a conventional method for manufacturing a semiconductor package 1 first mounts a semiconductor chip 11 on a package substrate 10 by flip-chip bonding (i.e., via conductive bumps 110 and an underfill 111) on an active surface 11a thereof, and then reflows a heat sink 13 on a non-active surface 11b of the semiconductor chip 11 via a TIM layer 12 (which includes a solder layer and a flux) on a top surface 130 thereof, and mounts support legs 131 of the heat sink 13 on the package substrate 10 via an adhesive layer 14. Then, a molding operation is performed to encapsulate the semiconductor chip 11 and the heat sink 13 with an encapsulant (not shown), and the top plate 130 of the heat sink 13 is exposed to the outside of the encapsulant and directly contacts the atmosphere. Then, the semiconductor package 1 is mounted on a circuit board 8 via a plurality of solder balls 15 with its package substrate 10.

In operation, the heat generated by the semiconductor chip 11 is conducted to the top sheet 130 of the heat sink 13 through the non-active surface 11b and the TIM layer 12 to dissipate the heat to the outside of the semiconductor package 1.

However, with the development of industrial applications, the development is gradually towards the trend of large-scale package specifications in recent years for high-density lines/high transmission speed/high lamination number/large-scale design of high-order products.

However, in the conventional semiconductor package 1, there is a demand for a package substrate 10 having a large board surfaceFor example, the plate body size is 100 x 100 mm²The requirement of (2) has no mass production, and the manufacturing cost of a single plate body is extremely high, so that the market competitiveness is not achieved.

Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package, a carrier substrate thereof and a fabrication method thereof, which not only have mass productivity but also have low manufacturing cost.

The bearing substrate of the invention comprises: a first circuit structure having a first side and a second side opposite to each other; at least one line member disposed on a first side of the first line structure; a cladding layer formed on the first side of the first circuit structure to clad the circuit member; and a second circuit structure formed on the cladding layer and electrically connected to the circuit member.

The invention also provides a method for manufacturing the bearing substrate, which comprises the following steps: providing a first circuit structure, wherein the first circuit structure is provided with a first side and a second side which are opposite; disposing at least one circuit member on a first side of the first circuit structure; forming a cladding layer on a first side of the first circuit structure such that the cladding layer wraps the circuit member; and forming a second circuit structure on the cladding layer, wherein the second circuit structure is electrically connected with the circuit member.

In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is electrically connected to the second circuit structure through a plurality of conductors.

In the above-mentioned carrier substrate and the manufacturing method thereof, a conductive pillar is formed on the first side of the first circuit structure, so that the conductive pillar is wrapped by the cladding layer and electrically connected to the first circuit structure and the second circuit structure.

In the foregoing carrier substrate and the method for fabricating the same, a plurality of conductive elements are formed on the second side of the first circuit structure.

In the foregoing carrier substrate and the method for fabricating the same, a plurality of conductive bumps are formed on the second circuit structure.

In the above-mentioned carrier substrate and the manufacturing method thereof, the cladding layer covers at least four of the circuit members.

In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is a package substrate.

In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is a circuit structure without a core layer.

In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member has a through-silicon via structure.

The present invention also provides an electronic package comprising: a carrier substrate; and at least one electronic element arranged on the second circuit structure.

The invention further provides a method for manufacturing an electronic package, comprising: providing the bearing substrate; and arranging at least one electronic element on the second circuit structure.

In the electronic package and the method for fabricating the same, the electronic device is an active device, a passive device or a combination thereof.

In the electronic package and the manufacturing method thereof, the electronic element is electrically connected to the second circuit structure.

In the electronic package and the method for manufacturing the same, a heat sink is disposed on the second circuit structure. For example, the heat sink contacts the electronic component.

In view of the above, in the electronic package, the carrier substrate and the manufacturing method thereof of the present invention, the circuit member is disposed on the first circuit structure and embedded in the cladding layer to increase the wiring area, so compared with the prior art, the present invention has mass productivity and the manufacturing cost of a single carrier substrate is very low, thereby having great market competitiveness.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package.

Fig. 2A to 2E are schematic cross-sectional views illustrating a method for fabricating a carrier substrate according to the present invention.

Fig. 2F to fig. 2G are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention.

FIG. 2G' is a schematic cross-sectional view of another embodiment of FIG. 2G.

Description of the symbols

1 semiconductor package 10 package substrate

11 active surface of semiconductor chip 11a,30a

11b,30b non-active side 110,29 conductive bump

111,33 primer 12 TIM layer

13,3a heat sink 130 topsheet

131,31 support the foot 14,91,310 adhesive layer

15 solder ball 2, 2' carrier substrate

2a line plate 20 first line structure

20a first side 20b second side

200 first insulating layer 201 first line redistribution layer

21 line member 21a top surface

21b bottom surface 210 wiring layer

211 insulator 212 protective film

213 Electrical contact pad 22 conductor

22a,23a end face 23 conductive post

24 bonding layer 25 cladding

26 second line structure 260 second insulating layer

261 second wire redistribution layer 27 conductive element

28 insulating protective layer 290 under bump metal layer

30 electronic component 300 electrode pad

32 Heat spreader 320 thermally conductive interface layer

4 electronic device 8 circuit board

9 bearing plate 90 is from type layer

S cut path 3 electronic package.

Detailed Description

The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.

It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.

Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing the carrier substrate 2 according to the present invention.

As shown in fig. 2A, a wiring board block 2A is provided, which includes a plurality of wiring members 21.

In the present embodiment, the circuit member 21 is a circuit structure (shown as a core type) such as a package substrate (substrate) having a core layer and a circuit structure or a coreless (core type) circuit structure, and includes an insulator 211 and a plurality of circuit layers 210 combined with the insulator 211, such as a fan-out (fan out) redistribution layer (RDL), and the insulator 211 is formed of a dielectric material, such as Polyoxadiazole (PBO), Polyimide (PI), Prepreg (PP), or the like; alternatively, the circuit member 21 may have a Through Silicon Via (TSV) structure. It should be understood that the circuit member 21 may also be a board with other configuration wires, such as an organic board (organic material), a semiconductor board (silicon), a ceramic board (ceramic), or other carrier board with metal wires (routing), but is not limited to the above.

In addition, the circuit member 21 is combined with and electrically connected to a plurality of conductors 22, and the conductors 22 are, for example, spherical shapes such as conductive traces and solder balls, or columnar shapes of metal materials such as copper columns and solder bumps, or nail shapes (stud) made by a wire bonding machine, but not limited thereto. In addition, a protection film 212, such as a passivation material, may be formed on the top surface 21a of the circuit member 21, such that a portion of the circuit layer 210 (e.g., the plurality of electrical contact pads 213) is exposed from the protection film 212, and the conductor 22 is formed on the electrical contact pads 213 and protrudes from the protection film 212.

As shown in fig. 2B, the circuit board block 2a is cut to obtain a plurality of circuit components 21, and one or more (more than four as shown in the figure) circuit components 21 are disposed on a first circuit structure 20, wherein the first circuit structure 20 is formed on the carrier plate 9 and has a first side 20a and a second side 20B opposite to each other, the first circuit structure 20 is bonded to the carrier plate 9 with the second side 20B thereof, and the circuit components 21 are disposed on the first side 20a of the first circuit structure 20. On the other hand, a plurality of conductive pillars 23 electrically connected to the first circuit structure 20 are also formed on the first side 20a of the first circuit structure 20, wherein the arrangement sequence of the circuit member 21 and the conductive pillars 23 can be selected according to the requirement.

In the present embodiment, the first circuit structure 20 includes at least a first insulating layer 200 and a first redistribution layer (RDL)201 disposed on the first insulating layer 200. For example, the material forming the first redistribution layer 201 is copper, and the material forming the first insulating layer 200 is a dielectric material such as poly-p-xylylene (PBO), Polyimide (PI), prepreg (PP), or the like.

In addition, the carrier 9 is, for example, a circular plate of semiconductor material (e.g., silicon or glass), on which a release layer 90 and an adhesive layer 91 are sequentially formed by coating, so that the first circuit structure 20 is disposed on the adhesive layer 91.

The conductive posts 23 are disposed on the first redistribution layer 201 and electrically connected to the first redistribution layer 201, and the material forming the conductive posts 23 is a metal material such as copper or a solder material.

In addition, the circuit member 21 is adhered to the first side 20a of the first circuit structure 20 by the bottom surface 21b thereof through a bonding layer 24 such as an adhesive material.

As shown in fig. 2C, a cladding layer 25 is formed on the first side 20a of the first circuit structure 20, so that the cladding layer 25 covers the circuit member 21, the bonding layer 24, the plurality of conductive bodies 22 and the plurality of conductive columns 23, and then the end surfaces 23a of the conductive columns 23 and the end surfaces 22a of the conductive bodies 22 are exposed out of the cladding layer 25 through a leveling process, so that the outer surface of the cladding layer 25 is flush with the end surfaces 23a of the conductive columns 23 and the end surfaces 22a of the conductive bodies 22.

In the present embodiment, the cover layer 25 is an insulating material, such as an encapsulant of epoxy resin, and can be formed on the first side 20a of the first circuit structure 20 by pressing (laminating) or molding (molding).

In addition, the planarization process removes a portion of the conductive pillar 23, a portion of the conductive body 22, and a portion of the cladding layer 25 by polishing.

As shown in fig. 2D, a second circuit structure 26 is formed on the cladding layer 25, and the second circuit structure 26 electrically connects the conductive pillar 23 and the conductive body 22.

In the embodiment, the second circuit structure 26 includes a plurality of second insulating layers 260 and a plurality of second redistribution layers (RDLs) 261 disposed on the second insulating layers 260, and the outermost second insulating layer 260 can be used as a solder mask layer, so that the outermost second redistribution layer 261 is exposed to the solder mask layer. Alternatively, the second circuit structure 26 may only include a single second insulating layer 260 and a single second redistribution layer 261.

In addition, the second redistribution layer 261 is formed of copper, and the second insulating layer 260 is formed of a dielectric material such as poly-p-xylylene (PBO), Polyimide (PI), Prepreg (PP), or the like.

As shown in fig. 2E, the carrier 9 and the release layer 90 and the adhesive layer 91 thereon are removed to expose the first circuit structure 20, thereby forming the carrier substrate 2 of the present invention.

Therefore, in the manufacturing method of the carrier substrate 2 of the present invention, the circuit member 21 is embedded in the cladding layer 25 mainly by the conventional packaging process to increase the wiring area, so compared with the prior art, the manufacturing method of the carrier substrate 2 of the present invention has mass productivity and the manufacturing cost of a single carrier substrate 2 is very low, thereby having market competitiveness.

As shown in fig. 2F, the carrier substrate 2 may be disposed with one or more electronic components 30 on the outermost second redistribution layer 261 to form an electronic package 3, and the carrier substrate 2 may be disposed with a plurality of conductive elements 27, such as solder balls, on the second side 20b of the first circuit structure 20.

In the present embodiment, an insulating passivation layer 28, such as a solder mask, may be formed on the second side 20b of the first circuit structure 20, and a plurality of openings are formed on the insulating passivation layer 28, so that the first redistribution layer 201 is exposed to the plurality of openings for combining with a plurality of conductive elements 27.

In addition, the electronic component 30 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the electronic component 30 is a semiconductor chip having an active surface 30a and an inactive surface 30b opposite to each other, and the electrode pads 300 of the active surface 30a are disposed on the second redistribution layer 261 in a flip-chip manner via a plurality of conductive bumps 29 such as solder material and electrically connected to the second redistribution layer 261, and the conductive bumps 29 are covered with the underfill 33; alternatively, the non-active surface 30b of the electronic component 30 is disposed on the second circuit structure 26 and electrically connected to the second redistribution layer 261 by bonding wires (not shown); or electrically connected to the second redistribution layer 261 through a conductive material (not shown) such as conductive paste or solder. However, the manner of electrically connecting the electronic component 30 to the second redistribution layer 261 is not limited to the above.

Also, an Under Bump Metallurgy (UBM) 290 may be formed on the outermost second redistribution layer 261 to facilitate bonding the conductive Bump 29.

As shown in fig. 2G, a singulation process is performed along the cutting path S shown in fig. 2F, so that the carrier substrate 2 is mounted on an electronic device 4, such as a package structure or a circuit board, via the conductive element 27 in a subsequent process.

In this embodiment, the electronic package 3 may be configured with a heat sink 3a according to requirements, which includes a supporting leg 31 and a heat dissipation body 32, and the supporting leg 31 is bonded to the second circuit structure 26 through an adhesive layer 310, and the heat dissipation body 32 of the heat sink 3a is bonded to the electronic component 30 through a heat conduction interface layer 320. For example, the plurality of support legs 31 are integrally formed on the radiator 32; alternatively, the plurality of support legs 31 may be provided to the radiator 32 in a bonded manner.

In addition, the thermal interface layer 320 can also be formed on the heat spreader 32 first, and then the heat spreader 32 is bonded to the non-active surface 30b of the electronic component 30 through the thermal interface layer 320. Similarly, the adhesive layer 310 may also be formed on the supporting legs 31 first, and then the supporting legs 31 are bonded to the second circuit structure 26 through the adhesive layer 310.

In addition, in order to enhance the adhesion strength between the thermal interface layer 320 and the electronic component 30, the surface of the electronic component 30 may be coated with Gold (so-called Coating Gold On Chip Back). Specifically, a gold layer is formed on the non-active surface 30b of the electronic component 30 and the surface of the heat spreader 32, and further a flux (flux) is used to facilitate the adhesion of the thermal interface layer 320 to the gold layer.

In addition, in other embodiments, the carrier substrate 2 'may omit the fabrication of the conductive pillars 23, as shown in fig. 2G'.

The present invention also provides an electronic package 3, comprising a carrier substrate 2, 2' and at least one electronic component 30, wherein the carrier substrate 2 comprises: a first circuit structure 20, a circuit member 21, a covering layer 25 and a second circuit structure 26, and the electronic component 30 is disposed on the second circuit structure 26.

The first circuit structure 20 has a first side 20a and a second side 20b opposite to each other, a plurality of conductive pillars 23 may be formed on the first side 20a as required, and the conductive pillars 23 are electrically connected to the first circuit structure 20.

The circuit member 21 is disposed on the first side 20a of the first circuit structure 20, and the circuit member 21 is coupled to and electrically connected to the plurality of conductors 22.

The cladding layer 25 is formed on the first side 20a of the first circuit structure 20, so that the cladding layer 25 covers the circuit member 21, the conductive body 22 and the conductive post 23, and the end surface 23a of the conductive post 23 and the end surface 22a of the conductive body 22 are exposed out of the cladding layer 25.

The second circuit structure 26 is formed on the cladding 25, and the second circuit structure 26 is electrically connected to the conductive pillar 23 and the circuit member 21 through the conductive body 22.

In one embodiment, the carrier substrate 2, 2' further includes a plurality of conductive elements 27 formed on the second side 20b of the first circuit structure 20.

In one embodiment, the carrier substrate 2, 2' further includes a plurality of conductive bumps 29 formed on the second circuit structure 26.

In one embodiment, the electronic component 30 is an active component, a passive component, or a combination thereof.

In one embodiment, the electronic component 30 is electrically connected to the second circuit structure 26.

In one embodiment, the electronic package 3 further includes a heat sink 3a disposed on the second circuit structure 26. For example, the heat sink 3a contacts the electronic component 30.

In summary, in the electronic package, the carrier substrate and the manufacturing method thereof of the present invention, the circuit member is disposed on the first circuit structure and embedded in the cladding layer through the conventional packaging process to increase the wiring area, so that the carrier substrate of the present invention has mass productivity and the manufacturing cost of a single carrier substrate is very low for the requirement of a large-sized package substrate, thereby having great market competitiveness.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.