Electronic package, bearing substrate thereof and manufacturing method
阅读说明:本技术 电子封装件及其承载基板与制法 (Electronic package, bearing substrate thereof and manufacturing method ) 是由 何祈庆 马伯豪 薛宇廷 曾景鸿 陆冠华 张宏达 于 2019-08-08 设计创作,主要内容包括:本发明涉及一种电子封装件及其承载基板与制法,包括设置至少一线路构件于第一线路结构上,再形成包覆层于该第一线路结构上以包覆该线路构件,之后形成第二线路结构于该包覆层上,且令该第二线路结构电性连接该线路构件,以经由现有封装制程将该线路构件嵌埋于该包覆层中,以增加布线区,故对于大尺寸板面的封装基板的需求,不仅具有量产性且制程成本低。(The invention relates to an electronic package, a bearing substrate and a manufacturing method thereof, which comprises the steps of arranging at least one circuit component on a first circuit structure, forming a coating layer on the first circuit structure to coat the circuit component, then forming a second circuit structure on the coating layer, and enabling the second circuit structure to be electrically connected with the circuit component, so that the circuit component is embedded in the coating layer through the existing packaging process to increase a wiring area, therefore, the requirement of a packaging substrate with a large-size plate surface is met, and the electronic package not only has mass production performance, but also has low manufacturing cost.)
1. A carrier substrate, comprising:
a first circuit structure having a first side and a second side opposite to each other;
at least one line member disposed on a first side of the first line structure; and
a cladding layer formed on the first side of the first circuit structure to clad the circuit member.
2. The carrier substrate of claim 1, further comprising a second circuit structure formed on the cover layer and electrically connected to the circuit member.
3. The carrier substrate of claim 2, wherein the circuit member is electrically connected to the second circuit structure via a plurality of electrical conductors.
4. The carrier substrate of claim 2, further comprising conductive pillars formed in the cladding layer for electrically connecting the first circuit structures and the second circuit structures.
5. The carrier substrate of claim 2, further comprising a plurality of conductive bumps formed on the second circuit structure.
6. The carrier substrate of claim 1, wherein the cladding layer covers at least four of the circuit members.
7. The carrier substrate according to claim 1, wherein the circuit member is a package substrate.
8. The carrier substrate of claim 1, wherein the circuit member is a coreless circuit structure.
9. The carrier substrate of claim 1, wherein the circuit member has a through-silicon via structure.
10. The carrier substrate of claim 1, wherein the circuit member is electrically connected to the first circuit structure via a plurality of electrical conductors.
11. An electronic package, comprising:
a carrier substrate according to any one of claims 1 to 10; and
at least one electronic element is arranged on one of the first side and the second side of the bearing substrate.
12. The electronic package according to claim 11, wherein the electronic component is an active component, a passive component or a combination thereof.
13. The electronic package according to claim 11, further comprising a plurality of conductive elements disposed on one of the first and second sides of the carrier substrate on which the electronic component is not disposed.
14. The electronic package of claim 11, further comprising a heat spreader disposed on the carrier substrate.
15. The electronic package of claim 14, wherein the heat spreader contacts the electronic component.
16. A method for fabricating a carrier substrate, comprising:
providing a first circuit structure with a first side and a second side which are opposite;
disposing at least one circuit member on a first side of the first circuit structure; and
forming a cladding layer on the first side of the first circuit structure such that the cladding layer covers the circuit member.
17. The method of claim 16, further comprising forming a second circuit structure on the cover layer and electrically connecting the second circuit structure to the circuit member.
18. The method of claim 17, wherein the circuit member is electrically connected to the second circuit structure via a plurality of electrical conductors.
19. The method as claimed in claim 17, further comprising forming a conductive pillar on the first side of the first circuit structure, and covering the conductive pillar with the coating layer to electrically connect the first circuit structure and the second circuit structure through the conductive pillar.
20. The method of claim 17, further comprising forming a plurality of conductive bumps on the second circuit structure.
21. The method of claim 16, wherein the cladding layer covers at least four of the circuit members.
22. The method of claim 16, wherein the circuit member is a package substrate.
23. The method of claim 16, wherein the circuit member is a coreless circuit structure.
24. The method of claim 16, wherein the circuit member has a through-silicon via structure.
25. The method of claim 16, wherein the circuit member is electrically connected to the first circuit structure via a plurality of electrical conductors.
26. A method of fabricating an electronic package, comprising:
providing a carrier substrate according to any one of claims 1 to 10; and
at least one electronic element is arranged on one of the first side and the second side of the bearing substrate.
27. The method of claim 26, wherein the electronic component is an active component, a passive component, or a combination thereof.
28. The method of claim 26, further comprising forming a plurality of conductive elements on one of the first and second sides of the carrier substrate not having the electronic component disposed thereon.
29. The method of claim 26, further comprising disposing a heat spreader on the carrier substrate.
30. The method of claim 29, wherein the heat spreader contacts the electronic component.
Technical Field
The present invention relates to a package structure, and more particularly, to an electronic package, a carrier substrate thereof and a method for fabricating the same.
Background
With the increasing demand for Electronic products in terms of functions and processing speed, the semiconductor chip, which is the core component of the Electronic product, needs to have higher density circuit Components (Electronic Components) and Electronic circuits (Electronic circuits), so that the semiconductor chip will generate a large amount of heat energy during operation, and the encapsulant covering the semiconductor chip is a poor heat-transfer material with a thermal conductivity of only 0.8Wm-1k-1 (i.e., the dissipation efficiency of heat energy is not good), so that the semiconductor chip will be damaged or the product reliability will be affected if the generated heat energy cannot be dissipated effectively.
In order to dissipate Heat energy into the atmosphere, a Heat Sink (Heat Sink or Heat Spreader) is usually disposed in the semiconductor package structure, and the Heat Sink is bonded to the back surface of the semiconductor chip via a Heat dissipation adhesive, such as a Thermal Interface Material (TIM), so as to dissipate the Heat generated by the semiconductor chip via the Heat dissipation adhesive and the Heat Sink.
As shown in fig. 1, a conventional method for manufacturing a semiconductor package 1 includes first mounting a
In operation, the heat generated by the
However, with the development of industrial applications, the development is gradually towards the trend of large-scale package specifications in recent years for high-density lines/high transmission speed/high lamination number/large-scale design of high-order products.
However, in the conventional semiconductor package 1, there is a need for a
Therefore, how to overcome the above problems of the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package, a carrier substrate thereof and a fabrication method thereof, which can reduce the fabrication cost.
The bearing substrate of the invention comprises: a first circuit structure having a first side and a second side opposite to each other; at least one line member disposed on a first side of the first line structure; and a cladding layer formed on the first side of the first circuit structure to clad the circuit member.
The invention also provides a method for manufacturing the bearing substrate, which comprises the following steps: providing a first circuit structure with a first side and a second side which are opposite; disposing at least one circuit member on a first side of the first circuit structure; and forming a cladding layer on the first side of the first circuit structure to make the cladding layer clad the circuit member.
In the above-mentioned carrier substrate and the manufacturing method thereof, a second circuit structure is formed on the cladding layer, and the second circuit structure is electrically connected to the circuit member. For example, the circuit member is electrically connected to the second circuit structure via a plurality of electrical conductors. And forming a conductive pillar on the first side of the first circuit structure to make the cladding layer cover the conductive pillar, and electrically connecting the conductive pillar with the first circuit structure. Alternatively, the method may include forming a plurality of conductive bumps on the second circuit structure.
In the above-mentioned carrier substrate and the manufacturing method thereof, the cladding layer covers at least four of the circuit members.
In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is a package substrate.
In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is a circuit structure without a core layer.
In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member has a through-silicon via structure.
In the above-mentioned carrier substrate and the manufacturing method thereof, the circuit member is electrically connected to the first circuit structure through a plurality of conductors.
The present invention also provides an electronic package comprising: a carrier substrate; and at least one electronic element arranged on one of the first side and the second side of the bearing substrate.
The invention further provides a method for manufacturing an electronic package, comprising: providing the bearing substrate; and disposing at least one electronic component on one of the first side and the second side of the carrier substrate.
In the electronic package and the method for fabricating the same, the electronic device is an active device, a passive device or a combination thereof.
In the electronic package and the method for fabricating the same, a plurality of conductive elements are formed on the first side and the second side of the carrier substrate without the electronic element.
In the electronic package and the method for manufacturing the same, a heat sink is disposed on the carrier substrate. For example, the heat sink contacts the electronic component.
As can be seen from the above, in the electronic package, the carrier substrate thereof and the manufacturing method thereof of the present invention, the circuit member is disposed on the first circuit structure and embedded in the cladding layer to increase the wiring area, so compared with the prior art, the present invention has mass productivity and the manufacturing cost of a single carrier substrate is very low, thereby having great market competitiveness.
In addition, the circuit structure is used for adjusting the number of the wiring layers of the circuit component, so that the number of the wiring layers of the circuit component is reduced, and the manufacturing yield of the circuit component is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package.
Fig. 2A to 2E are schematic cross-sectional views illustrating a method for fabricating a carrier substrate according to a first embodiment of the invention.
Fig. 2F to fig. 2G are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a first embodiment of the invention.
FIG. 2G' is a schematic cross-sectional view of another embodiment of FIG. 2G.
FIG. 2G' is a schematic cross-sectional view of another embodiment of FIG. 2E.
Fig. 3A to 3B are schematic cross-sectional views illustrating a method for fabricating a carrier substrate according to a second embodiment of the invention.
Fig. 3C to fig. 3D are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to a second embodiment of the invention.
Description of the symbols
1
11 active surface of
11b,30b
111,33
13,3a heat sink 130 topsheet
131,31 support the
15
20a
200 first
21
211
213
22a,
24
26
261 second
28 insulating
3, 3'
300
320 heat conducting interface layer 4 electronic device
8
90 cutting the path from the release layer S.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing a
As shown in fig. 2A, a wiring board block 2A is provided, which includes a plurality of
In the embodiment, the
In addition, the
As shown in fig. 2B, the
In the present embodiment, the
In addition, the
The
In addition, the
As shown in fig. 2C, a
In the present embodiment, the
In addition, the planarization process removes a portion of the
As shown in fig. 2D, a
In the embodiment, the
In addition, the
As shown in fig. 2E, the
Therefore, in the manufacturing method of the
In addition, the first circuit structure 20 (or the second circuit structure 26) is used to adjust the number of wiring layers of the
As shown in fig. 2F, the
In the present embodiment, an insulating
In addition, the
In addition, an Under Bump Metallurgy (UBM) 290 may be formed on the outermost
As shown in fig. 2G, a singulation process is performed along the cutting path S shown in fig. 2F, so that the
In the present embodiment, the electronic package 3 may be configured with a
In addition, the
In addition, in order to enhance the adhesion strength between the
In addition, in other embodiments, the carrier substrate 2 'may omit the fabrication of the
Fig. 3A to 3B are schematic cross-sectional views illustrating a method for manufacturing a carrier substrate 3A according to a second embodiment of the invention. The difference between this embodiment and the first embodiment is that the process of the second circuit structure is omitted, and the other processes are substantially the same, so the same parts are not described below.
As shown in fig. 3A, the process shown in fig. 2A to 2C is performed by using the
As shown in fig. 3B, the
Therefore, in the manufacturing method of the
In addition, the
As shown in fig. 3C, the
As shown in fig. 3D, a singulation process is performed along the dicing path S shown in fig. 3C to obtain the electronic package 3'.
The present invention further provides an electronic package 3,3 'comprising a
The
The
The
In one embodiment, the
In one embodiment, the electronic package 3,3 'further includes a plurality of
In one embodiment, the
In one embodiment, the
In one embodiment, the electronic package 3 further includes a
In summary, in the electronic package, the carrier substrate and the manufacturing method thereof of the present invention, the circuit member is disposed on the first circuit structure and embedded in the cladding layer through the conventional packaging process to increase the wiring area, so that the carrier substrate of the present invention has mass productivity and the manufacturing cost of a single carrier substrate is very low for the requirement of a large-sized package substrate, thereby having great market competitiveness.
In addition, the circuit structure can be used for adjusting the number of wiring layers of the circuit component, so that the number of wiring layers of the circuit component is reduced, and the manufacturing yield of the circuit component is improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
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