阅读说明：本技术 具有高电阻率热障壁的存储器装置 (Memory device with high resistivity thermal barrier ) 是由 D·R·埃科诺米 郑鹏园 于 2020-04-28 设计创作，主要内容包括：本申请案涉及具有高电阻率热障壁的存储器装置。在一些实例中,障壁材料可以定位于存储器单元区、氧化物区和/或硅穿孔TSV上方。所述障壁可包含所述存储器单元区上方的第一区和所述TSV上方的第二区。可对所述障壁施加例如等离子体处理的工艺,这可导致所述第一区和第二区具有不同热电阻率(例如,不同密度)。因此,由于所述不同热电阻率,所述存储器单元可热隔绝于在所述存储器装置中生成的热能。(The present application relates to memory devices having high resistivity thermal barriers. In some examples, a barrier material may be positioned over the memory cell regions, the oxide regions, and/or the through-silicon vias TSVs. The barrier may include a first region over the memory cell region and a second region over the TSV. A process, such as a plasma treatment, may be applied to the barrier wall, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Thus, the memory cell can be thermally isolated from thermal energy generated in the memory device due to the different thermal resistivities.)

1. An apparatus, comprising:

a plurality of pillars located over a substrate, each of the plurality of pillars comprising a memory cell;

an oxide region over the substrate;

a via extending through the oxide region to the substrate;

a barrier material over at least the plurality of pillars, the oxide regions, and the vias, the barrier material comprising a first section having a first density and a second section having a second density; and

an access line over the barrier material and configured to communicate with each of the memory cells.

2. The apparatus of claim 1, wherein the first section of the barrier material is located over at least some of the plurality of pillars and a first section of the oxide region, and the second section of the barrier material is located over at least the via and a second section of the oxide region.

3. The apparatus of claim 1, wherein the first section of the barrier material is located over the plurality of pillars and at least a first section of the oxide region, and the second section of the barrier material is located over the via, the second section of the barrier material corresponding to a width of the via closest to the barrier material.

4. The apparatus of claim 3, wherein the second section of the barrier material is limited to the same area as an area of an end of the via.

5. The apparatus of claim 1, further comprising:

circuitry in contact with the substrate, the circuitry configured to communicate signals with each of the memory cells through the vias and the access lines.

6. The apparatus of claim 1, wherein the second density is greater than the first density.

7. The apparatus of claim 1 wherein at least a first portion of the first section of the barrier material comprises dinitrogen.

8. The apparatus of claim 7, wherein the barrier material comprises tungsten silicon nitride, and wherein the first portion of the first section of the barrier material has a higher density of tungsten-nitrogen bonds than the second section of the barrier material.

9. The apparatus of claim 1, wherein the barrier material is configured to thermally insulate each of the memory cells from the access line.

10. The apparatus of claim 1, wherein each of the memory cells comprises a storage element and a selector device.

11. The apparatus of claim 1, wherein the oxide region is in contact with at least one of the plurality of pillars.

12. The apparatus of claim 1, wherein the oxide region is located on a first side of the via and a second side of the via.

13. A method, comprising:

forming an oxide material;

forming a plurality of pillars, at least one of the plurality of pillars being in contact with the oxide material;

forming a via through a portion of the oxide material;

forming a barrier material over the plurality of pillars, the oxide material, and the vias, the barrier material comprising a first section over at least the plurality of pillars and a second section over at least the vias; and

applying a plasma to the first section of the barrier material to change a density of the first section from a second density to a first density, the second section having the second density.

14. The method of claim 13, wherein applying the plasma comprises:

applying the plasma to a top surface of a top portion of the first section, wherein the top portion of the first section comprises the first density based at least in part on applying the plasma.

15. The method of claim 13, further comprising:

determining a target density for the first section of the barrier material; and

selecting the barrier material having the second density greater than the target density based at least in part on determining the target density, wherein applying the plasma to the first section of the barrier material is based at least in part on selecting the barrier material to adjust the density of the barrier material from the second density to the first density closer to the target density.

16. The method of claim 13, further comprising:

masking the second section of the barrier wall material, wherein applying the plasma to the first section of the barrier wall material is based at least in part on masking the second section of the barrier wall material.

17. The method of claim 13, further comprising:

etching at least a portion of the oxide material, wherein the plurality of pillars are formed adjacent to the oxide material based at least in part on etching at least the portion of the oxide material.

18. The method of claim 13, further comprising:

forming access lines over the barrier material, wherein the access lines are configured to communicate through the barrier material.

19. The method of claim 13, in which the dimension of the second section of the barrier material is the same as the dimension of the via in a first direction.

20. The method of claim 13, wherein the first section of the barrier material is in contact with at least the plurality of pillars and the second section of the barrier material is in contact with at least the vias.

21. The method of claim 20, wherein the first density is lower than the second density.

22. The method of claim 13, wherein the barrier material comprises tungsten silicon nitride, or wherein the plasma comprises nitrous oxide, helium, or a combination thereof.

23. The method of claim 13, wherein the barrier material comprises a bilayer structure.

24. An apparatus, comprising:

a pillar comprising a memory cell and located over a substrate;

an oxide region over the substrate and in contact with the pillar;

a via in contact with the oxide region and extending through the oxide region to the substrate;

a barrier material comprising a first section and a second section, the first section having a first resistivity and being in contact with at least the pillar, and the second section having a second resistivity and being in contact with at least the via; and

an access line in contact with the barrier material and configured to communicate signaling to the memory cells.

25. The apparatus of claim 24, wherein the first section of the barrier material is in contact with at least a section of the access line that is different from a second section of the access line directly above the via.

Technical Field

Background

The following generally relates to systems having memory devices, and more specifically relates to memory devices having high resistivity thermal barriers.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices have two states, typically represented as a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, components of the electronic device may read or sense the stored state in the memory device. To store information, components of the electronic device may write or program states in the memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memories (RAMs), Read Only Memories (ROMs), dynamic RAMs (drams), synchronous dynamic RAMs (sdrams), ferroelectric RAMs (ferams), magnetic RAMs (mrams), resistive RAMs (rrams), flash memories, Phase Change Memories (PCMs), and the like. The memory devices may include volatile memory cells or nonvolatile memory cells. Non-volatile memory cells can maintain their stored logic state for long periods of time, even in the absence of an external power source. Volatile memory device cells may lose their stored state over time unless periodically refreshed by an external power source.

In some cases, the memory device may perform an access operation (e.g., a read operation or a write operation) on the memory cells. Performing an access operation may generate heat at or near the memory cell. The generated heat may dissipate onto nearby components, such as memory cells, and in some cases may disturb the state stored by other memory cells.

Disclosure of Invention

An apparatus is described. The apparatus includes: a plurality of pillars located over a substrate, each of the plurality of pillars comprising a memory cell; an oxide region over the substrate; a via extending through the oxide region to the substrate; a barrier material over at least the plurality of pillars, the oxide regions, and the vias, the barrier material comprising a first section having a first density and a second section having a second density; and an access line over the barrier material and configured to communicate with each of the memory cells.

A method is described. The method comprises the following steps: forming an oxide material; forming a plurality of pillars, at least one of the plurality of pillars being in contact with the oxide material; forming a via through a portion of the oxide material; forming a barrier material over the plurality of pillars, the oxide material, and the vias, the barrier material comprising a first section over at least the plurality of pillars and a second section over at least the vias; and applying a plasma to the first section of the barrier material to change the density of the first section from a second density to a first density, the second section having the second density.

An apparatus is described. The apparatus includes: a pillar comprising a memory cell and located over a substrate; an oxide region over the substrate and in contact with the pillar; a via in contact with the oxide region and extending through the oxide region to the substrate; a barrier material comprising a first section and a second section, the first section having a first resistivity and being in contact with at least the pillar, and the second section having a second resistivity and being in contact with at least the via; and an access line in contact with the barrier material and configured to communicate signaling to the memory cell.

Drawings

FIG. 1 illustrates an example memory device including an array of memory cells supporting a high resistivity thermal barrier, according to an example as disclosed herein.

FIG. 2 illustrates an example of a memory array supporting a high resistivity thermal barrier in accordance with an example as disclosed herein.

Fig. 3-5 illustrate examples of memory devices having high resistivity thermal barriers in accordance with examples as disclosed herein.

FIG. 6 illustrates an example of a fabrication process supporting a memory device having a high resistivity thermal barrier in accordance with an example as disclosed herein.

Fig. 7A and 7B illustrate an example of a plasma application process supporting a memory device having a high resistivity thermal barrier in accordance with an example as disclosed herein.

Fig. 8-10 show flow diagrams illustrating one or more methods of supporting a memory device having a high resistivity thermal barrier in accordance with examples as disclosed herein.

Detailed Description

The memory device may include one or more self-selected memory cells comprising several components, such as cell components, arranged in a stack. The one or more cell elements may be in contact with other elements, such as electrodes. In some cases, the outermost electrodes may be in contact with barrier ribs, such as tungsten silicon nitride (WSiN) barrier ribs, which in turn may be in contact with access lines, such as word lines or digit lines. The barrier may be configured to prevent molecular diffusion between the outermost electrodes and corresponding access lines (e.g., the barrier may be an example of a diffusion barrier). Additionally, the barriers may be configured to allow one or more electrical signals (e.g., programming signals) to pass through the barrier.

However, applying a signal (e.g., a programming signal or other signal) to the memory cells may generate thermal energy (e.g., heat, such as latent heat) at the memory cells that may be dissipated toward or onto the memory cells located in the surrounding area. In some scenarios, a memory cell that generates thermal energy may be referred to as an aggressor cell, and a memory cell to which thermal energy is dissipated may be referred to as a victim cell. Thermal energy may be dissipated toward or onto a victim cell through (e.g., via) a thermally conductive material coupled to the memory cell, such as a digit line or word line. When thermal energy dissipates toward or onto the victim cell, the thermal energy may cause the victim cell to transition one or more states stored by the victim cell, which may be referred to as thermal interference. The barrier can be configured to at least partially thermally insulate the memory cell from the thermally conductive material. The thermal conductivity of the barrier may depend at least in part on the density of the barrier (e.g., a higher density of WSiN may result in higher thermal conductivity, which in turn may lead to a greater amount of thermal interference). However, in some examples, a barrier with high thermal conductivity or low density may prevent certain signals from being communicated from circuitry associated with the memory device to one or more memory cells. For example, such signals may be communicated from the circuitry, through vias (e.g., Through Silicon Vias (TSVs), interconnects), and to access lines coupled with the memory cells. While it may be beneficial to reduce thermal interference between memory cells (e.g., by using barriers), it may also be beneficial to transfer signals to the access lines with relatively little interference.

To mitigate thermal interference and/or stabilize the resistivity of the barrier, a low density portion of the barrier material can be formed that is configured to provide thermal insulation for the selected memory cell. The low density portions may be formed by depositing a barrier material, e.g., via Physical Vapor Deposition (PVD), and applying a plasma treatment to the deposited barrier material. Applying a plasma to the barrier wall material may form a low density portion at the exposed surface of the barrier wall material. In some cases, as an example only, the plasma may be generated from nitrous and helium gas molecules. In the case where the barrier material is WSiN, the low-density portion may also be WSiN. But the low density portions may have a greater proportion of tungsten-nitrogen bonds relative to the deposited barrier material. Additionally or alternatively, the low density portions may have a lower proportion of tungsten-silicon bonds relative to the deposited barrier material. These ratios may reduce the density of the processed portions, stabilize the resistivity, increase the resistivity relative to the remaining deposition barrier material, or a combination thereof, which may reduce thermal interference of the memory cell without impeding signal transfer to the access line coupled with the memory cell.

The features of the present invention are initially described in the context of a memory device. Specific examples are described subsequently in the context of memory arrays, various memory devices, manufacturing processes, and plasma application processes. These and other features of the present invention are further illustrated by and described with reference to apparatus diagrams and flow diagrams related to memory devices having high resistivity thermal barriers.

FIG. 1 illustrates an example memory device 100 according to an example of the invention. Memory device 100 may also be referred to as an electronic memory device. FIG. 1 is an illustrative representation of various components and features of a memory device 100. Thus, it should be understood that the components and features of the memory device 100 are shown to illustrate the functional interrelationship, not the actual physical location within the memory device 100 therein.

In the illustrative example of fig. 1, the memory device 100 includes a three-dimensional (3D) memory array 102, although the teachings herein may also be used to form a 2D (single stack) memory array (in other device types). The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 can be programmed to store two states, represented as a logic 0 and a logic 1. In some examples, memory cell 105 may be configured to store more than two logic states (e.g., a multi-level cell). In some examples, memory cells 105 may include a self-selected memory cell, 3DXPoint^TMA memory cell, a PCM cell comprising a storage component and a selection component, a conductive bridge ram (cbram) cell, or a FeRAM cell. The memory array 102 may be located above a substrate including various circuits, such as a row decoder 120, a sense component 125, a column decoder 130, Complementary Metal Oxide Semiconductor (CMOS) under an array (not shown), or the like. Although some elements included in fig. 1 are labeled with numerical indicators and other corresponding elements are not labeled, they are the same or will be understood to be similar in order to increase the visibility and clarity of the depicted features.

The memory array 102 may include two or more two-dimensional (2D) memory arrays formed on top of each other. This may increase the number of memory cells that can be placed or created on a single die or substrate, which in turn may reduce production costs or improve performance of the memory device, or both, as compared to 2D arrays. Memory array 102 may include two levels of memory cells 105 (e.g., memory cells 105-a and 105-b) and thus may be considered a 3D memory array; however, the number of levels is not limited to two (e.g., 2)^NA hierarchy wherein N ═ 2,3,4, 5.). Each level may be aligned or positioned such that memory cells 105 may be aligned (precisely, overlapping, or approximately) to each other on each level, forming a memoryA cell stack 145. In some cases, a level of memory cells may be referred to as a deck of memory cells. In some cases, memory cell stack 145 may include multiple self-selected memory cells that are located on top of each other while sharing access lines for both. In some cases, the self-selected memory cells may be multi-level self-selected memory cells configured to store more than one bit of data using multi-level storage techniques.

In some examples, each row of memory cells 105 is connected to a word line 110 and each column of memory cells 105 is connected to a digit line 115. The access lines may refer to word lines 110, digit lines 115, or both. The word line 110 and digit line 115 may be substantially perpendicular to each other, and may create an array of memory cells. As shown in FIG. 1, two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as digit line 115. That is, digit line 115 may be in electronic communication with the bottom electrode of upper memory cell 105 and the top electrode of lower memory cell 105. Other configurations may be possible, for example, the third layer may share word lines 110 with the lower layers.

In general, one memory cell 105 may be located at the intersection of two conductive lines, such as word line 110 and digit line 115. This intersection may be referred to as the address of the memory cell. Target memory cell 105 may be memory cell 105 located at the intersection of the energized word line 110 and digit line 115; that is, word line 110 and digit line 115 may be energized to read or write memory cell 105 at its intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same word line 110 or digit line 115 may be referred to as non-target memory cells 105.

As discussed herein, an electrode may be coupled to a memory cell 105 and a word line 110 or digit line 115. The term electrode may refer to an electrical conductor (e.g., a conductive material), and in some cases, may serve as an electrical contact to memory cell 105. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory device 100. In some examples, memory cell 105 may include one or more chalcogenide materials (e.g., germanium-antimony-tellurium (GST)) between a first electrode and a second electrode. One side of the first electrode may be coupled to the word line 110 and the other side of the first electrode may be coupled to one of the one or more chalcogenide materials. Additionally, one side of the second electrode may be coupled to digit line 115 and the other side of the second electrode may be coupled to one of the one or more chalcogenide materials. The first and second electrodes may be the same material (e.g., carbon) or different. In some cases, one or both of the word line 110 and the digit line 115 may be in contact with first and second barrier ribs that contact the first electrode and the second electrode, respectively.

Operations such as reads and writes may be performed on memory cell 105 by activating or selecting word line 110 and digit line 115. In some examples, digit lines 115 may also be referred to as bit lines 115. Additionally or alternatively, either or both of word line 110 and digit line 115 may be referred to as access lines. References to access lines, word lines, and digit lines or the like may be interchanged without loss of understanding or operation. Activating or selecting a word line 110 or digit line 115 may include applying a voltage to the respective line. The word lines 110 and digit lines 115 may be made of a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductively-doped semiconductor, or other conductive materials, alloys, compounds, or the like.

Access to memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 may receive a row address from the memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, a column decoder 130 may receive a column address from a memory controller 140 and activate the appropriate digit lines 115. For example, the memory array 102 may include a plurality of word lines 110 labeled WL _1 through WL _ M, and a plurality of digit lines 115 labeled DL _1 through DL _ N, where M and N depend on the array size. Thus, by activating word line 110 and digit lines 115, e.g., WL _2 and DL _3, memory cell 105 at its intersection can be accessed.

After access, the memory cell 105 may be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage may be applied to the memory cell 105 (using the corresponding word line 110 and digit line 115) and the presence of the resulting current may depend on the applied voltage and threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. Additionally, if applying a voltage does not result in a current, other voltages can be applied until the sensing component 125 detects a current. By evaluating the voltage that results in the current, the stored logic state of memory cell 105 can be determined. In some cases, the magnitude of the voltage may be ramped up until current flow is detected. In other cases, the predetermined voltages may be applied sequentially until a current is detected. Likewise, a current may be applied to memory cell 105, and the magnitude of the voltage used to generate the current may depend on the resistance or threshold voltage of memory cell 105. In some examples, sensing component 125 may read information stored in a selected memory cell 105 by detecting current or no current through memory cell 105.

The sensing component 125 can include various transistors or amplifiers to detect and amplify differences in signals associated with the sensed memory cell 105, which can be referred to as latching. The detected logic state of memory cell 105 may then be output as output 135 through column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 can be connected to or in electronic communication with column decoder 130 or row decoder 120. FIG. 1 also shows an alternative option (in dashed box) to arrange the sensing component 125-a. One of ordinary skill in the art will appreciate that the sensing component 125 can be associated with a column decoder or a row decoder without losing its functional purpose.

Memory cell 105 may be set or written by similarly activating the relevant word line 110 and digit line 115, and at least one logical value may be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data to be written to memory cells 105, such as input/output 135. In the case of a selected memory cell comprising a chalcogenide material, memory cell 105 may be written to store data by applying a programming signal to the selected memory cell.

The memory controller 140 may control the operation (e.g., read, write, re-write, refresh, discharge) of the memory cells 105 through various components, such as the row decoder 120, the column decoder 130, and the sense components 125. In some cases, one or more of row decoder 120, column decoder 130, and sensing component 125 may be collocated with memory controller 140. The memory controller 140 may generate row and column address signals to activate the desired word line 110 and digit line 115. Memory controller 140 may also generate and control various voltages or currents used during operation of memory device 100.

The memory array 102 may be located above a substrate including various circuits, such as a row decoder 120, a sensing component 125, a column decoder 130, CMOS under an array (not shown), or the like. In some cases, the memory array 102 may include a high resistivity (e.g., low density) thermal barrier formed based on the fabrication techniques described herein. In some examples, the density of the thermal barrier wall may be inversely proportional to the resistivity of the thermal barrier wall. For example, a plasma may be applied to the thermal barrier to increase its resistivity. In some examples, an increase in resistivity may result in a reduced density, and vice versa.

In some cases, applying a signal to memory cell 105 may generate thermal energy. When memory cell 105 includes a high resistivity (e.g., low density) thermal barrier wall material as described herein, the barrier material may be configured to thermally insulate memory cell 105 and may prevent dissipation of generated thermal energy onto or toward other memory cells 105 or other components. Additionally or alternatively, a barrier material having multiple segments (e.g., a first segment, a second segment) can prevent thermal energy from dissipating onto or toward one or more memory cells 105 while improving (e.g., facilitating, not inhibiting) transmission of signals to access lines of the memory array 102. In other words, barrier material located over an interconnect region (e.g., over a via as described with reference to fig. 3-5) may have a lower resistivity than a region located over memory cell 105. This may allow signals to be transmitted to various access lines (e.g., from the substrate and through the interconnect region) while allowing the memory cells 105 to be thermally isolated.

FIG. 2 illustrates an example of a memory array 200 supporting a high resistivity thermal barrier according to an example of the invention. The memory array 200 may be an example of a portion of the memory array 102 described with reference to FIG. 1. In some examples, multiple instances of the memory array 200 can be repeated (e.g., formed and stacked on top of each other) to form a 3D memory device. The 3D memory device may include two or more stacks of memory cells. Memory array 200 may include a stack 205 of memory cells (e.g., a first stack of memory cells) positioned above a substrate 204. In the case of a 3D memory array (not shown), memory array 200 may include a second array or stack of memory cells over the first array or stack 205. The memory array 200 may also include word lines 110-a, word lines 110-b, and bit lines 115, which may be examples of the word lines 110 and bit lines 115 described with reference to FIG. 1. In some examples, memory array 200 may also include barrier material 230 between stack 205 of memory cells and bit lines 115.

Although some elements included in fig. 2 are labeled with numerical indicators and other corresponding elements are not labeled, they are the same or will be understood to be similar in order to increase the visibility and clarity of the depicted features.

In some cases, the memory cells of stack 205 can each include a first electrode 215, a chalcogenide material 220, and a second electrode 225. In some examples, stack 205 may include a plurality of cell components that may be separated by third electrodes (not shown). Additionally or alternatively, stack 205 may include one or more barrier materials. As used herein, the material included in the cell stack between the word line 110 and the bit line 115 can be considered to be included in the memory cell and referred to collectively or individually as memory cell material. For example, as described below with reference to fig. 3-5, the memory cell material (e.g., the material of memory cell 305 described with reference to fig. 3) may be understood to be a composite (heterogeneous, mixed, merged) material and may include dissimilar materials included in first electrode 215, chalcogenide material 220, and/or second electrode 225. In some cases, the combination of various materials (e.g., first electrode 215, chalcogenide material 220, second electrode 225) that can form a memory cell (e.g., memory cell 105-a, memory cell 105-b) can also be collectively referred to as a memory cell stack. As shown in fig. 2, stack 205 may be coupled with barrier material 230 located between stack 205 and bit lines 115.

In some cases, barrier material 230 can provide thermal insulation between access lines (e.g., digit lines 115) and electrodes 225. In other examples, barrier material 230 may be located between a word line (e.g., word line 110-a) and electrode 215 (not shown). In yet another example, a barrier material may be located between an access line (e.g., digit line 115) and electrode 225 and also between a word line (e.g., word line 110-a) and electrode 215 (e.g., there may be two barrier materials 230 associated with one or more pillars of memory array 200). Thus, one or more pillars of the memory array 200 may include a barrier material, an electrode (e.g., a bottom electrode), a selector device, an electrode (e.g., a middle electrode), a memory cell, an electrode (e.g., a top electrode), and a barrier material. Thermal insulation may be provided, for example, by a low density barrier material (e.g., a high resistivity barrier material). In one case, if a programming signal is applied to the memory cell and the barrier material 230 is thermally insulating, the electrode 225 can still conduct the generated thermal energy. However, the barrier material 230 may mitigate the amount of thermal energy transferred to the word line 110-a. Additionally or alternatively, the resistivity of barrier material 230 may fluctuate by a factor (e.g., 2 or 3 times) as the corresponding cell element generates thermal energy.

For example, the memory cells of deck 205 may receive programming signals from digit lines 115. When a memory cell receives a programming signal, it can generate thermal energy. The memory cell may impart thermal energy to the barrier material 230, which may cause its resistivity to change (e.g., rise). After receiving the programming signal, the memory cell may release thermal energy (e.g., the memory cell may cool). As the memory cells release thermal energy, the barrier material 230 may also release thermal energy. As barrier material 230 releases thermal energy, its resistivity may decrease. However, the trajectory followed by the resistivity of barrier material 230 as thermal energy is released may not match that inThe trajectory followed by the resistivity of barrier material 230 as thermal energy is generated. These fluctuations may bring about V_T、I_{Reduction of position}Or a shift in the amount of read disturb.

In some examples, access lines (e.g., word lines 110, bit lines 115) may include electrode layers (e.g., conformal layers) in place of electrodes 215 or 225, and thus may comprise multiple layers of access lines. In such examples, the electrode layers of the access lines may interface with the memory material (e.g., chalcogenide material 220). In some examples, access lines (e.g., word lines 110, bit lines 115) may interface directly with memory material (e.g., chalcogenide material 220) without an electrode layer or electrode therebetween.

In some examples, the memory cells of the stack 205 may have a common conductive line such that corresponding pillars may share the bit line 115 or the word line 110. For example, electrode 225 and a top electrode of an adjacent pillar may both be coupled to bitline 115 such that bitline 115 is shared by adjacent memory cells (e.g., horizontally aligned).

In some examples, memory array 200 may include one or more additional stacks of memory cells stacked on stack 205. Each additional stack of memory cells may be aligned (e.g., vertically aligned) and may include additional bit lines. For example, an additional stack of memory cells may be coupled with stack 205 such that the bottom electrode is coupled with bit line 115 and the top electrode is coupled with an additional bit line. The additional bitlines can be electrically isolated from the bitlines 115 (e.g., an insulating material can be interposed between the additional bitlines and the bitlines 115). Thus, the first stack 205 and each additional stack may be separated and operated independently of each other. In some cases, an access line (e.g., word line 110 or bit line 115) may include a selection component (e.g., a two-terminal selector device, which may be configured as one or more thin film materials integrated with the access line) for a respective memory cell at each intersection. Thus, the access lines and the selection members may together form a composite material layer acting as access lines and selection members.

In some cases, the architecture of the memory array 200 may be referred to as an example of a cross-point architecture, as memory cells may form in a topology between word lines 110 and bit lines 115 as illustrated in fig. 2At the point of intersection. This cross-point architecture may provide relatively high density data storage and lower production costs compared to some other memory architectures. For example, a memory array having a cross-point architecture may have memory cells with a reduced area, and thus may support increased memory cell density compared to some other architectures. For example, 6F with those having three terminal select elements, for example²Compared to other architectures of memory cell area, the cross-point architecture may have 4F²Memory cell area, where F is the minimum feature size (e.g., minimum feature size). For example, a DRAM memory array may use a transistor (e.g., a thin film transistor) that is a three terminal device as a select component for each memory cell, and thus a DRAM memory array including a given number of memory cells may have a larger memory cell area than a memory array having a cross-point architecture including the same number of memory cells.

Although the example of fig. 2 shows one stack 205, other configurations may include any number of stacks (e.g., 2 stacks, 4 stacks, 8 stacks, 16 stacks, 32 stacks, or a greater number of stacks). In some examples, one or more of the stacks may include a self-selected memory cell including chalcogenide material 220. In other examples, one or more of the stacks may include FeRAM cells that include ferroelectric material. In yet further examples, one or more of the stacks may include PCM cells that include a storage component and a selection component. The chalcogenide material 220 may, for example, comprise a chalcogenide glass, such As an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) may be referred to As a SAG alloy. In some examples, the SAG alloy may include silicon (Si) and such chalcogenide materials may be referred to as SiSAG alloys. In some examples, the chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), gallium (Ga), or fluorine (F), each of which may be in atomic or molecular form.

In some cases, a stack of memory devices (e.g., stack 205) may be formed using the fabrication techniques described herein. For example, the memory array 200 may be formed using one or more fabrication techniques as described with reference to fig. 3-7. In some examples, the substrate 204 may include various circuitry, such as CMOS (not shown) under the array. In some cases, the CMOS under the array may be configured to communicate with the memory array 200 through vias located in a peripheral region of the array (e.g., it may be configured to transmit signaling to the memory cells of the stack 205). For example, the vias may allow signaling to be transmitted from the CMOS to the access lines (e.g., to bit lines 115). The fabrication techniques described herein may result in the formation of a high resistivity thermal barrier having multiple sections (e.g., a first section, a second section). The sections of the barrier can be treated such that the sections above the memory array 200 can prevent thermal energy from dissipating onto one or more memory cells, and the regions above the vias can allow signals to be transmitted to various access lines (e.g., the sections above the vias can have relatively low thermal resistivity).

FIG. 3 illustrates an example of a memory device 300 supporting a high resistivity thermal barrier according to an example of the invention. In some examples, memory device 300 may include one or more memory cells 305 located above a substrate (not shown), which may be an example of stack 205 of memory cells described with reference to fig. 2. The memory device 300 may include an oxide region 310 and one or more vias 315. In some examples, the via 315 can extend through a portion of the oxide region 310 (e.g., the oxide region 310 can be located on both sides of the via 315). Additionally or alternatively, the memory device 300 may include a barrier material 320 and an access line 325. In some examples, barrier material 320 may be located over memory cells 305, oxide regions 310, and/or vias 315, and access lines 325 may be located over barrier material 320.

In some examples, memory cell 305 may be included in or referred to as a pillar. For example, each pillar may include a memory cell and one or more electrodes. In some examples, each memory cell may be or may be referred to as a self-selecting memory cell 305. The self-selected memory cells 305 can include one or more cell components that can be programmed to a logic state by applying a programming signal to the respective memory cell 305. Providing programming signals to memory cell 305 may store data (e.g., one or more logic values at cell components of memory cell 305). For example, if a cell component receives a programming signal of a first polarity, memory cell 305 may store a logic '0', and if a cell component receives a programming signal of a second polarity, memory cell 305 may store a logic '1'.

Additionally or alternatively, each memory cell 305 can include a memory cell material, which can be understood to be a composite (heterogeneous, mixed, merged) material and can include dissimilar materials included in electrodes and/or chalcogenide materials. In some examples, the memory cell material may include one or more electrodes (e.g., electrode 215 and electrode 225 described with reference to fig. 2) and a chalcogenide material (e.g., chalcogenide material 220 described with reference to fig. 2). Thus, in some examples, memory cells 305 can be understood to include volatile and/or nonvolatile memory cells.

In some examples, the memory device 300 can include an oxide region 310. The oxide region 310 may be located adjacent to one of the memory cells 305. That is, in some examples, the oxide region 310 can contact, abut against, and/or be separate from at least one of the pillars of the memory cell 305. In some examples, a dielectric material may be located between each of the memory cells 305, and the oxide region 310 may be in contact with at least one of the memory cells 305. In some examples, the dielectric material between each of the memory cells 305 can be or can include an oxide material (e.g., an oxide material deposited in the oxide region 310). In some examples, the oxide region 310 can be formed (e.g., deposited) on a substrate. Various processing techniques may be performed prior to forming memory cells 305, e.g., the top surface of oxide regions 310 may be polished. For example, the top surface of the oxide region 310 may be removed using a polishing technique, such as a Chemical Mechanical Planarization (CMP) process step. A portion of oxide region 310 may then be removed (e.g., it may be etched) to form a region in which memory cell 305 is formed. Thus, by removing a portion of the oxide region 310, at least one memory cell 305 can be adjacent to (e.g., contact) the oxide region 310.

In some examples, the oxide region 310 may be or may include a dielectric material. As discussed herein, the one or more vias 315 may extend through the oxide region 310 and may transmit signaling to one or more components, such as the memory cell 305. Thus, the oxide region 310 (e.g., dielectric material) may isolate the memory cell 305 from the via 315. That is, oxide regions 310 may prevent electrical and/or thermal interference that may otherwise occur between memory cells 305 and vias 315. In some examples, the oxide region 310 may include a plurality of vias 315, and each via 315 may be separated by a portion of the oxide region 310. In other words, the oxide regions 310 may isolate one or more vias 315 from each other and/or from each of the memory cells 305. In some examples, each via 315 can extend through the oxide region 310 (e.g., to a substrate below the oxide region 310). In some examples, oxide regions 310 may be located on (e.g., adjacent to, in contact with) each side of via 315.

As discussed herein, the oxide region 310 may include one or more vias 315. The vias 315, which may be or may be referred to as through-silicon vias (TSVs) or interconnects, may communicate signaling from the substrate of the memory device 300 to one or more memory cells. For example, signaling may be communicated to access line 325 and may be associated with an access operation (e.g., a read operation, a write operation) of one or more memory cells 305. In some examples, the vias 315 can be formed using a fabrication process, such as an etching process, to remove a portion of the oxide regions 310. In other words, a portion of oxide region 310 may be removed and via 315 may be formed therein. Thus, in some examples, oxide regions 310 may be located on both sides of vias 315 (or on both sides of each via 315).

In some examples, barrier material 320 may be deposited over memory cell 305, oxide region 310, and/or via 315 (or each via 315 in the case of multiple vias). The barrier material 320 may include tungsten silicon nitride (WSiN). In some examples, untreated barrier material 320 may be deposited (e.g., upon, e.g., applying a plasma)Barrier material 320 prior to one or more processing techniques of the daughter) to improve reset current benefits (e.g., I may be reduced_{Reduction of position}、V_TAnd a more consistent value of read disturb applied to memory cell 305). However, applying a signal to memory unit 305 may generate thermal energy (e.g., heat, such as latent heat) at memory unit 305. The heat may typically dissipate onto other memory cells 305 located in the surrounding area. Thermal energy may be dissipated to the victim cell through a thermally conductive material, such as a digit line or word line, coupled to the memory cell. Thus, a barrier capable of insulating one or more memory cells 305 may be beneficial.

As discussed herein, various techniques may be used to alter one or more properties associated with barrier material 320. The density or resistivity of at least a portion of barrier material 320 may be altered using one or more techniques or processing steps, for example. As one non-limiting example, a plasma may be applied to at least a portion of the barrier material 320. In some examples, the processing barrier material 320 may mitigate (e.g., prevent) such thermal energy from interfering with other components, such as the memory cells 305 in the array. In some examples, increasing the thermal resistivity (e.g., reducing density) of the barrier material 320 (e.g., by applying plasma) may cause signaling communicated between the vias 315 and the access lines 325 to be impeded. Thus, by processing portions (e.g., sections) of barrier material 320 (e.g., with plasma), barrier material 320 can thermally isolate one or more memory cells 305 and allow signaling to be communicated through vias (e.g., from the substrate) to access lines 325.

In some examples, barrier material 320 may include a first section 330 and a second section 335. The first section 330 may be located over at least the memory cell 305, and the second section 335 may be located over the oxide region 310 and/or the via 315 (e.g., which may be higher than the rest of the memory device 300). To increase the thermal resistivity or decrease the density of first section 330 of barrier material 320, second section 335 may be masked (e.g., a portion of barrier material 320 may be at least partially masked). In other words, plasma may be applied to the first section 330 and not to the second section 335, which may result in a localized application of plasma. Plasma may be applied to the top portion of the first section 330. Thus, a bottom portion of the first section 330 (e.g., below the first section) does not receive plasma processing. This may result in the top portion (e.g., top layer) of the first section 330 having a different density (e.g., a different higher resistivity) than the bottom portion. In some examples, a plasma is applied to the first section 330 of the barrier material 320, and dinitrogen may be present on the upper surface or within the upper layer of the first section 330.

In some examples, the type of plasma treatment may be selected. For example, the process may be selected based on different process times, different deposition chamber temperature functions, different deposition chamber pressure functions, different amounts of constituent molecules (e.g., dinitrogen or helium) used to create the plasma for the plasma process, different plasma powers, or a combination thereof. In some examples, the plasma may be made from a gas comprising molecules of dinitrogen and helium. The plasma may be applied at any point in a range of durations (e.g., 50 seconds to 100 seconds). The lower limit of the duration range may be in a range between 46 seconds and 54 seconds, between 47 seconds and 53 seconds, between 48 seconds and 52 seconds, between 49 seconds and 51 seconds, or may be about 50 seconds. The upper limit of the duration range may be in a range between 96 seconds and 104 seconds, 97 seconds and 103 seconds, 98 seconds and 102 seconds, 99 seconds and 101 seconds, or may be about 100 seconds. Additionally, the plasma treatment may be associated with any power having a power value in the range of 1kW and 2 kW. The lower power of the power value range may be in a range between 0.6 kilowatts (kW) and 1.4kW, 0.7kW and 1.3kW, 0.8kW and 1.2kW, 0.9kW and 1.1kW, or may be about 1.0 kW. The upper power of the power value range may be in a range between 1.6kW and 2.4kW, 1.7kW and 2.3kW, 1.8kW and 2.2kW, 1.9kW and 2.1kW, or may be about 2.0 kW.

By applying plasma to the first section 330, the density of the first section 330 can be reduced and the resistivity can be altered. In some examples, decreasing the density of the first section 330 may result in an increased resistivity of the first section 330. Additionally or alternatively, the density of the second sections 335 may remain relatively higher than the first sections 330. For example, the density of the first section 330 may be reduced from approximately 6.756 grams per cubic centimeter (g/cc) to a density of 3.7 g/cc. Because the reduced density of barrier material 320 can result in increased thermal resistivity, applying plasma to first section 330 of barrier material 320 can result in a section above memory cell 305 having increased thermal resistivity compared to a section above via 315. Such processing may result in the barrier material 320 insulating one or more memory cells 305 while allowing signaling to pass through the vias (from the substrate) to the access lines 325.

In some cases, the low density portion of the barrier material (e.g., the first section 330) may include a bilayer structure. In one example (e.g., when a low density barrier material is utilized), a first layer of the bi-layer structure (e.g., a surface layer in contact with the access lines 325) may be more abundant (e.g., denser) with tungsten than a second layer of the bi-layer structure (e.g., a bulk layer in contact with the memory cells 305). In another example (e.g., when a low density barrier material is utilized), a first layer of the bi-layer structure (e.g., a surface layer in contact with the electrode memory cells 305) may be more abundant (e.g., denser) with tungsten than a second layer of the bi-layer structure (e.g., a bulk layer in contact with the access lines 325). In either example, the first layer can have a different (e.g., thinner) thickness than the second layer. The double-layer structure may have an overall density that is less than second section 335 of barrier material 320. Additionally or alternatively, the barrier material may comprise a three-layer structure. In one example, a tri-layer structure may include a first layer that may be more abundant (e.g., denser) with tungsten than a second layer (e.g., an intermediate layer). In some examples, the third layer may be or may be associated with an original density (i.e., the third layer may have the same density as the untreated barrier material 320).

FIG. 4 illustrates an example of a memory device 400 supporting a high resistivity thermal barrier according to an example of the invention. In some examples, memory device 400 may include one or more memory cells 405 located above a substrate (not shown), which may be an example of 305 described with reference to fig. 3. The memory device 400 may include an oxide region 410 and one or more vias 415, which may be examples of the oxide region 310 and the via 315 described with reference to fig. 3. In some examples, memory device 400 can include barrier material 420 and access lines 425. Barrier material 420 may be located over memory cell 405, oxide region 410, and/or via 415, and access line 425 may be located over barrier material 420.

In some examples, memory device 400 can include an oxide region 410 that can be positioned adjacent to (e.g., in contact with) one of memory cells 405. In some examples, oxide region 410 can be in contact with memory cell 405, can be proximate (e.g., adjacent) to memory cell 405, and/or can be separate from memory cell 405. The oxide region 410 may be or may include a dielectric material that may insulate the memory cell 405 from one or more vias 415 that extend through the oxide region 410. That is, oxide regions 410 may prevent electrical and/or thermal interference that may otherwise occur between memory cells 405 and signaling conveyed by vias 415 (e.g., from the substrate to access lines 425). In some examples, the oxide region 410 may include a plurality of vias 415, and each via 415 may be separated by a portion of the oxide region 410. Each via 415 may extend through the oxide region 410 (e.g., to a substrate below the oxide region 410). In some examples, oxide regions 410 may be located on (e.g., adjacent to, in contact with) each side of vias 415.

As discussed herein, the oxide region 410 may include one or more vias 415. The vias 415, which may be or may be referred to as through-silicon vias (TSVs) or interconnects, may communicate signaling from the substrate of the memory device 400 to one or more components, such as the memory cells 405. Barrier material 420 can be deposited over memory cell 405, oxide region 410, and/or via 415 (or each via 415 in the case of multiple vias), which can improve reset current benefits (e.g., I_{Reduction of position}、V_TAnd a more consistent value of read disturb may be applied to memory cell 405). In some examples, it may be beneficial for the barrier material 420 to thermally insulate the one or more memory cells 405.

A plasma may be applied to at least a portion (e.g., a zone) of the barrier material 420 to improve the thermal resistivity of the respective zone. In some examples, the plasma may be applied directly over each of the memory cells 405. That is, when plasma is applied directly over each of the memory cells, the barrier material 420 directly over each memory cell 405 may be processed (i.e., it may have a different density than other portions of the barrier material 420), while the barrier material not directly over each memory cell 405 may have a different density than the processed portions. In some examples, a plasma may be applied directly over each of memory cells 405 using one or more patterning techniques that result in a plasma being applied directly over each memory cell 405. Various techniques may be used to alter one or more properties associated with the barrier material 420. For example, one or more techniques or processing steps may be used to alter the density or resistivity of at least a portion of the barrier material 420. In some examples, the processing barrier material 420 can mitigate (e.g., prevent) such thermal energy from interfering with other memory cells 405 in the array. However, it may be beneficial for the barrier material 420 over the vias 415 not to impede signaling transfer to the access lines 425. Thus, by treating portions (e.g., sections) of barrier material 420 with plasma, barrier material 420 may insulate one or more memory cells 405 and allow signaling to be communicated through vias (from the substrate) to access lines 425.

In some examples, barrier material 420 may include a first section 430 and a second section 435. The first section 430 can be located over at least the memory cell 405, and the second section 435 can be located over the oxide region 410 and/or the via 415 (e.g., which can be higher than the rest of the memory device 400). As described herein, it may be desirable for first section 430 (e.g., over memory cell 405) of barrier material 420 to have a high thermal resistivity (e.g., low density) and second section 435 (e.g., over at least via 415) to have a relatively lower thermal resistivity (e.g., relatively higher density).

Thus, the untreated barrier material 420 as shown in fig. 4 may be selected based on its resistivity. For example, untreated barrier material 420 (e.g., barrier material 420 prior to applying one or more processing techniques such as plasma) may have a relatively low resistivity such that it may be desirable to increase the resistivity of first section 430 (or decrease the density of first section 430). In some examples, untreated barrier material 420 may have a higher density (e.g., lower resistivity) than untreated barrier material 320, as shown and discussed with reference to fig. 3. Accordingly, a target density (e.g., a target resistivity) for the first section 430 can be determined, and plasma can be applied to the first section 430 as one example of a processing technique that changes the density and/or resistivity. The difference between the treated and untreated portions of the barrier material 420 may be the same or similar difference as the difference between the treated and untreated portions of the barrier material 320 described with reference to fig. 3. That is, the barrier material 320 may be associated with a first resistivity, and the difference in resistivity between treated and untreated portions of the barrier material 320 may be represented by Δ. With respect to fig. 4, barrier material 420 may be associated with a second resistivity that is lower than the first resistivity (e.g., of barrier material 320). A target density (e.g., a target resistivity) for a portion of barrier material 420 can be determined, and in some examples, a plasma can be applied such that a difference in resistivity between treated and untreated portions of barrier material 420 can be represented by Δ 1. In some examples, Δ and Δ 1 may be the same or similar values.

As discussed herein, a plasma treatment may be applied to the first section 430 to replicate the desired resistivity, i.e., the plasma treatment may increase the thermal resistivity of the first section 430 while the resistivity of the second section 435 remains relatively low. In some examples, increasing the resistivity of the first section 430 may result in a reduced density of the first section 430. Additionally or alternatively, the density of the second section 435 can remain relatively higher than the first section 430. In some examples, the plasma treatment may cause barrier material 420 to insulate one or more memory cells 405 while allowing signaling to pass through the vias (from the substrate) to access lines 425.

In some cases, the low density portion of the barrier material (e.g., first section 430) may include a bilayer structure. In one example (e.g., when a low density barrier material is utilized), an upper layer of the bi-layer structure (e.g., a surface layer in contact with access lines 425) may be richer (e.g., denser) of tungsten than a lower layer of the bi-layer structure (e.g., a bulk layer in contact with memory cells 405). In another example (e.g., when a low density barrier material is utilized), a lower layer of the bi-layer structure (e.g., a surface layer in contact with the electrode memory cells 405) may be more abundant (e.g., denser) with tungsten than an upper layer of the bi-layer structure (e.g., a bulk layer in contact with the access lines 425). In either example, one layer (e.g., an upper layer or a lower layer) can have a different (e.g., thinner) thickness than the other layer. The double-layer structure may have an overall density that is less than the second section 435 of barrier material 420. Additionally or alternatively, the barrier material may comprise a three-layer structure. In one example, the tri-layer structure may include an upper layer, which may be more tungsten rich (e.g., denser) than the middle layer of the tri-layer structure. In some examples, the lower layer may be or may be associated with an original density (i.e., the third layer may have the same density as the untreated barrier material 320). In another example, the tri-layer structure may include a lower layer, which may be more abundant (e.g., denser) with tungsten than the middle layer of the tri-layer structure. In some examples, the upper layer may be or may be associated with an original density (i.e., the third layer may have the same density as the untreated barrier material 420).

FIG. 5 illustrates an example of a memory device 500 that supports a high resistivity thermal barrier according to an example of the invention. In some examples, memory device 500 may include one or more memory cells 505 located over a substrate (not shown), which may be an example of 305 described with reference to fig. 3. Memory device 500 may include an oxide region 510 and one or more vias 515, which may be examples of oxide region 310 and vias 315 described with reference to fig. 3. In some examples, memory device 500 can include barrier material 520 and access lines 525. Barrier material 520 may be located over memory cells 505, oxide regions 510, and/or vias 515, and access lines 525 may be located over barrier material 520.

In some examples, memory device 500 can include an oxide region 510 that can be positioned adjacent to (e.g., in contact with) one of the memory cells 505. The oxide region 510 may be or may include a dielectric material that may isolate the memory cell 505 from one or more vias 515 extending through the oxide region 510. That is, oxide regions 510 can prevent electrical and/or thermal interference that might otherwise occur between memory cell 505 and signaling communicated by vias 515 (e.g., from the substrate to access lines 525). In some examples, oxide region 510 may include a plurality of vias 515, and each via 515 may be separated by a portion of oxide region 510. Each via 515 may extend through the oxide region 510 (e.g., to the substrate below the oxide region 510). In some examples, oxide regions 510 may be located on (e.g., adjacent to, in contact with) each side of via 515.

As discussed herein, the oxide region 510 may include one or more vias 515. The vias 515, which may be or may be referred to as through-silicon vias (TSVs) or interconnects, may communicate signaling from the substrate of the memory device 500 to one or more components, such as the memory cells 505. Barrier material 520 may be deposited over memory cell 505, oxide region 510, and/or via 515 (or each via 515 in the case of multiple vias), which may improve reset current benefits (e.g., I_{Reduction of position}、V_TAnd a more consistent value of read disturb may be applied to memory cell 505). In some examples, it may be beneficial for the barrier material 520 to thermally insulate the one or more memory cells 505.

A plasma may be applied to at least a portion (e.g., a zone) of the barrier material 520 to improve the thermal resistivity of the respective zone. Various techniques may be used to alter one or more properties associated with barrier material 520. For example, one or more techniques or processing steps may be used to alter the density or resistivity of at least a portion of barrier material 520. In some examples, the process barrier material 520 can mitigate (e.g., prevent) such thermal energy from interfering with other memory cells 505 in the array. However, it may be beneficial for the barrier material 520 over the vias 515 not to impede signaling transfer to the access lines 525. Thus, by treating portions (e.g., sections) of barrier material 520 with plasma, barrier material 520 may insulate one or more memory cells 505 and allow signaling to be communicated through vias (from the substrate) to access lines 525.

As described herein, barrier material 520 may include a first section 530 and a second section 535. The first section 530 may be located over all portions of the memory device 500 except the via 515. In other words, the second segment 535 may be located directly over the via 515 (e.g., over the top surface of the via 515, only directly over/in the vertical space overlying the via). In some examples, the second segment 535 may be masked using reverse polarity shredding or by utilizing a mask of vias 515 that may be relevant to other fabrication techniques associated with generating one or more components otherwise shown in fig. 5. For example, one or more processing techniques may be used to deposit oxide region 510, form memory cell 505, and form via 515 extending through oxide region 510. Via 515 may be formed by masking oxide region 510 and/or memory cell 505 and then etching through at least oxide region 510 (e.g., etching through oxide region 510 to the substrate). Thus, as described with reference to fig. 5, barrier material 520 may be processed utilizing processing steps to form one or more portions of memory device 500.

For example, a plasma may be applied to the first section 530 of the barrier material 320 to increase the resistivity of the first section 530 (e.g., decrease the density of the first section 530). The plasma may be applied after second section 535 has been masked. As described above, a previous masking process (e.g., for forming via 515) may be utilized to apply plasma to first section 530. In some examples, utilizing such previous processes may improve the time required to produce the memory device 500 and/or reduce the costs associated with its production.

In some examples, applying the plasma to the first section 530 may reduce the density of the first section 530 from approximately 6.756 grams per cubic centimeter (g/cc) to a density of 3.7 g/cc. Because the reduced density of barrier material 520 may result in increased thermal resistivity, applying plasma to first section 530 of barrier material 520 may result in a section above memory cell 505 having increased thermal resistivity relative to the rest of barrier material 520. In other words, applying plasma to portions of barrier material 520 not located over vias 515 may prevent impedance in signaling communicated from vias 515 to access lines 525. In some examples, masking the area directly above the via (e.g., second section 535) may utilize existing processing steps (e.g., masking processes) for forming via 515. This may result in reduced processing time and reduced processing costs when forming the memory device 500.

In some cases, the low density portion of the barrier material (e.g., the first section 530) may include a bilayer structure. In one example (e.g., when a low density barrier material is utilized), an upper layer of the bi-layer structure (e.g., a surface layer in contact with access lines 525) may be more abundant (e.g., denser) with tungsten than a lower layer of the bi-layer structure (e.g., a bulk layer in contact with memory cells 505). In another example (e.g., when a low density barrier material is utilized), a lower layer of the bi-layer structure (e.g., a surface layer in contact with the electrode memory cells 505) may be more abundant (e.g., denser) with tungsten than an upper layer of the bi-layer structure (e.g., a bulk layer in contact with the access lines 525). In either example, one layer (e.g., an upper layer or a lower layer) can have a different (e.g., thinner) thickness than the other layer. The double layer structure may have an overall density that is less than the second section 535 of barrier material 520. Additionally or alternatively, the barrier material may comprise a three-layer structure. In one example, the tri-layer structure may include an upper layer, which may be more tungsten rich (e.g., denser) than the middle layer of the tri-layer structure. In some examples, the lower layer may be or may be associated with an original density (i.e., the third layer may have the same density as the untreated barrier material 320). In another example, the tri-layer structure may include a lower layer, which may be more abundant (e.g., denser) with tungsten than the middle layer of the tri-layer structure. In some examples, the upper layer may be or may be associated with an original density (i.e., the third layer may have the same density as the untreated barrier material 520).

FIG. 6 illustrates an example of a fabrication process 600 that supports a memory device having a high resistivity (e.g., low density) thermal barrier in accordance with an example as disclosed herein.

At 605, PVD (e.g., Direct Current (DC) magnetron PV) may be usedD, which may also be referred to as reactive sputtering) to deposit the barrier material. As described herein, a barrier material may be deposited over a stack of memory cells (e.g., memory cell 305 as described with reference to fig. 3), oxide regions (e.g., oxide region 310 as described with reference to fig. 3), and/or vias (e.g., via 315 as described with reference to fig. 3). The plasma used in PVD may be a plasma generated from argon and nitrous molecules (e.g., PVD may be N₂Reactive PVD). Additionally, the material targeted by the plasma may be composed of tungsten and silicon. For example, the material may be WSi_xMaterial, where X may refer to the ratio of silicon atoms relative to tungsten atoms in the target material. In general, X may be a value between 2 and 4 or equal to 2 and 4. For example, X may be equal to 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, or 4.0. In some cases, the barrier material may be deposited via Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any other deposition method. In some cases, the barrier material may be deposited on the semiconductor substrate.

At 610, the deposited barrier material may be exposed to the atmosphere. Exposing the deposited barrier material to the atmosphere may involve a deposition chamber containing the barrier to allow air to enter the deposition chamber. In some cases, the deposition chamber may first create a vacuum to pump out the gases used to create the PVD plasma, and then the deposited barrier material may be exposed to the atmosphere. In this case, atmospheric air may refer to air that is locally located around the deposition chamber (e.g., air within a room containing the deposition chamber), or may refer to air that is pumped or otherwise collected from a remote location (e.g., air from outside the room). Although the present example assumes that the deposited barrier material may be exposed to air, it is possible that the deposited barrier material may be exposed to other gases or specific components of air (e.g., nitrogen, dinitrogen, oxygen, dioxide, water vapor, argon, or carbon dioxide).

At 615, a portion of the barrier material may be masked. For example, as described herein, the barrier material may include a first section (e.g., first section 330 as described with reference to fig. 3) and a second section (e.g., second section 335 as described with reference to fig. 3). One or both of the sections (or one or more subsets of one or more of the sections) may be masked to apply plasma to unmasked sections. This may allow one section (e.g., the unmasked section) to have a lower density and higher resistivity based on the plasma process. In some examples, the masked sections may correspond to areas over one or more memory cells (e.g., memory cells 305, 405 as described with reference to fig. 3 and 4, respectively) or over one or more vias (e.g., via 515 as described with reference to fig. 5). For example, the segments may be masked by using reverse polarity shredding or one or more via based masks.

At 620, it may be determined (e.g., by a controller of the deposition chamber or based on one or more other components or readings) what type of plasma treatment is to be applied to the deposited barrier material. For example, as described with reference to fig. 4, a plasma treatment that increases the thermal resistivity (e.g., reduces density) of the barrier material over the memory cells may be desirable. Different types of plasma processes may use different process times, different deposition chamber temperature functions, different deposition chamber pressure functions, different amounts of constituent molecules (e.g., nitrous or helium) to prepare the plasma for the plasma process, different plasma powers, or combinations thereof. In some cases, the type of plasma treatment may be determined based on an expected density of the low density barrier material, an expected thickness of the low density barrier material, an expected atomic ratio of tungsten-nitrogen bonds to tungsten-silicon bonds in the low density barrier material, a proportion of an expected chemical composition of the low density barrier material, an expected resistivity of the low density barrier material, or a combination thereof. Additionally or alternatively, different types of plasma treatments may be used under different process conditions.

In some cases, exposing the deposited barrier material to the atmosphere (at 610) may not be performed, and a portion of the barrier material may be masked (at 615), or the type of plasma treatment suitable for the deposited barrier material may be determined (at 620) after depositing the barrier material using PVD (at 605). Such a case where a portion of the barrier material may be masked (at 615) or the type of plasma treatment suitable for the deposited barrier material may be determined (at 620) directly after deposition of the barrier material using PVD (at 605) may be referred to as an in-situ backtracking process.

The type of plasma treatment and/or the thickness of the deposited barrier material may affect the density and/or thickness of the resulting low density barrier material. In one example, 150 angstroms can be deposited

A barrier material, and may initially have an initial density and be free of a low density barrier material. In some examples, the initial density may be between 6.356 and 7.156 grams per cubic centimeter (g/cc), 6.456 and 7.056g/cc, 6.556g/cc and 6.956g/cc, 6.656g/cc and 6.856g/cc, or may be about 6.756 g/cc. In that

The first plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having a first density and a first low density barrier material thickness. For example, the first low density barrier material thickness may be inAndand

andor may be aboutAnd the first density can be between 3.3g/cc and 4.1g/cc, 3.4g/cc and 4.0g/cc, 3.5g/cc and 3.9g/cc, 3.6g/cc and 3.8g/cc,or may be about 3.7 g/cc. In thatThe second plasma treatment on the deposited barrier material may produce a low density barrier material or a layer having a bilayer structure of a second density and a second low density barrier material thickness. For example, the second low density barrier material thickness may be inAnd

and

andand

or may be aboutAnd the second density may be between 3.12g/cc and 3.92g/cc, 3.22g/cc and 3.82g/cc, 3.32g/cc and 3.72g/cc, 3.42g/cc and 3.62g/cc, or may be about 3.52 g/cc.

In another example, may be deposited

A barrier material, and may have an initial density and be free of a low density barrier material. The initial density may be between 6.365 and 7.165, 6.465 and 7.065, 6.565 and 6.965, 6.655 and 6.865, or may be about 6.765 g/cc. In that

First plasma treatment on the deposited barrier materialA layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having a first density and a first low density barrier material thickness may be created. The first density may be between 3.35g/cc and 4.15g/cc, 3.45g/cc and 4.05g/cc, 3.55g/cc and 3.95g/cc, 3.65g/cc and 3.85g/cc, or may be about 3.75 g/cc. In thatThe second plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having a second density and a second low density barrier material thickness. The second density may be between 3.11g/cc and 3.91g/cc, 3.21g/cc and 3.81g/cc, 3.31g/cc and 3.71g/cc, 3.41g/cc and 3.61g/cc, or may be about 3.51 g/cc.

Additionally or alternatively, the type of plasma treatment and/or the thickness of the deposited barrier material may affect the atomic ratio of tungsten-nitrogen bonds to tungsten-silicon bonds within the resulting low density barrier material. In one example of the above-described method,the barrier material may be deposited and may have an initial atomic ratio between 0.31 and 0.39, 0.32 and 0.38, 0.33 and 0.37, 0.34 and 0.36, or the initial atomic ratio may be about 0.35. In that

The first plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having an atomic ratio between 0.42 and 0.50, 0.43 and 0.49, 0.44 and 0.48, 0.45 and 0.47, or the atomic ratio may be about 0.46. In thatThe second plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having an atomic ratio between 1.32 and 1.40, 1.33 and 1.39, 1.34 and 1.38, 1.35 and 1.37, or the atomic ratio may be about 1.36.

In another example of the above-described method,the barrier material may be deposited and may have an atomic ratio between 0.33 and 0.41, 0.34 and 0.40, 0.35 and 0.39, 0.36 and 0.38, or the atomic ratio may be about 0.37. In that

The first plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having an atomic ratio between 1.32 and 1.40, 1.33 and 1.39, 1.34 and 1.38, 1.35 and 1.37, or the atomic ratio may be about 1.36. In that

The second plasma treatment on the deposited barrier material may produce a layer of low density barrier material or a bilayer structure (e.g., a bulk layer) having an atomic ratio between 1.99 and 2.07, 2.00 and 2.06, 2.01 and 2.05, 2.02 and 2.04, or the atomic ratio may be about 2.03.

Additionally or alternatively, the type of plasma treatment and/or the thickness of the deposited barrier material may affect the proportion of silicon, tungsten, nitrogen, or a combination thereof, in the low density barrier material or layer of the bilayer structure. For example, the first plasma treatment may generate a proportion of W_PSiN_QAnd the second plasma treatment may produce a proportion of W_RSiN_SWhere P and R may refer to the ratio of tungsten atoms to silicon atoms in the low density barrier material. Q and S may refer to the ratio of nitrogen atoms to silicon atoms in the low density barrier material. P may not equal R and Q may not equal S. In general, P and R may range from 0.5 to 2.0, and Q and S may range from 0.5 to 2.0.

In general, the deposited barrier material can have a density within a range of density values (e.g., between 6.7g/cc and 7.7g/cc, 6g/cc and 9.2g/cc, or 6g/cc and 7.5 g/cc) that can be attributed, at least in part, to PVD process capability and repeatability. In some cases, the lower density of the density value range may be within a range between 5.5g/cc and 6.5g/cc, 5.6g/cc and 6.4g/cc, 5.7g/cc and 6.3g/cc, 5.8g/cc and 6.2g/cc, 5.6g/cc and 6.1g/cc, or may be about 6 g/cc. In some cases, the lower density of the density value range may be within a range between 6.2g/cc and 7.2g/cc, 6.3g/cc and 7.1g/cc, 6.4g/cc and 7.0g/cc, 6.5g/cc and 6.9g/cc, 6.6g/cc and 6.8g/cc, or may be about 6.7 g/cc. In some cases, the upper density of the density value range may be within a range between 7.2g/cc and 8.2g/cc, 7.3g/cc and 8.1g/cc, 7.4g/cc and 8.0g/cc, 7.5g/cc and 7.9g/cc, 7.6g/cc and 7.8g/cc, or may be about 7.7 g/cc. In some cases, the upper density of the density value range may be within a range between 8.7g/cc and 9.7g/cc, 8.8g/cc and 9.6g/cc, 8.9g/cc and 9.5g/cc, 9.0g/cc and 9.5g/cc, 9.1g/cc and 9.3g/cc, or may be about 9.2 g/cc. Additionally, the range may be limited by increasing the difficulty of controlling resistivity (e.g., thermal or electrical) as the amount of nitrous within the PVD plasma (e.g., flow of nitrous) increases.

The low density barrier material may also have a density within a range of density values, such as between 3.5g/cc and 5 g/cc. The lower limit density of the density value range for a layer of a low density barrier material or bilayer structure (e.g., a body layer) can be in a range between 3.0g/cc and 4.0g/cc, 3.1g/cc and 3.9g/cc, 3.2g/cc and 3.8g/cc, 3.3g/cc and 3.7g/cc, 3.4g/cc and 3.6g/cc, or can be about 3.5 g/cc. The upper density of the density value range for the layer of the low density barrier material or bilayer structure may be in the range between 4.5g/cc and 5.5g/cc, 4.6g/cc and 5.4g/cc, 4.7g/cc and 5.3g/cc, 4.8g/cc and 5.2g/cc, 4.9g/cc and 5.1g/cc, or may be about 5 g/cc. Applying a plasma treatment may affect the density of the low density barrier material or layers of the bilayer structure (e.g., the bulk layer) such that the density is below the range of density values for the deposited barrier material, which may reduce the thermal conductivity associated with the low density barrier material relative to the deposited barrier material.

At 625, a plasma may be applied to the deposited barrier material. The plasma may be produced from a gas consisting of molecules of dinitrogen and helium. The plasma may be applied anywhere in a range of durations (e.g., 50 seconds to 100 seconds). The duration of the lower limit density may range between 46 seconds and 54 seconds, between 47 seconds and 53 seconds, between 48 seconds and 52 seconds, between 49 seconds and 51 seconds, or may be about 50 seconds. The upper density may range in duration from 96 seconds to 104 seconds, from 97 seconds to 103 seconds, from 98 seconds to 102 seconds, from 99 seconds to 101 seconds, or may be about 100 seconds. Additionally, the plasma treatment may be associated with any power having a power value in the range of 1kW and 2 kW. The lower power of the power value range may be in a range between 0.6 kilowatts (kW) and 1.4kW, 0.7kW and 1.3kW, 0.8kW and 1.2kW, 0.9kW and 1.1kW, or may be about 1.0 kW. Additionally or alternatively, the lower power of the power value range may be a value equal to or greater than 0.1kW or 0.5 kW. The upper power of the power value range may be in a range between 1.6kW and 2.4kW, 1.7kW and 2.3kW, 1.8kW and 2.2kW, 1.9kW and 2.1kW, or may be about 2.0 kW. Additionally or alternatively, the upper limit may be a value equal to or greater than 2.0 kW. In some cases, the plasma applied at 625 may be the same as the plasma applied at 605. In some cases, the plasma may be applied based on a target resistivity (e.g., thermal or electrical) of the low density barrier material.

At 630, a low density barrier material can be formed on an exposed surface of a portion (e.g., section) of the deposited barrier material. For example, referring to fig. 3, a low density (and relatively high resistivity) barrier material may be formed over the stack of memory cells 305. The low density barrier material may be formed due to the presence of a higher percentage of nitrogen at the surface after treatment by the plasma. Additionally or alternatively, the low density barrier material may be formed of tungsten pumped to the surface of the low density barrier material, which may form a bilayer structure. At the surface, a first layer of the bilayer structure may be denser than a second layer of the bilayer structure adjacent to the first layer, possibly because tungsten is pumped to the denser layer of the bilayer structure. The second layer may be less dense than the deposited barrier material and the first layer may be less dense, as dense or more dense than the deposited barrier material. The bilayer structure may have a lower overall density than the deposited barrier material.

Fig. 7A and 7B illustrate examples of plasma application processes 700-a and 700-B supporting a memory device having a high resistivity thermal barrier in accordance with examples as disclosed herein. In some examples, plasma application processes 700-a and 700-b may implement an example of manufacturing process 600. For example, the plasma application process 700-a may depict an example of the processing step 605 as described with reference to fig. 6. Plasma application process 700-b may simultaneously depict examples of process steps 610 and 625 as described with reference to fig. 6.

With respect to plasma application process 700-a, atmospheric molecules (e.g., air) may be pumped out of deposition chamber 705 to create a vacuum. The nitrogen and argon gases in gaseous form may enter the deposition chamber 705 and fill the vacuum. The nitrous and argon gases may receive thermal energy (e.g., the nitrous and argon gases may be heated) until a plasma comprised of nitrogen and argon ions is formed. Nitrogen and argon ions may contact the target barrier material 710 (e.g., WSi)_XMaterial, where 2 ≦ X ≦ 4), and tungsten and silicon molecules may be eliminated from the target barrier material 710. Tungsten and silicon molecules may fall to exposed surfaces of memory device 715 (e.g., top surfaces of one or more memory cells 305, oxide regions 310, and/or vias 315 as described with reference to fig. 3) and may begin to form barrier material 720 (e.g., WSiN). As barrier material 720 begins to form, tungsten and silicon molecules may begin to fall onto the exposed surfaces of barrier material 720 and increase the thickness of barrier material 720. The memory device may be on a temperature controlled platform.

With respect to plasma application process 700-b, atmospheric molecules (e.g., air) may be pumped out of deposition chamber 705 to create a vacuum. Dinitrogen and, in some cases, helium gas may enter the deposition chamber 705 and fill the vacuum. The nitrous gas may receive thermal energy (e.g., the nitrous gas may be heated using thermal or Radio Frequency (RF) radiation) until a plasma comprised of nitrogen ions is formed. If helium gas also enters deposition chamber 705, the plasma may also contain helium ions. The nitrogen ions may contact the surface of the barrier material 720, pull the tungsten outward, and combine with the tungsten. This process may continue until a low density barrier material (e.g., a low density barrier material as described with reference to fig. 3, such as low density barrier material 320) is formed on the surface of barrier material 720, or, if all of barrier material 720 becomes a low density barrier material, on the surface of memory device 715. In some cases, plasma application process 700-b may be referred to as CVD nitridation.

FIG. 8 shows a flow diagram illustrating a method or method 800 of supporting a memory device having a high resistivity thermal barrier, according to an aspect of the present invention. The operations of method 800 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of a manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware. In some examples, a controller implementing the operations of method 800 may be used to control a deposition control chamber as described with reference to fig. 6 and 7.

At 805, the method 800 may include forming an oxide material. The operations of 805 may be performed according to methods described herein. In some examples, aspects of the operations of 805 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 810, the method 800 may include forming a set of one or more pillars. In some examples, at least one of the set of pillars may be in contact with an oxide material. The operations of 810 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 815, the method 800 may include forming a via through a portion of the oxide material. The operations of 815 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 820, the method 800 can include forming a barrier material over the set of pillars, oxide material, and vias. In some examples, the barrier material can include a first section over at least the set of pillars and a second section over at least the via. The operations of 820 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 825, the method 800 may include applying a plasma to the first section of the barrier material to change a density of the first section from the second density to the first density. In some examples, the second section may have a second density. The operations of 825 may be performed to fabricate a memory array as described with reference to fig. 3-5.

In some examples of the method 800 and apparatus described herein, applying the plasma may include applying the plasma to a top surface of a top portion of the first section, wherein the top portion of the first section includes a first density based on applying the plasma.

Some examples of the method 800 and apparatus described herein may further include determining a target density for the first section of barrier material, and selecting a barrier material having a second density greater than the target density based on determining the target density, wherein applying the plasma to the first section of barrier material may be based on selecting the barrier material to adjust the density of the barrier material from the second density to a first density that may be closer to the target density.

Some examples of the method 800 and apparatus described herein may further include masking a second section of barrier material, wherein applying the plasma to the first section of barrier material may be based on masking the second section of barrier material. Some examples of the method 800 and apparatus described herein may further include etching at least a portion of the oxide material, wherein the set of pillars may be formed at locations adjacent to the oxide material based on etching at least a portion of the oxide material. Some examples of the method 800 and apparatus described herein may further include forming access lines over the barrier material, where the access lines may be configured to communicate through the barrier material.

In some examples of the method 800 and apparatus described herein, the dimension of the second section of barrier material may be the same as the dimension of the via in the first direction. In some examples of the methods 800 and apparatus described herein, a first section of barrier material may be in contact with at least the set of pillars and a second section of barrier material may be in contact with at least the through-holes. In some examples of the method 800 and apparatus described herein, the first density may be lower than the second density. In some examples of the method 800 and apparatus described herein, the barrier material comprises tungsten silicon nitride or the plasma comprises nitrous oxide, helium, or a combination thereof. In some examples of the method 800 and apparatus described herein, the barrier material may comprise a bilayer structure.

In some examples, a manufacturing system as described herein may include features, means, or instructions (e.g., non-transitory computer-readable medium storing instructions executable by a processor) for forming an oxide material; forming a plurality of pillars, at least one of the plurality of pillars being in contact with an oxide material; forming a via through a portion of the oxide material; forming a barrier material over a plurality of pillars, an oxide material, and vias, the barrier material comprising a first section over at least the plurality of pillars and a second section over at least the vias; and applying a plasma to the first section of the barrier material to change the density of the first section from the second density to the first density, the second section having the second density.

In some examples, the feature, means, or instructions for applying the plasma may include applying the plasma to a top surface of a top portion of the first section, wherein the top portion of the first section comprises a first density based at least in part on applying the plasma.

In some examples, the fabrication systems herein may include features, means, or instructions for determining a target density for a first section of barrier material based at least in part on determining the target density and selecting a barrier material having a second density greater than the target density, wherein applying plasma to the first section of barrier material is based at least in part on selecting the barrier material to adjust the density of the barrier material from the second density to a first density closer to the target density.

In some examples, the fabrication systems herein may include features, means, or instructions for masking a second section of the barrier wall material, wherein applying the plasma to the first section of the barrier wall material is based at least in part on masking the second section of the barrier wall material.

In some examples, the fabrication systems herein may include features, means, or instructions for etching at least a portion of an oxide material, wherein the plurality of pillars are formed at a location adjacent to the oxide material based at least in part on etching at least the portion of the oxide material.

In some examples, the fabrication systems herein may include features, means, or instructions for forming access lines over the barrier material, where the access lines are configured to communicate through the barrier material.

In some examples of the methods, means, apparatuses, and non-transitory computer readable media described herein, a dimension of the second section of barrier material is the same as a dimension of the via in the first direction. In some examples of the methods, means, apparatuses, and non-transitory computer readable media described herein, the first section of barrier material is in contact with at least the plurality of pillars and the second section of barrier material is in contact with at least the through-holes.

In some examples of the methods, components, devices, and non-transitory computer readable media described herein, the first density is lower than the second density.

In some examples of the methods, components, apparatus, and non-transitory computer readable media described herein, the barrier material comprises tungsten silicon nitride or wherein the plasma comprises dinitrogen, helium, or a combination thereof.

In some examples of the methods, means, apparatuses, and non-transitory computer readable media described herein, the barrier material comprises a bilayer structure.

FIG. 9 shows a flow diagram illustrating a method or method 900 of supporting a memory device having a high resistivity thermal barrier, according to an aspect of the present invention. The operations of method 900 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of a manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware. In some examples, a controller implementing the operations of method 900 may be used to control a deposition control chamber as described with reference to fig. 6 and 7.

At 905, the method 900 may include forming an oxide material. The operations of 905 may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 910, the method 900 may include forming a set of pillars. In some examples, at least one of the set of pillars may be in contact with an oxide material. The operations of 910 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 915, the method 900 can include forming a via through a portion of the oxide material. The operations of 915 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 920, the method 900 may include determining a target density for the first section of barrier material. The operations of 920 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 925, the method 900 may include selecting a barrier material having a second density greater than the target density based on determining the target density. In some examples, applying the plasma to the first section of the barrier material is based on selecting the barrier material to adjust the density of the barrier material from the second density to a first density closer to the target density. The operations of 925 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 930, the method 900 can include forming a barrier material over the set of pillars, oxide material, and vias. In some examples, the barrier material can include a first section over at least the set of pillars and a second section over at least the via. The operations of 930 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 935, the method 900 can include applying a plasma to the first section of the barrier material to change the density of the first section from the second density to the first density. In some examples, the second section may have a second density. The operations of 935 may be performed to fabricate a memory array as described with reference to fig. 3-5.

FIG. 10 shows a flow diagram illustrating a method or method 1000 of supporting a memory device having a high resistivity thermal barrier, according to an aspect of the present invention. The operations of method 1000 may be performed by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of a manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware. In some examples, a controller implementing the operations of method 1000 may be used to control a deposition control chamber as described with reference to fig. 6 and 7.

At 1005, the method 1000 may include forming an oxide material. The operations of 1005 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 1010, the method 1000 can include forming a set of pillars. In some examples, at least one of the set of pillars may be in contact with an oxide material. The operations of 1010 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 1015, the method 1000 can include forming a via through a portion of the oxide material. The operations of 1015 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 1020, the method 1000 can include forming a barrier material over the set of pillars, oxide material, and vias. In some examples, the barrier material can include a first section over at least the set of pillars and a second section over at least the via. The operations of 1020 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 1025, the method 1000 may include masking a second section of barrier material. In some examples, applying the plasma to the first section of barrier material may be based on masking the second section of barrier material. The operations of 1025 may be performed to fabricate a memory array as described with reference to fig. 3-5.

At 1030, the method 1000 can include applying a plasma to a first section of the barrier material to change a density of the first section from a second density to a first density. In some examples, the second section may have a second density. The operations of 1030 may be performed to fabricate a memory array as described with reference to fig. 3-5.

It should be noted that the methods described above describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are possible. Further, portions from two or more of the methods may be combined.

An apparatus is described. The apparatus may include: a set of pillars over a substrate, each of the set of pillars including a memory cell; an oxide region over the substrate; a via extending through the oxide region to the substrate; a barrier material over the set of pillars, oxide regions, and vias, the barrier material comprising a first section having a first density and a second section having a second density; and an access line located over the barrier material and configured to communicate with each of the memory cells.

In some examples, a first section of barrier material may be located over at least some of the pillars and a first section of the oxide region, and a second section of barrier material may be located over at least the vias and a second section of the oxide region. In some examples, a first section of barrier material may be located over the set of pillars and at least the first section of the oxide region, and a second section of barrier material may be located over the vias, the second section of barrier material corresponding to a width of the vias closest to the barrier material.

In some examples, the second section of barrier material may be limited to the same area as the area of one end of the via. Some examples of an apparatus may include circuitry in contact with a substrate, the circuitry configured to communicate signals with each of the set of memory cells through vias and access lines. In some examples, the second density may be greater than the first density. Some examples may further include that at least a first portion of the first section of barrier material comprises dinitrogen.

In some examples, the barrier material comprises tungsten silicon nitride, and wherein a first portion of a first section of the barrier material may have a higher density of tungsten-nitrogen bonds than a second section of the barrier material. In some examples, the barrier material can be configured to thermally isolate each of the memory cells from the access lines. In some examples, each of the memory cells includes a storage element and a selector device. In some examples, the oxide region can be in contact with at least one of the set of pillars. In some examples, the oxide region can be located on a first side of the via and a second side of the via.

An apparatus is described. The apparatus may include: a pillar including a memory cell and located over a substrate; an oxide region over the substrate and in contact with the pillar; a via in contact with and extending through the oxide region to the substrate; a barrier material comprising a first section and a second section, the first section having a first resistivity and being in contact with at least the pillar, and the second section having a second resistivity and being in contact with at least the via; an access line in contact with a barrier material and configured to communicate signaling to the memory cell.

In some examples, a first section of barrier material may be in contact with at least a section of an access line that is different from a second section of the access line directly above the via.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show the signals as a single signal; however, one of ordinary skill in the art will appreciate that the signals may represent a signal bus, where the bus may have a variety of bit widths.

The terms "in electronic communication," "in conductive contact," "in connection with," and "coupled" may refer to a relationship between components that supports a signal flowing between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there are any conductive paths between the components that can support a signal flowing between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, signal flow between connected components may be interrupted for a period of time, for example using one or more intermediate components such as switches or transistors.

The term "coupled" refers to a condition that moves from an open circuit relationship between components, in which a signal cannot currently be transmitted between the components through a conductive path, to a closed circuit relationship between the components, in which a signal can be transmitted between the components through a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow.

The term "isolation" refers to the relationship between components where signals cannot currently flow between components. If there is an open circuit between the components, they are isolated from each other. For example, components that are spaced apart by a switch positioned between two components are isolated from each other when the switch is open. When the controller isolates two components, the controller implements the following changes: signals are prevented from flowing between components using conductive paths that previously permitted signal flow.

The term "layer" as used herein refers to a layered or thin layer of geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of the surface. For example, a layer may be a three-dimensional structure, where two dimensions are greater than the third dimension, such as a thin film. A layer may comprise different elements, components and/or materials. In some cases, a single layer may be comprised of two or more sublayers. In some of the figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, one skilled in the art will recognize that the layers are three-dimensional in nature.

As used herein, the term "substantially" means that the modified feature (e.g., verb or adjective substantially modified by the term) is not necessarily absolute, but is close enough to obtain the benefit of the feature.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, etc., that provide conductive paths between elements or components of the memory array.

Devices including memory arrays discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during initial formation or growth of the substrate, by ion implantation or by any other doping means.

The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may comprise heavily doped semiconductor regions, for example degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carrier is the signal), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein in connection with the drawings describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "advantageous" over other instances. The detailed description contains specific details that provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label irrespective of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and embodiments are within the scope of the invention and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that perform a function may also be physically located at various positions, including being distributed such that portions of the function are performed at different physical locations. Further, as used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that a list of at least one of, for example, A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Further, as used herein, the phrase "based on" should not be construed as referring to a closed condition set. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the invention. In other words, the phrase "based on" as used herein should likewise be interpreted as the phrase "based at least in part on".

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.