阅读说明：本技术 测试结构，晶圆及测试结构的制作方法
(Test structure, wafer and manufacturing method of test structure
) 是由 刘钊
熊涛
许毅胜 于 2020-06-17 设计创作，主要内容包括：公开了一种集成电路的测试结构,包括多组第一掺杂指和多组第二掺杂指,其中,至少一组所述第一掺杂指和至少一组所述第二掺杂指设置为沿第一方向的交叉指型配置,至少一组所述第一掺杂指和至少一组所述第二掺杂指设置为沿第二方向的交叉指型配置,所述第一方向和所述第二方向垂直。本申请的集成电路的测试结构,能够检测芯片中不同方向的寄生结的击穿特性,同时能够兼顾遮挡效应带来的影响,从而更好的监测了集成电路制造过程中的复杂性,提高了半导体集成电路的良率和可靠性。(A test structure for an integrated circuit is disclosed, comprising a plurality of sets of first doping fingers and a plurality of sets of second doping fingers, wherein at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a first direction, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a second direction, and the first direction and the second direction are perpendicular. The application discloses integrated circuit's test structure can detect the breakdown characteristic of the parasitic junction of equidirectional in the chip, can compromise simultaneously and shelter from the influence that the effect brought to better monitoring the complexity in the integrated circuit manufacturing process, improved semiconductor integrated circuit's yield and reliability.)
1. A test structure for an integrated circuit, comprising:
a plurality of sets of first doping fingers; and
a plurality of sets of second doping fingers are provided,
wherein at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a first direction, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a second direction, and the first direction and the second direction are perpendicular.
2. The test structure of claim 1, further comprising: a doped region, wherein the plurality of sets of second doping fingers are located on the doped region.
3. The test structure of claim 1, further comprising: a plurality of isolation structures, wherein the plurality of isolation structures surround the plurality of sets of first doping fingers, respectively, or the plurality of isolation structures are disposed between the plurality of sets of first doping fingers and the plurality of sets of second doping fingers, respectively.
4. The test structure of claim 1, wherein the plurality of sets of first doping fingers and the plurality of sets of second doping fingers have the same conductivity type.
5. The test structure of claim 4, wherein the doped regions have a conductivity type opposite the plurality of sets of first doped fingers and the plurality of sets of second doped fingers.
6. The test structure of claim 4, wherein the plurality of sets of first doping fingers differ from the plurality of sets of second doping fingers in doping concentration.
7. The test structure of claim 1, further comprising a plurality of sets of third doping fingers formed in the plurality of sets of first doping fingers.
8. The test structure of claim 7, wherein the plurality of sets of first doping fingers, the plurality of sets of second doping fingers, and the plurality of sets of third doping fingers have the same conductivity type.
9. The test structure of claim 7, wherein the plurality of sets of third doping fingers are of the same doping concentration as the plurality of sets of second doping fingers.
10. The test structure of claim 7, further comprising: a plurality of isolation structures, wherein the plurality of isolation structures are respectively disposed between the plurality of sets of first doping fingers and the plurality of sets of second doping fingers.
11. The test structure of claim 10, wherein the third doping finger is immediately adjacent to the isolation structure.
12. The test structure of claim 10, wherein the third doping finger is separate from the isolation structure.
13. The test structure of claim 2, wherein the plurality of sets of first doping fingers, the doped region and the plurality of sets of second doping fingers constitute a plurality of test junctions, and breakdown characteristics of the test structure are collectively determined based on breakdown characteristics of the plurality of test junctions.
14. The test structure of any one of claims 1-13, further comprising: the first conductive line is connected with the plurality of groups of first doping fingers, and the second conductive line is connected with the plurality of groups of second doping fingers.
15. A wafer comprising an array of chips and the test structure of any one of claims 1-14.
16. A method of fabricating a test structure, comprising:
forming a plurality of groups of first doping fingers;
forming a doped region; and
a plurality of sets of second doping fingers are formed in the doped region,
wherein at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a first direction, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a second direction, and the first direction and the second direction are perpendicular.
17. The method of fabricating a test structure according to claim 16, further comprising: forming a plurality of isolation structures, wherein the plurality of isolation structures are respectively disposed between the plurality of sets of first doping fingers and the plurality of sets of second doping fingers.
18. The method of fabricating a test structure according to claim 16 or 17, further comprising: forming a plurality of sets of third doping fingers among the plurality of sets of first doping fingers.
19. The method of claim 18, wherein the plurality of third doping fingers and the plurality of second doping fingers are formed by a same ion implantation process.
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a test structure, a method for manufacturing the test structure, and a wafer.
Background
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given substrate area according to a specified circuit layout. CMOS is formed in millions of integrated circuits because of its superior characteristics in terms of both operating speed and cost efficiency.
Flash memory (Flash) chips need to use much higher voltage than power supply voltage when performing read/write operation (for example, Flash memory chips may use positive high voltage of +11V and negative high voltage of-11V), which results in higher and higher isolation requirements inside devices and/or between different devices in Flash memory chips, and such requirements not only include that the design of the devices (for parasitic PN junctions and parasitic BJTs) needs to be improved continuously, but also include that test structures for testing these parasitic PN junctions and parasitic BJTs need to be improved. With the continuous shrinking of transistor dimensions, the integrated circuit design becomes more and more complex, the shielding effect (shadow effect) of the parasitic PN junction, the parasitic BJT and the ion implantation becomes more and more serious, and the requirement for the test structure becomes higher and higher.
The shielding effect is related to the direction of ion implantation and the thickness of photoresist, the circuit of the memory has different directional configurations due to space limitation during layout, so that the electrical characteristics in the actual integrated circuit structure are different due to different ion implantation directions.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a test structure, which can detect the breakdown characteristics of the parasitic junctions in different directions in the chip by using a plurality of test junctions arranged in an interdigital manner along the first direction and the second direction, and can also take into account the influence of the shielding effect, thereby better monitoring the complexity in the manufacturing process of the integrated circuit and improving the yield and reliability of the semiconductor integrated circuit.
According to an aspect of the invention, a test structure is provided. The test structure includes a plurality of sets of first doping fingers and a plurality of sets of second doping fingers. At least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a first direction, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigital configuration along a second direction, and the first direction and the second direction are perpendicular.
According to another aspect of the invention, a wafer is provided. The wafer comprises a chip array and the test structure.
According to another aspect of the present invention, a method for fabricating a test structure is provided. The method comprises the following steps: forming a plurality of groups of first doping fingers; forming a doped region; and forming a plurality of sets of second doping fingers in the doping region. Wherein the plurality of sets of second doping fingers are formed in the doped region, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigitated configuration along a first direction, at least one set of the first doping fingers and at least one set of the second doping fingers are arranged in an interdigitated configuration along a second direction, the first direction and the second direction being perpendicular.
According to the test structure of the semiconductor integrated circuit, the plurality of test junctions which are arranged in the interdigital mode along the first direction and the second direction respectively can detect the breakdown characteristics of parasitic junctions in different directions in a chip, and meanwhile, the influence caused by a shielding effect can be considered, so that the complexity in the manufacturing process of the integrated circuit is better monitored, the electrical characteristics of circuits in the chip can meet the requirements, and the yield and the reliability of the semiconductor integrated circuit are improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIGS. 1a and 1b are schematic views of a semiconductor wafer;
FIG. 2a is a cross-sectional view of a CMOS chip;
FIG. 2b is a cross-sectional view of a CMOS subject to shadowing effects;
FIG. 3a is a top view of a test structure according to a first embodiment of the present invention;
FIG. 3b is a cross-sectional view of the test structure taken along line A-A' of FIG. 3 a;
FIG. 3c is a schematic illustration of an ion implantation process to form doped regions in a test structure;
FIGS. 3d and 3e are cross-sectional views of the test structure taken along line B-B' of FIG. 3a and having different degrees of influence by the masking effect of the photoresist layer;
FIG. 4a is a flowchart illustrating a method for fabricating a test structure according to a first embodiment of the present invention;
FIGS. 4b-4d are top views of intermediate stages in a process for fabricating a test structure according to a first embodiment of the present invention;
FIG. 5 is a top view of a test structure according to a second embodiment of the present invention;
FIG. 6 is a top view of a test structure according to a third embodiment of the present invention;
FIG. 7 is a top view of a test structure according to a fourth embodiment of the present invention;
FIG. 8a is a top view of a test structure according to a fifth embodiment of the present invention;
FIG. 8b is a cross-sectional view of the test structure taken along line C-C' of FIG. 8 a;
FIG. 8c is a cross-sectional view of the test structure taken along line D-D' of FIG. 8 a;
FIG. 9 is a top view of a test structure according to a sixth embodiment of the present invention;
FIG. 10 is a flowchart illustrating a method of fabricating a test structure according to a fifth embodiment of the present invention;
11a-11e are top views of intermediate stages in the fabrication of a test structure in accordance with fifth embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. The components in the drawings are merely schematic and are not necessarily to scale. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The fabrication of integrated circuits requires the formation of a large number of circuit elements, such as a plurality of NMOS and PMOS, on a specific substrate area according to a specified circuit layout, and in order not to affect the performance of the integrated circuit, isolation between adjacent circuit elements is required, and accordingly, the isolation of the integrated circuit needs to be monitored, such as a parasitic PN junction or a parasitic BJT in the integrated circuit.
The manufacturing process of integrated circuits can be largely divided into three stages: (1) the fabrication of semiconductor wafers, (2) the fabrication of integrated circuits on semiconductor wafers, (3) the dicing, electrical testing, and packaging of integrated circuits. In the fabrication of integrated circuits on a wafer, the substrate is divided into a number of individual chips (dies), and adjacent chips are separated by scribe lines.
When the chip fabrication of an integrated circuit is complete or at an intermediate stage of the fabrication process, the chip needs to be tested to ensure that the fabrication process conforms to design specifications. A typical test method is known as a Wafer Acceptance Test (WAT), which is used to monitor manufacturing process variations by testing certain dummy features (test structures). In wafer acceptance testing, the test structure is electrically connected to external circuitry or probes of a probe card via test pads or test electrodes to inspect the quality of the integrated circuit process.
As shown in fig. 1a and 1b, the wafer comprises a plurality of chips 102 formed on a substrate 101 and at least one test structure 103. The plurality of chips 102 are arranged in an array. The test structure 103 is formed at an edge region between the chips 102 (as shown in fig. 1 a), or at a scribe line region of the wafer (as shown in fig. 1 b). The test structure 103 has the same or similar specifications as the portion of the chip to be monitored, such as width, depth, doping type, doping concentration, etc., for monitoring the breakdown characteristics of the parasitic PN junction and/or the parasitic BJT in the integrated circuit chip region 102.
Fig. 2a is a cross-sectional view of a CMOS chip 102. In chip 102, there are a large number of circuit components, and between adjacent components, such as NMOS and PMOS, parasitic PN junctions and/or parasitic BJTs may be formed. Referring to fig. 2a, the NMOS and PMOS are formed on a P-type substrate 101. Wherein the NMOS includes a P-well 1012, N + doped regions 1015 (source and drain regions), and a gate 1017; the PMOS includes an N-well 1011, P + doped regions 1014 (source and drain regions), and a gate 1016. The NMOS also includes a P + doped region 1019. The P + doped region 1019 is formed in the P-well 1012 as a metal contact window for supplying a P-well voltage (Bulk voltage) to the P-well 1012. The PMOS also includes an N + doped region 1018. An N + doped region 1018 is formed in the N-well 1011 as a metal contact window for supplying an N-well voltage to the N-well 1011. The NMOS and PMOS are separated by a Shallow Trench Isolation (STI) 1013.
In the present description, the conductivity type refers to N-type doping, P-type doping. The P-type impurity (dopant) includes, for example, boron (B), aluminum (Al), gallium (Ga), or indium (In). The N-type impurity includes, for example, phosphorus (P) or arsenic (As). The sign "+" following the doping type is used to illustrate the relative doping concentration. For example, "P +" refers to a higher doping concentration than that of the "P" doped region. But does not mean that the doping concentrations of the P + doped region 1014 and the P + doped region 1019 are the same.
In the structure shown in fig. 2a, the doping concentration of the P-type substrate is about 3x 1012cm-3～1014cm-3(ii) a The doping concentration of the P-well 1012 of the NMOS is about 5x 1016cm-3(ii) a The N + doped region 1015 serves as a source/drain region with a doping concentration of about 1017cm-3～5x1019cm-3(ii) a The doping concentration of the N well 1011 of the PMOS is about 1016cm-3(ii) a P + doped region 1014 as source/drain region having a doping concentration of about 5x 1017cm-3～1018cm-3。
The following parasitic BJTs exist between adjacent NMOS and PMOS. From the source/drain of NMOS (N + doped region 1015), to the P-well 1012 of NMOS, and then to the N-well 1011 of PMOS, forming NPN parasitic BJT. PNP parasitic BJTs are formed from the source/drain (P + doped region 1014) of the PMOS to the N-well 1011 of the PMOS and then to the P-well 1012 of the NMOS. For example, a parasitic PN junction formed from the P well 1012 of the NMOS to the N well 1011 of the PMOS is also included between the adjacent NMOS and PMOS.
The chip 102 in fig. 1a and 1b may be any integrated circuit chip, illustrated here as a Flash chip. The Flash chip comprises a memory cell array and a peripheral circuit, wherein the peripheral circuit comprises a bit line driver (bit line driver), a word line driver (word line driver), a sense amplifier (sense amplifier), a buffer (buffer) and the like. According to the configuration mode of the memory cell array, the Flash chip is divided into NOR Flash and NAND Flash. A typical memory cell is a floating gate transistor (floating gate transistor) that includes a channel region, a source region, a drain region, a tunneling dielectric layer, a floating gate, a control gate, and a dielectric layer between the floating gate and the control gate. In the memory cell array, parasitic structures exist in peripheral circuits.
The P-well 1012, N + doped region 1015, N-well 1011, and P + doped region 1014 in the CMOS shown in fig. 2a are formed by ion implantation and activation processes. For example, N-well 1011 is formed and P-well 1012 is formed. When forming the P-well 1012, the N-well 1011 is masked with a thick photoresist. If the direction of the ion implantation process for forming the P-well 1012 is the direction shown by the arrow in fig. 2b, the ion implantation angle is blocked by the photoresist, so that the blocking effect occurs, the P-well 1012 will be formed at the position shown in fig. 2b, the source/drain (N + doped region 1015) of the NMOS formed in the subsequent process is in the offset P-well, it is difficult to make a small amount of P-well dopant fully diffuse to the whole P-well region predetermined in design through the heat treatment, the P-type substrate is not implanted into the P-well, the doping concentration of the P-type substrate is much lower than that of the P-well, the isolation capability is reduced, the penetration voltage of the parasitic BJT is much lower, and the leakage of the circuit is increased.
In order to monitor whether the parasitic PN junction and the parasitic BJT in the chip are satisfactory, a test structure is formed in the scribe region and/or the edge region of the substrate 101. The test structure includes a plurality of sets of first doping fingers, a doping region, and a plurality of sets of second doping fingers. The doped regions surround the sets of first doping fingers. The plurality of sets of second doping fingers are formed in the doping region. At least one set of first doping fingers and at least one set of second doping fingers extend along a first direction and are arranged in an interdigitated configuration along the first direction, and at least one set of first doping fingers and at least one set of second doping fingers extend along a second direction and are arranged in an interdigitated configuration along the second direction. The first direction and the second direction are different, for example the first direction and the second direction are perpendicular.
The first and second doped fingers arranged in an interdigitated configuration form a test junction. The test structure comprises at least two test junctions, and the interdigital arrangement directions of the at least two test junctions are vertical. The breakdown characteristics of the parasitic junctions in the chip regions corresponding to the test structures are determined by the breakdown characteristics of the at least two test junctions together.
Fig. 3a shows a top view of a test structure 100 according to a first embodiment of the present invention. The test structure 100 includes a first set of first doping fingers 121, a second set of first doping fingers 221, a first set of second doping fingers 122, a second set of second doping fingers 222, and a doping region 124. The first set of second doping fingers 122 and the second set of second doping fingers 222 are formed in the doping region 124. The doped region 124 surrounds the first and second sets of first doping fingers 121 and 221. In other embodiments, the doped region 124 partially surrounds the first and second sets of first doping fingers 121 and 221.
The first group of first doping fingers 121 and the first group of second doping fingers 122 extend along the Y-direction (first direction) and are arranged alternately to form an interdigital configuration. The second group of first doping fingers 221 and the second group of second doping fingers 222 extend along the X-direction (second direction) and are alternately arranged to form an interdigital configuration. The X-direction and the Y-direction are perpendicular.
The test structure 100 shown in fig. 3a comprises three first doping fingers 121, three second doping fingers 122, three first doping fingers 221 and three second doping fingers 222, the number of doping fingers being merely exemplary. The three first doping fingers 121 are connected to a connection portion extending in the X direction. The three first doping fingers 221 are connected to a connection portion extending in the Y direction. The three second doping fingers 122 are connected to a connection portion extending in the X direction. The three second doping fingers 222 are connected to a connection portion extending in the Y direction.
The first doping fingers 121 and 221, the second doping fingers 122 and 222 have a first conductivity type, and the doping region 124 has a second conductivity type. The first conductivity type refers to n-type doping and the second conductivity type refers to p-type doping, or the first conductivity type refers to p-type doping and the second conductivity type refers to n-type doping. The first and second sets of first doping fingers 121 and 221 have the same doping concentration, and the first and second sets of second doping fingers 122 and 222 have the same doping concentration. In some embodiments, the doping concentration of the first doping fingers 121 and 221 is the same as the doping concentration of the second doping fingers 122 and 222. In some embodiments, the doping concentration of the first doping fingers 121 and 221 is different from the doping concentration of the second doping fingers 122 and 222. For example, the doping concentration of the second doping fingers 122 and 222 is higher than that of the first doping fingers 121 and 221. In this example, the first doping fingers 121 and 221 are N-type doped with a doping concentration equal to that of the N-well 1011 in fig. 2a, the second doping fingers 122 and 222 are also N-type doped with a doping concentration equal to that of the N + doping region 1015 in fig. 2a, and the doping region 124 is P-type doped with a doping concentration equal to that of the P-well 1012 in fig. 2 a.
The doped region 124 is provided with a connection window 1241 of an electrode for providing a breakdown test voltage V1, such as a P-well voltage, to the doped region 124. A connection window 1211 for an electrode is disposed on the connection portion of the first group of first doping fingers 121, and a connection window 2211 for an electrode is disposed on the connection portion of the second group of first doping fingers 221, so that a breakdown test voltage V2, for example, an N-well voltage, may be provided to the first group of first doping fingers 121 and the second group of first doping fingers 221. The connection portion of the first group of second doping fingers 122 is provided with a connection window 1221 of an electrode, and the connection portion of the second group of second doping fingers 222 is provided with a connection window 2221 of an electrode, so that a breakdown test voltage V3, for example, 0 to 10V, can be provided to the second doping fingers 122 and 222. The arrangement position of the connection window of the electrode is not limited to the position shown in fig. 3 a.
Fig. 4a is a flowchart of a method for manufacturing a test structure 100 according to a first embodiment of the invention. Fig. 4b-4d are top views of intermediate stages in the fabrication process of test structure 100.
In step S101, a first group of first doping fingers 121 and a second group of first doping fingers 221 are formed in the substrate 101 of the test structure region on the wafer. The first doping fingers 121 extend along the Y direction, and the second doping fingers 221 extend along the X direction. The first and second sets of first doping fingers 121 and 221 are formed by ion implantation and activation processes. The activation process is, for example, Rapid thermal Processing (Rapid thermal Processing) or laser annealing (LaserAnnealing).
The first doping fingers 121 and 221 are, for example, N-type doping regions, formed by implanting N-type impurities and activating, and the first doping fingers 121 and 221 and the N-well 1011 in the chip 102 use the same ion implantation and activation process parameters. Preferably, the first doping fingers 121 and 221 and the N-well 1011 in the chip 102 are formed by the same ion implantation and activation process. A top view of the first doping fingers 121 and 221 formed is shown in fig. 4 b.
In step S102, a doped region 124 is formed in the substrate 101 of the test structure region, and the doped region 124 surrounds the first group of first doping fingers 121 and the second group of first doping fingers 221. The doped region 124 is formed by an ion implantation and activation process. The doped region 124 is, for example, a P-type doped region, and is formed by implanting P-type impurities and activating. The same ion implantation and activation process parameters are used for the doped region 124 and the P-well 1012 in the wafer 102. While performing the ion implantation process of the doped region 124, a photoresist layer is covered on the first and second sets of first doping fingers 121 and 221 such that the first doping fingers 121 and 221 are not affected by the ion implantation process of forming the doped region 124. The thickness of the photoresist layer covering the first doping fingers 121 and 221 is the same as the thickness of the photoresist layer covering the N-well 1011 when the P-well 1012 is formed in the chip 102. Preferably, the doped region 124 and the P-well 1012 in the wafer 102 are formed by the same ion implantation and activation process.
The photoresist layer on the first doping fingers 121 and 221 may have a shielding effect on the ion implantation process of the doping region 124. For example, the direction of the ion implantation is in the plane defined by the Z-direction and the Y-direction, and is offset from the Z-direction by a certain angle (e.g., 5 degrees to 15 degrees), then the photoresist layer on the second set of first doping fingers 221 will have a shielding effect on the ion implantation process of the doped region 124. In this ion implantation direction, the top view of the first doping fingers 121 and 221 and the doping region 124 is shown in FIG. 4c, the regions 129-1, 129-2, 129-3 and 129-4 are not implanted with P-type impurities due to the shielding effect, and the doping concentration is still equal to the doping concentration of the substrate. In the case that the direction of the ion implantation is in the plane defined by the Z direction and the X direction, and deviates from the Z direction by a certain angle, the photoresist on the first group of first doping fingers 121 may have a shielding effect on the ion implantation process of the doping region 124, as shown in fig. 3 c.
In step S103, a first group of second doping fingers 122 and a second group of second doping fingers 222 are formed in the doping region 124. Wherein the first set of second doping fingers 122 extend along the Y-direction and are arranged in an interdigital configuration with the first set of first doping fingers 121 in the Y-direction, and the second set of second doping fingers 222 extend along the X-direction and are arranged in an interdigital configuration with the second set of first doping fingers 221 in the X-direction. The first set of second doping fingers 122 and the second set of second doping fingers 222 are also formed by an ion implantation and activation process. For example, the first doping fingers 121 and 221 are N-doped regions, the doping region 124 is a P-doped region, the second doping fingers 122 and 222 are N + doped regions, and the second doping fingers 122 and 222 are formed by implanting N-type impurities and activating. The second doping fingers 122 and 222 and the N + doped regions in the wafer 102 use the same ion implantation and activation process parameters. Preferably, the second doping fingers 122 and 222 and the N + doping region 1015 in the chip 102 are formed through the same ion implantation process. When the ion implantation process of the second doping fingers 122 and 222 is performed, the first doping fingers 121 and 221 and the doping region 124 are covered with photoresist, and the portion of the doping region 124 for forming the second doping fingers 122 and 222 is not covered with photoresist. Fig. 4d shows a top view of the first doping fingers 121 and 221, the doping region 124, and the second doping fingers 122 and 222 after step S103.
After the first set of first doping fingers 121, the second set of first doping fingers 221, the doping region 124, the first set of second doping fingers 122, and the second set of second doping fingers 222 are formed, an insulating layer is formed on the first set of first doping fingers 121, the second set of first doping fingers 221, the doping region 124, the first set of second doping fingers 122, and the second set of second doping fingers 222. Openings are formed in the insulating layer to form electrode connection windows 1211, 1221, 2211, 2221 and 1241. In order to reduce contact resistance, an N + doped region/P + doped region is disposed between the N/P doped region and the electrode. The first doping fingers 121 and 221, the doping region 124, and the second doping fingers 122 and 222 may be connected to the corresponding pads through wires using the connection windows 1211, 1221, 2211, 2221, and 1241 of the electrodes.
Fig. 3b is a cross-sectional view taken along line a-a' in fig. 3 a. In the present embodiment, the ion implantation direction of the doped region 124 is in the plane defined by the Z direction and the Y direction and is deviated from the Z direction by a certain angle, so that the photoresist layer on the first group of first doping fingers 121 has substantially no shielding effect on the ion implantation of the doped region 124, and the photoresist layer on the second group of first doping fingers 221 has shielding effect on the ion implantation of the doped region 124. In other embodiments, the ion implantation direction of the doped region 124 is in a plane defined by the Z direction and the X direction and is offset from the Z direction by a certain angle, and at this time, the photoresist layer on the second group of first doping fingers 221 has substantially no influence on the ion implantation of the doped region 124, and the photoresist layer on the first group of first doping fingers 121 has a shielding influence on the ion implantation of the doped region 124. As shown in fig. 3b, the first group of first doping fingers 121 and the doping region 124 are formed at predetermined positions in the X direction.
Fig. 3c illustrates the shadowing effect during the ion implantation process for forming the doped region 124. The photoresist layer PR on the second set of first doping fingers 221 blocks the ion beam, resulting in a blocking effect, and the formed doped region 124 deviates from a predetermined forming position. A desired doped but undoped region having a length d depending on the angle of ion implantation and the thickness of the photoresist layer PR exists between the formed doped region 124 and the first doping finger 221, and the impurity concentration of the region is the same as that of the substrate 101.
Fig. 3d and 3e are cross-sectional views of the test structures of fig. 3a taken along line B-B' to different degrees of influence of the occlusion effect. The occlusion effect is more severe in the embodiment shown in fig. 3e than in the embodiment shown in fig. 3 d. In the embodiment shown in fig. 3e, the region between the second doping finger 222 and the first doping finger 221 on its (-X) direction side is not doped due to the shadowing effect, i.e. the doped region 124 is not formed in this region, and the breakdown characteristics are affected.
In the test structure 100, the first doping finger 121, the doping region 124 and the second doping finger 122 constitute a first test junction, and the first doping finger 221, the doping region 124 and the second doping finger 222 constitute a second test junction. The breakdown characteristic of the test structure 100 is determined by the breakdown characteristic of the first test junction and the breakdown characteristic of the second test junction together. Taking the first test junction as an example, the method for testing the breakdown characteristic includes: a first wire (not shown) applies a voltage of 0V (V1) across the doped region 124 through the electrode connection window 1241, a second wire (not shown) applies a voltage of 0V (V2) across the first set of first doped fingers 121 through the electrode connection window 1211, a third wire (not shown) applies a voltage V3 across the first set of second doped fingers 122 through the electrode connection window 1221, the voltage V3 is gradually increased to 10V, and the value of the voltage V3 applied across the first set of second doped fingers 122 is recorded as the breakdown voltage of the first test junction when the current between the electrode 1211 and the electrode 1221 is greater than a threshold value. Likewise, the breakdown voltage of the second test junction may be obtained. According to the breakdown characteristics of the multiple test junctions, the breakdown characteristics of the parasitic junction and the parasitic BJT in the chip 102 can be monitored to ensure that the electrical characteristics of the circuit in the chip 102 meet the requirements.
Fig. 5 is a top view of a test structure according to a second embodiment of the invention. The test structure 200 includes a first set of first doping fingers 121, a second set of first doping fingers 221, a first set of second doping fingers 122, a second set of second doping fingers 222, and a doping region 124. The first set of first doping fingers 121, the second set of first doping fingers 221, the first set of second doping fingers 122, the second set of second doping fingers 222 having a first conductivity type, the doping region 124 having a second conductivity type, the second conductivity type being opposite to the first conductivity type. The doped region 124 partially surrounds the first doping fingers 121 and 221. Second doping fingers 122 and 222 are formed in the doping region 124. The doping concentration of the first doping fingers 121 and 221 is less than the doping concentration of the second doping fingers 122 and 222.
As shown in fig. 5, a first group of third doping fingers 123 and a second group of third doping fingers 223 are disposed in the first group of first doping fingers 121 and the second group of first doping fingers 221, respectively. The first and second sets of third doping fingers 123 and 223 are smaller than the depths of the first and second sets of first doping fingers 121 and 221. The first set of third doping fingers 123, the second set of third doping fingers 223, the first set of first doping fingers 121 and the second set of first doping fingers 221 have the same conductivity type. The third doping fingers 123 and 223 have a higher doping concentration than the first doping fingers 121 and 221. Connection windows 1211 and 2211 of the electrodes are disposed on the third doping fingers 123 and 223, respectively. In some embodiments, the third doping fingers 123 and 223 and the second doping fingers 122 and 222 have the same doping concentration. In some embodiments, the third doping fingers 123 and 223 and the second doping fingers 122 and 222 are formed through the same ion implantation process.
Fig. 6 is a top view of a test structure according to a third embodiment of the present invention. The test structure 300 is substantially the same as the test structure 100 in FIG. 3a, and the same reference numerals are omitted here for brevity. The first and second sets of first doping fingers 121 and 221 are connected by a conductive line 1261, and the first and second sets of second doping fingers 122 and 222 are connected by a conductive line 1262. For example, the wires 1261 connect the connection windows 1211 and 2211 of the electrodes of the first and second groups of first and second doping fingers 121 and 221, the wires 1262 connect the connection windows 1221 and 2221 of the electrodes of the first and second groups of second doping fingers 122 and 222, and the wires 1261 and 1262 are further connected to corresponding test pads. Thus, the breakdown voltage of the test structure 300 can be obtained through one test without separately testing the breakdown voltages of the first test junction and the second test junction, thereby reducing the number of test steps.
FIG. 7 is a top view of a test structure according to a fourth embodiment of the present invention. The test structure 400 is substantially the same as the test structure 100 in FIG. 3a, and the same reference numerals are omitted here for brevity. Test structure 400 also includes isolation structures 125 and 225. The isolation structure 125 surrounds the first set of first doping fingers 121 and the isolation structure 225 surrounds the second set of first doping fingers 221. The isolation structures 125 and 225 are, for example, shallow trench isolations. The isolation structures 125 and 225 may be formed prior to the first set of first doping fingers 121, the second set of first doping fingers 122 and the doped region 124. Isolation structures 125 and 225 have the same parameters (e.g., width, depth, fill material) as, for example, shallow trench isolation between NMOS and PMOS in chip 102. In the test structure 400 shown in fig. 7, the second doping fingers 122 and 222 are separated from the isolation structures 125 and 225 by the doped region 124.
Fig. 8a is a top view of a test structure according to a fifth embodiment of the present invention. FIG. 8b is a cross-sectional view of the test structure taken along line C-C' of FIG. 8 a. FIG. 8c is a cross-sectional view of the test structure taken along line D-D' in FIG. 8 a.
The test structure 500 includes a first set of first doping fingers 121, a second set of first doping fingers 221, a first set of second doping fingers 122, a second set of second doping fingers 222, a first set of third doping fingers 123, a second set of third doping fingers 223, a doping region 124, isolation structures 125 and 225. In the present embodiment, the direction of the ion implantation forming the doped region 124 is in the plane defined by the Z-direction and the Y-direction, and is offset from the Z-direction by an angle (e.g., 5 degrees to 15 degrees).
The first set of first doping fingers 121 and the doping regions 124 are separated by an isolation structure 125, and the second set of first doping fingers 221 and the doping regions 124 are separated by an isolation structure 125. It should be noted that, under the isolation structure 125, the first doping finger 121 and the doping region 124 may contact (as shown in fig. 8 b), and under the isolation structure 225, the first doping finger 221 and the doping region 124 may contact (as shown in fig. 8 c). The isolation structures 125 and 225 are, for example, shallow trench isolations.
The first group of first doping fingers 121 and the first group of second doping fingers 122 extend along the Y direction. The first group of first doping fingers 121 and the first group of second doping fingers 122 are alternately arranged and disposed in an interdigital configuration along the Y direction. The second set of first doping fingers 221 and the second set of second doping fingers 222 extend along the X-direction. The second group of first doping fingers 221 and the second group of second doping fingers 222 are alternately arranged and disposed in an interdigital configuration along the X-direction.
The first group of third doping fingers 123 is formed in the first group of first doping fingers 121, and the depth of the first group of third doping fingers 123 is less than that of the first group of first doping fingers 121. The second set of third doping fingers 223 is formed in the second set of first doping fingers 221, and the depth of the second set of third doping fingers 223 is less than the depth of the second set of first doping fingers 221. The first set of second doping fingers 122 and the second set of second doping fingers 222 are formed in the doping region 124. The first doping fingers 121 and 221, the second doping fingers 122 and 222, the third doping fingers 123 and 223 have a first conductivity type, and the doping region 124 has a second conductivity type. The second conductivity type is opposite to the first conductivity type.
The first set of third doping fingers 123 is immediately adjacent to the isolation structure 125 and the second set of third doping fingers 223 is immediately adjacent to the isolation structure 225. The first set of second doping fingers 122 is in close proximity to the isolation structure 125 and the second set of second doping fingers 222 is in close proximity to the isolation structure 225. This may reflect the breakdown characteristics in the extreme case of the design rule (design rule). In other embodiments, the third doping fingers 123 and 223 may be spaced apart from the isolation structures 125 and 225, and the second doping fingers 122 and 222 may also be spaced apart from the isolation structures 125 and 225.
The first set of first doping fingers 121 and the second set of first doping fingers 221 are formed prior to the doping region 124. In the case where the direction of the ion implantation for forming the doped region 124 is in the plane defined by the Z-direction and the Y-direction and is offset from the Z-direction by a certain angle, the photoresist layer on the first set of first doping fingers 121 has no shielding effect on the ion implantation for forming the doped region 124 (as shown in fig. 8 b), and the photoresist layer on the second set of first doping fingers 221 has shielding effect on the ion implantation for forming the doped region 124 (as shown in fig. 8 c). As shown in fig. 8c, the doped region 124 is not completely formed at the predetermined position, and a region having a doping concentration equal to that of the substrate 101 exists between the first doping finger 221 and the second doping finger 222.
The doping concentration of the second doping fingers 122 and 222 is higher than that of the first doping fingers 121 and 221. The doping concentration of the third doping fingers 123 and 223 is also higher than that of the first doping fingers 121 and 221. In some embodiments, the third doping fingers 123 and 223 and the second doping fingers 122 and 222 have the same doping concentration.
In one example, the first and second sets of first and second doping fingers 121 and 221 are N-doped regions, the first and second sets of second doping fingers 122 and 222 are N + doped regions, the doped region 124 is a P-doped region, and the first and second sets of third doping fingers 123 and 223 are N + doped regions. Although the second doping fingers 122 and 222 and the third doping fingers 123 and 223 are both N + doping regions in this description, the doping concentrations of the second doping fingers 122 and 222 and the third doping fingers 123 and 223 are not necessarily the same. For example, the doping concentration and depth of the first doping fingers 121 and 221 are equal to the doping concentration and depth of the N-well 1011 of fig. 2, the doping concentration and depth of the second doping fingers 122 and 222 are equal to the doping concentration and depth of the N + doping region 1015 of fig. 2, the doping concentration and depth of the doping region 124 are equal to the doping concentration and depth of the P-well 1012 of fig. 2, and the doping concentration and depth of the third doping fingers 123 and 223 are equal to the doping concentration and depth of the N + doping region 1018 of fig. 2.
Test structure 500 includes two test junctions. One of the test junctions is comprised of a first set of third doping fingers 123, a first set of first doping fingers 121, a doping region 124 and a first set of second doping fingers 122. Another test junction is comprised of a second set of third doping fingers 223, a second set of first doping fingers 221, a doped region 124/substrate doping concentration region, and a second set of second doping fingers 222. In testing the breakdown characteristics, a test voltage V1 is applied to the third doping fingers 123 and 223, a test voltage V2 is applied to the doping region 124, a test voltage V3 is applied to the second doping fingers 122 and 222, and a voltage V3 at which the test junction breaks down is recorded as a breakdown voltage of the test junction. The breakdown voltage of test structure 500 is determined based on the breakdown voltages of the two test junctions.
Fig. 10 is a flow chart of a method of fabricating a test structure 500. Fig. 11a-11e are top views of intermediate stages in the fabrication process of test structure 500.
In step S201, isolation structures 125 and 225 are formed in the test structure region on the wafer. The isolation structure formation steps include, for example, etching a trench, filling with an insulating material, and planarizing. The insulating material includes, for example, silicon dioxide, silicon nitride. A top view of the resulting isolation structures 125 and 225 is shown in fig. 11 a.
In step S202, a plurality of sets of first doping fingers are formed. The sets of first doping fingers are formed in the regions defined by the isolation structures 125 and 225. The plurality of sets of first doping fingers includes, for example, a first set of first doping fingers 121 and a second set of first doping fingers 221. The first set of first doping fingers 121 extend along the Y-direction and the second set of first doping fingers 221 extend along the X-direction. The first set of first doping fingers 121 and the second set of first doping fingers 221 are formed as shown in fig. 11 b. The plurality of sets of first doping fingers are formed by an ion implantation and activation process. When the ion implantation process is performed, the photoresist covers half of the isolation structure so that the dopant can be implanted under the isolation structure.
In step S203, a plurality of sets of third doping fingers are formed in the plurality of sets of first doping fingers. The plurality of sets of third gate doping fingers includes, for example, a first set of third doping fingers 123 and a second set of third doping fingers 223. The plurality of sets of first doping fingers are formed by an ion implantation and activation process. For example, the dosage of the ion implantation for forming the third doping finger is larger than that of the ion implantation for forming the first doping finger, or the capability of the ion implantation for forming the third doping finger is smaller than that of the ion implantation for forming the first doping finger. The area of the third doping finger and the area of the first doping finger may be the same (as in fig. 11c), so that the third doping finger and the isolation structure are in close proximity. In other embodiments, the third doping finger has an area smaller than the area of the first doping finger, such that the third doping finger is spaced apart from the isolation structure by a distance.
In step S204, the doped region 124 is formed. The doped region 124 is formed by an ion implantation and activation process. When the ion implantation process is performed, the photoresist covers half and all of the first doping fingers/third doping fingers of the isolation structure, so that the dopant can be implanted under the isolation structure. In the present embodiment, the ion implantation direction of the doped region 124 is in a plane defined by the Z-direction and the Y-direction and is offset at an angle from the Z-direction. The photoresist layer on the second set of first doping fingers 221 has a shielding effect on the ion implantation of the doping region 124, as shown in fig. 11 d.
In step S205, a plurality of sets of second doping fingers are formed in the doping region 124. The plurality of sets of second doping fingers includes, for example, the first set of second doping fingers 122 and the second set of doping fingers 222. The first set of second doping fingers 122 extend along the Y direction and alternate with the first set of first doping fingers 121 to form an interdigitated configuration in the Y direction. The second set of second doping fingers 222 extend along the X-direction and are arranged alternately with the second set of first doping fingers 221 to form an interdigital configuration in the X-direction, as shown in fig. 11 e.
In the above-described method for fabricating the test structure, the isolation structure is not necessarily formed prior to the plurality of sets of first doping fingers and doping regions. For example, a plurality of sets of first doping fingers may be formed first, and then doped regions may be formed. For another example, after forming a plurality of sets of first doping fingers and doping regions, an isolation structure is formed. For another example, after forming the plurality of sets of first doping fingers, the plurality of sets of second doping fingers, the plurality of sets of third doping fingers and the doping regions, the isolation structure is formed.
Fig. 9 is a top view of a test structure 600 according to a sixth embodiment of the invention. The test structure 600 is substantially the same as the test structure 500 in FIGS. 8a-8c, and the same reference numerals are omitted here for brevity. In the test structure 500 in fig. 8a-8c, the isolation structures 125 surround the first set of first doping fingers 121 and the isolation structures 225 surround the second set of first doping fingers 221. In the test structure 600 shown in fig. 9, the isolation structures 125 are disposed only between the first set of first doping fingers 121 and the doped regions 124, and the isolation structures 225 are disposed only between the second set of first doping fingers 221 and the doped regions 124. In the test structure 500 of fig. 8a-8c, the first set of third doping fingers 123 is in close proximity (direct contact) with the isolation structure 125 and the second set of third doping fingers 223 is in close proximity (direct contact) with the isolation structure 225. In the test structure 600 shown in fig. 9, the third doping finger 123 is spaced apart from the isolation structure 125 and occupied by the first doping finger 121, and the third doping finger 223 is spaced apart from the isolation structure 225 and occupied by the first doping finger 221.
In some CMOS formation processes, a P well is formed before an N well, that is, after the P well is formed, the N well is formed by injecting N-type impurities, and the formation position of the N well may be shifted due to a shadow effect. Correspondingly, the first doping fingers 121, the second doping fingers 221, the first doping fingers 122, and the second doping fingers 222 in the test structure 100-600 have P-type doping, and the doping region 124 has N-type doping.
The test structure provided by the application can be used for testing the breakdown voltage of the parasitic BJT in the chip, and the breakdown voltage of the parasitic BJT in the chip is determined according to the breakdown voltages of the plurality of test junctions, so that the process in the chip manufacturing process is monitored, and the yield and the reliability of the chip are improved.
Furthermore, in the plurality of test junctions of the test structure, the first doping fingers and the second doping fingers in part of the test junctions are arranged in an interdigital configuration along the first direction, and the first doping fingers and the second doping fingers in part of the test junctions are arranged in an interdigital configuration along the second direction, so that electronic components in different arrangement directions in a chip can be better monitored, the monitoring accuracy of parasitic BJTs in the chip is improved, and the yield and the reliability of the chip are further improved.
The invention also provides a wafer, which comprises a plurality of chips and at least one test structure. The at least one test structure is disposed in a scribe area and/or an edge area of the wafer.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
