Semiconductor device package and method of manufacturing the same

文档序号：973297 发布日期：2020-11-03 浏览：3次中文

阅读说明：本技术 半导体设备封装和其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由颜尤龙博恩·卡尔·艾皮特凯·史提芬·艾斯格于 2019-07-24 设计创作，主要内容包括：本公开的至少一些实施例涉及一种半导体设备封装。所述半导体设备封装包含载体、囊封体和天线,所述载体具有第一表面和与所述第一表面相对的第二表面。所述囊封体安置于所述载体的所述第一表面上。所述天线安置于所述囊封体上。所述天线包含晶种层和导电层。(At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite the first surface, an encapsulation, and an antenna. The encapsulation is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation. The antenna includes a seed layer and a conductive layer.)

1. A semiconductor device package, comprising:

a carrier having a first surface and a second surface opposite the first surface;

an encapsulation disposed on the first surface of the carrier; and

an antenna disposed on the encapsulation, the antenna comprising a seed layer and a conductive layer.

2. The semiconductor device package of claim 1, wherein the conductive layer is separated from the encapsulation by the seed layer.

3. The semiconductor device package of claim 1, wherein an upper surface of the antenna is lower than an upper surface of the encapsulation.

4. The semiconductor apparatus package of claim 1, further comprising a shielding layer disposed on the first surface of the carrier.

5. The semiconductor device package of claim 4, wherein the shielding layer comprises a seed layer and a conductive layer.

6. The semiconductor device package of claim 4, wherein the encapsulation encapsulates the antenna and the shielding layer.

7. The semiconductor device package of claim 1, wherein the antenna further comprises a protective layer disposed on the seed layer and the conductive layer.

8. The semiconductor device package of claim 1, wherein the carrier includes a first conductive layer proximate the encapsulation and a second conductive layer proximate the second surface.

9. The semiconductor device package of claim 8, wherein the carrier further comprises a seed layer, and wherein the seed layer is disposed between the first conductive layer and the second conductive layer.

10. The semiconductor device package of claim 1, wherein the carrier comprises a quad flat no lead (QFN) structure.

11. A semiconductor device package, comprising:

a carrier having a first surface and a second surface opposite the first surface, the carrier comprising a first layer proximate the first surface and a second layer proximate the second surface, the second layer comprising a bilayer; and

an encapsulation disposed on the first surface of the carrier,

an antenna disposed on the encapsulation, the antenna comprising a seed layer and a conductive layer,

wherein a material of one of the seed layer and the conductive layer of the antenna is the same as a material of one of the bi-layers of the second layer.

12. The semiconductor device package of claim 11, wherein the conductive species in the second layer is greater in content than the conductive species in the first layer.

13. The semiconductor apparatus package of claim 11, wherein the antenna is disposed in a trench on a surface of the encapsulation.

14. The semiconductor device package of claim 13, wherein one of the bi-layers comprises substantially the same material as the seed layer.

15. The semiconductor apparatus package of claim 11, further comprising a shielding layer disposed on the first surface of the carrier.

16. The semiconductor device package of claim 15, wherein the shielding layer comprises a seed layer and a conductive layer.

17. The semiconductor device package of claim 15, wherein the shielding layer surrounds the antenna.

18. A method of manufacturing a semiconductor package apparatus, comprising:

providing a carrier comprising a first patterned layer proximate a first surface of the carrier;

encapsulating the carrier by an encapsulation body;

forming a trench in the encapsulation;

forming a conductive layer in the trench and on the carrier; and

after forming the conductive layer in the trench and on the carrier, forming a second patterned layer proximate a second surface of the carrier, the second surface being opposite the first surface.

19. The method of claim 18, wherein a seed layer is formed in the trench prior to forming the conductive layer in the trench and on the carrier.

20. The method of claim 18, wherein the conductive layer is formed by an electroplating operation.

21. The method of claim 19, wherein the conductive layer and the seed layer are ground to form an antenna.

22. The method of claim 19, wherein the conductive layer and the seed layer are ground to form a masking layer.

23. The method of claim 18, wherein forming the conductive layer on the carrier comprises electroplating the conductive layer proximate to the second surface of the carrier.

24. The method of claim 23, wherein electroplating the conductive layer proximate the second surface of the carrier is performed simultaneously with forming an antenna.

25. The method of claim 23, wherein electroplating the conductive layer proximate the second surface of the carrier is performed simultaneously with forming a shield layer.

26. The method of claim 18, further comprising disposing at least one semiconductor apparatus on the carrier prior to encapsulating the carrier.

27. The method of claim 18, wherein forming the trench further comprises forming a first trench having a first trench depth from an upper surface of the encapsulation and forming a second trench having a second trench depth in the encapsulation, wherein the second trench depth is greater than the first trench depth.

28. The method of claim 18, wherein the first patterned layer is formed by a half-etch operation.

29. The method of claim 18, wherein the second patterned layer is formed by a half-etch operation.

30. A semiconductor device package, comprising:

a carrier;

a first semiconductor device disposed on the carrier;

a first encapsulation disposed on the carrier, the encapsulation encapsulating the first semiconductor device and the carrier;

a patterned conductive layer embedded in the encapsulation, the patterned conductive layer including an upper surface exposed from the first encapsulation; and

a second encapsulation disposed on the first encapsulation.

31. The semiconductor device package of claim 30, further comprising an antenna disposed on the second encapsulant, the antenna including a seed layer and a conductive layer.

32. The semiconductor apparatus package of claim 31, further comprising a shielding layer disposed on the patterned conductive layer, wherein the shielding layer comprises a seed layer and a conductive layer.

33. The semiconductor apparatus package of claim 32, further comprising a second semiconductor apparatus disposed on the first encapsulation and electrically connected to the patterned conductive layer.

34. The semiconductor device package of claim 33, wherein the second semiconductor device, the antenna, the shielding layer are encapsulated by the second encapsulation, and wherein an upper surface of the antenna and an upper surface of the shielding layer are exposed through the second encapsulation.

35. The semiconductor device package of claim 30, wherein the patterned conductive layer comprises a seed layer.

36. The semiconductor device package of claim 35, wherein the patterned conductive layer comprises conductive pads and conductive traces.

37. The semiconductor device package of claim 30, wherein the patterned conductive layer comprises an antenna.

Technical Field

The present disclosure relates to a semiconductor device package including an antenna including a seed layer and a conductive layer.

Background

The antenna is formed by a plating operation and is disposed on an upper surface of a molding compound of the IC package. During the electroplating operation, the back side of the substrate may be protected by an adhesion layer in order to avoid plating of the conductive material on the back side of the substrate. However, residues of the adhesive may remain on the backside of the substrate after the removal operation.

The substrate may be replaced by a metal frame. However, the metal frame may be easily deformed during the heating operation.

A shielding layer may be included in the semiconductor package to shield an integrated circuit within the semiconductor package from electromagnetic interference. An antenna may be included instead of the shielding layer. In another case, both an antenna and a shielding layer may be included. The thickness of the shielding layer may depend on whether the shielding layer is intended to block electromagnetic interference signals having a high frequency or a low frequency. High frequency means 0.5GHz to 6GHz, and low frequency means 10MHz to 100 MHz. For example, in order to achieve the effect of shielding, due to a tunneling effect of a low frequency signal, a thickness of a shielding layer for blocking electromagnetic interference (EMI) having a relatively low frequency is thicker than a thickness of a shielding layer for blocking electromagnetic interference having a relatively high frequency. However, if the shield layer having a greater thickness is formed by a sputtering operation, higher cost and longer manufacturing time are incurred, and thus lower yield is incurred.

Disclosure of Invention

In some embodiments, according to one aspect of the present disclosure, a semiconductor device package includes a carrier having a first surface and a second surface opposite the first surface, an encapsulation, and an antenna. The encapsulation is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation. The antenna includes a seed layer and a conductive layer.

In some embodiments, according to one aspect of the present disclosure, a semiconductor device package includes a carrier having a first surface and a second surface opposite the first surface, an encapsulation, and an antenna. The carrier includes a first layer proximate the first surface and a second layer proximate the second surface. The second layer includes a bilayer. The encapsulation is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation. The antenna includes a seed layer and a conductive layer. A material of one of the seed layer and the conductive layer of the antenna is the same as a material of one of the bi-layers of the second layer.

In some embodiments, according to another aspect of the present disclosure, a method for manufacturing a semiconductor device package is disclosed. The method comprises the following steps: providing a carrier comprising a first patterned layer proximate a first surface of the carrier; encapsulating the carrier by an encapsulation body; forming a trench in the encapsulation; after forming a conductive layer in the trench and on the carrier and forming the conductive layer in the trench and on the carrier, forming a second patterned layer proximate a second surface of the carrier, the second surface being opposite the first surface.

Drawings

Aspects of the present disclosure are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the different features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1B illustrates a perspective view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1C illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1D illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2B illustrates a perspective view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 3 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5A-5H illustrate intermediate operations of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure.

Fig. 6A-6H illustrate intermediate operations of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure.

Fig. 7 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 8 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 9A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 9B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 10A-10H illustrate intermediate operations of a method of manufacturing a semiconductor device package according to some embodiments of the present disclosure.

Fig. 11A-11I illustrate intermediate operations of methods of manufacturing semiconductor device packages according to some embodiments of the present disclosure.

Fig. 12A-12J illustrate intermediate operations of a method of manufacturing a semiconductor device package, according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, references in the following description to the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various implementations and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

Fig. 1A is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a carrier 10, semiconductor devices 11 and 12, an encapsulation body 13, an antenna 14, and a shield layer 15.

In some embodiments, the carrier 10 has an upper surface 10t and a lower surface 10b opposite the upper surface 10 t. The carrier 10 has a side face 10l between the upper face 10t and the lower face 10 b. The carrier 10 has a layer 102 near the upper surface 10t and a layer 101 near the lower surface 10 b. In some embodiments, layer 102 may be conductive layer 102 and layer 101 may be conductive layer 101. In some embodiments, the carrier 10 may comprise a leadframe or quad flat no-lead (QFN) structure. In some embodiments, the layer 102 proximate the upper surface 10t may include a leadframe or quad flat no-lead (QFN) structure. During the plating operation, the organic carrier counterpart may require additional adhesive or protective layers at its back surface in order to prevent the plating of solder bumps or balls positioned at the back surface during the aforementioned operations. In the event that the adhesive or protective layer is not completely removed from the backside of the organic carrier counterpart, the residual adhesive can be carried to subsequent operations. On the other hand, the application of adhesive to the back side of the QFN structure may be omitted during the plating operation, and thus, the problem of residual adhesive may be effectively avoided. In some embodiments, the material capacity of conductive layer 101 may be different from the material capacity of conductive layer 102. For example, the conductive species in conductive layer 102, such as copper (Cu), may be greater in content than the same conductive species in conductive layer 101. Conductive layers 101 and 102 can be patterned to form two patterned conductive layers. As shown in fig. 1A, conductive layer 101 is in contact with conductive layer 102. The boundary between conductive layer 101 and conductive layer 102 may be identified. In some embodiments, conductive layer 101 may comprise a copper (Cu) alloy or other suitable material. The conductive layer 102 may comprise Cu or other suitable material.

As illustrated in fig. 1A, the carrier 10 may include a recess 104 adjacent to the periphery of the lower surface 10b of the carrier 10. The recess 104 provides space for solder (e.g., SnPb) to bleed out. The carrier 10 may be securely bonded to a Printed Circuit Board (PCB). The recess 104 of the carrier 10 may serve as a wettable side for electronic devices for vehicular applications.

The semiconductor device 11 is disposed on the upper surface 10t of the carrier 10. The semiconductor device 11 may be wire bonded to the carrier 10 by conductive wires 112. The adhesive 111 is disposed between the carrier 10 and the semiconductor device 11. In some embodiments, the semiconductor device 11 may be flip-chip bonded to the carrier 10. The semiconductor device 11 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic components or semiconductor devices.

Similarly, semiconductor device 12 may be wire bonded to carrier 10 by conductive lines 122. The adhesive 121 is disposed between the carrier 10 and the semiconductor device 12. The configuration of the semiconductor device 12 is similar to that of the semiconductor device 11. Semiconductor device 12 may be substantially the same as or different from semiconductor device 11.

The encapsulation 13 is disposed on the upper surface 10t of the carrier 10. The encapsulation body 13 encapsulates the carrier 10. The encapsulation body 13 encapsulates the upper surface 10t of the carrier 10. The encapsulation body 13 encapsulates the semiconductor devices 11 and 12. The encapsulation body 13 has an upper surface 13t and a side surface 13l substantially perpendicular to the upper surface 13 t. The encapsulation 13 has a groove to accommodate the antenna 14. The encapsulation 13 further has additional grooves to accommodate the shielding layer 15. The encapsulation 13 may be exposed through an opening of the carrier 10. The encapsulation 13 may be exposed through the lower surface 10b of the carrier 10.

The antenna 14 is disposed on the upper surface 13t of the capsule 13. The antenna 14 is disposed in a groove of the encapsulation 13. An antenna 14 is embedded in the encapsulation 13. The antenna 14 has an upper surface 14t exposed from the encapsulation 13. The upper surface 14t of the antenna 14 is coplanar with the upper surface 13t of the encapsulation 13. The antenna 14 is at least laterally encapsulated by the encapsulation 13.

The antenna 14 has a seed layer 141 and a conductive layer 142. The seed layer 141 may comprise Ti, TiCu, or other suitable material. The seed layer 141 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 141 may include a material having a high magnetic permeability. Conductive layer 142 may comprise Cu or other suitable material. The conductive layer 142 may be separated or spaced apart from the encapsulation 13 by a seed layer 141. The conductive layer 142 is surrounded by the seed layer 141 from the sidewalls and bottom. In some embodiments, the appearance or shape of the antenna may be varied depending on the desired application.

The shielding layer 15 may be disposed on the upper surface 10t of the carrier 10. The shield layer 15 is disposed in an additional trench of the encapsulation 13. The barrier layer 15 is encapsulated by the encapsulation body 13. The shield layer 15 has an upper surface 15t and a side surface 15s substantially perpendicular to the upper surface 15 t. The upper surface 15t of the shield layer 15 is coplanar with the upper surface 13t of the encapsulation 13 and exposed from the encapsulation 13. The side surface 15s of the shielding layer 15 is coplanar with the side surface 10l of the carrier 10. The shielding layer 15 is in contact with the side face 13l of the capsule 13. The shield layer 15 may surround the antenna pattern of each compartment. As shown in fig. 1A, semiconductor device 11 may be in a left compartment defined by shielding layer 15, while semiconductor device 12 may be in a right compartment defined by shielding layer 15. The shield layer 15 surrounds the encapsulation 13. The shield 15 is separated or spaced apart from the antenna 14 by the encapsulation 13.

The shielding layer 15 includes a seed layer 151 and a conductive layer 152. The seed layer 151 may comprise Ti, TiCu, or other suitable material. The seed layer 151 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 151 may include a material having a high magnetic permeability. Conductive layer 152 can comprise Cu or other suitable material. Conductive layer 152 is separated or spaced apart from encapsulation 13 by seed layer 151.

Fig. 1B is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The shielding layer 15 surrounds the carrier 10. Shield layer 15 surrounds semiconductor devices 11 and 12 (not shown in fig. 1B). The shield layer 15 surrounds the encapsulation 13. The shield 15 surrounds the antenna 14. The shielding layer 15 surrounds the antenna 14 in a manner that prevents electromagnetic interference (EMI) from a wider frequency range, including low frequency EMI. Of course, lower frequency EMI has a longer wavelength than a higher frequency EMI counterpart, and thus a thicker shielding layer may be needed to effectively filter out low frequency EMI. The thickness of the shield layer 15 may be controlled by the manufacturing operations provided in this disclosure. A suitable thickness of the shield layer 15 may be achieved by an electroplating operation, as described in some embodiments in this disclosure. Various sputtering operations may also be applied to form the shield layer 15. In some embodiments, the electroplating operation may have yield and cost benefits for both operations.

A side surface of one terminal of the shield layer 15 may be substantially coplanar with a side surface of one terminal of the encapsulation body 13. A side surface of one terminal of the shielding layer 15 may be substantially coplanar with a side surface of one terminal of the antenna 14.

Fig. 1C is a top view of a semiconductor device package 1' according to some embodiments of the present disclosure. The semiconductor device package 1' is similar to the semiconductor device package 1 in fig. 1B except that the appearance or shape of the antenna 14' is different from the appearance or shape of the antenna 14, and the surface of the antenna 14' is surrounded by the encapsulation 13, for example, to form various sides.

Fig. 1D is a cross-sectional view of a semiconductor device package 1 "according to some embodiments of the present disclosure. The semiconductor device package 1 "is similar to the semiconductor device package 1 in fig. 1C, except that the pattern of the antenna 14" or antenna 14' "is different from the pattern of the antenna 14' and the shielding layers 15' and 15" are embedded in the encapsulation 13, e.g. from the sides. The shield 15' surrounds the antenna 14 ". The shield 15 "surrounds the antenna 14". In some embodiments, the pattern of antenna 14 "is different than the pattern of antenna 14". That is, two different antennas or antenna patterns are implemented in two adjacent compartments or any two compartments of a semiconductor device package. In some embodiments, one compartment with an antenna and another compartment without an antenna may be implemented. More than two compartments may be implemented. The compartments may have different shapes to match the design, such as triangular, curved, trapezoidal or other irregular shapes, and so forth.

In addition to the configuration of the shielding layers 15, 15', 15 ", the shielding layers may completely cover the bottom semiconductor die from a top view perspective. In other words, the shielding layer may cover one of the compartments from a top view perspective. Because the shielding layer may be electrically connected to the carrier 10 through the side edges illustrated in fig. 1A and 1B, the shielding layer may also act as a heat sink or heat sink in case the shielding layer completely covers the corresponding compartment. In some other embodiments, the shield layer may have a fence or mesh configuration from a top view perspective. The fence or mesh configuration may have manufacturing benefits when a grinding or planarization operation is performed to remove excess shield material from the top of the compartment.

Fig. 2A is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 may be similar to the semiconductor device package 1 in fig. 1A, except that the shield layer 25 may be laterally surrounded by the encapsulation 13. In other words, the shielding layer 25 is embedded in the encapsulation body 13. In some embodiments, side 13l of encapsulation 13 may be substantially coplanar with side 10l of carrier 10. The barrier layer 25 may be encapsulated by the encapsulation 13. In some embodiments, the encapsulation 13 may cover the side 10l of the carrier 10 (not shown in fig. 2A). As shown in fig. 2A, the two compartments may then be separated or sawed by a laser sawing operation. When performing a laser sawing operation, the laser may be focused on the encapsulation 13 between adjacent shielding layers 25, and after that operation the shielding layers 25 in the individual singulated packages may be laterally covered by the encapsulation 13. In some other embodiments, roller blades may be implemented to perform the aforementioned separation or sawing operations individually or in combination with laser blades. In some embodiments, the lateral spacing of adjacent shielding layers 25 may be designed to suit the dimensions of the laser blade and/or the roller blade.

The shielding layer 25 includes a seed layer 251 and a conductive layer 252. The seed layer 251 may comprise Ti, TiCu, or other suitable material. The seed layer 251 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 251 may include a material having a high magnetic permeability. Conductive layer 252 may comprise Cu or other suitable material. The conductive layer 252 is separated from the encapsulation 13 by a seed layer 251. The conductive layer 252 is surrounded by a seed layer 251.

Fig. 2B is a perspective view of a semiconductor device package 2 according to some embodiments of the present disclosure. Shield layer 25 surrounds semiconductor devices 11 and 12 (not shown in fig. 2B). The shield 25 surrounds the antenna 14. The encapsulation 13 surrounds the shielding layer 25. The shield layer 25 may surround the antenna pattern of each compartment. As shown in fig. 2A, semiconductor device 11 may be in a left compartment defined by shielding layer 25, while semiconductor device 12 may be in a right compartment defined by shielding layer 25. The barrier layer 25 surrounds the encapsulation 13. The shield 25 is separated or spaced apart from the antenna 14 by the encapsulation 13.

Fig. 3 is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to the semiconductor device package 1 in fig. 1A except that the upper surface 34t of the antenna 34 and the upper surface 35t of the shield layer 35 are lower than the upper surface 13t of the encapsulation body 13. The side surfaces of the shield layer 35 are substantially coplanar with the side surfaces 13l of the capsule 13. This configuration of the antenna 34 and the shielding layer 35 may allow the upper surface 34t of the antenna 34 to be recessed from the upper surface 13t of the encapsulation body 13, and in addition, prevent the upper surface 34t of the antenna 34 from being scratched or the like during a manufacturing operation, an operating operation, or an operation for attaching the semiconductor device package 3 to a PCB.

Antenna 34 has a seed layer 341 and a conductive layer 342. The seed layer 341 may comprise Ti, TiCu, or other suitable material. The seed layer 341 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 341 may include a material having a high magnetic permeability. Conductive layer 342 can comprise Cu or other suitable material. The conductive layer 342 is separated from the encapsulation 13 by the seed layer 341. Conductive layer 342 is surrounded by seed layer 341. In some embodiments, the pattern of the antenna may be varied based on the particular application.

The shielding layer 35 includes a seed layer 351 and a conductive layer 352. The seed layer 351 may comprise Ti, TiCu, or other suitable material. The seed layer 351 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 351 may include a material having a high magnetic permeability. Conductive layer 352 may comprise Cu or other suitable material. The conductive layer 352 may be separated from the encapsulation 13 by a seed layer 351.

Fig. 4 is a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. Semiconductor device package 4 is similar to semiconductor device package 1 in fig. 1A, except that carrier 40 may be a tri-layer structure, antenna 44 may be a tri-layer structure, and shield 45 may be a tri-layer structure.

Carrier 40 has an upper surface 40t and a lower surface 40b opposite upper surface 40 t. Carrier 40 has a side 40l between upper surface 40t and lower surface 40 b. Carrier 40 may have a conductive layer 401 proximate upper surface 40t, a conductive layer 402 proximate lower surface 40b, and a seed layer 403 between conductive layer 401 and conductive layer 402. In some embodiments, the conductive layer 402 and the seed layer 403 form a bilayer in contact with the conductive layer 401. In some embodiments, the conductive layers 401 and 402 and the seed layer 403 form three layers. The materials of the conductive layers 401 and 402 and the seed layer 403 may be different from each other. The conductive layer 401 is in contact with a seed layer 403. The seed layer 403 is in contact with the conductive layer 402. In some embodiments, the conductive layer 401 may comprise a copper (Cu) alloy or other suitable material. The conductive layer 402 may comprise Cu or other suitable material. The seed layer 403 may comprise Ti, TiCu, or other suitable material. The seed layer 403 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 403 may comprise a material having a high magnetic permeability. The carrier 40 may be, for example, a lead frame. Carrier 40 may comprise a quad flat no-lead (QFN) structure. The conductive species in conductive layer 402, such as copper (Cu), may be greater in content than the conductive species in conductive layer 401. For example, conductive layer 401 may be a QFN structure comprising a Cu alloy, and conductive layer 401 may be a Cu layer formed by an electroplating and/or sputtering operation.

Carrier 40 may have a recess 404 adjacent the periphery of lower surface 40b of carrier 40. The recess 404 provides space for solder (e.g., SnPb) to bleed out. Carrier 40 may be securely joined to a Printed Circuit Board (PCB). The groove 404 may serve as a wettable side for the vehicle electronics. In some embodiments, when the solder wets at the groove 404 of the carrier 40 and bonds the carrier 40 to the PCB, the periphery of the solder may be viewed when inspecting the semiconductor device package 4 from a top view perspective.

The antenna 44 is disposed on the upper surface 13t of the capsule 13. The antenna 44 is disposed in a groove of the encapsulation 13. The antenna 44 is embedded in the encapsulation 13. The antenna 44 has an upper surface 44 t. The upper surface 44t of the antenna 44 is coplanar with the upper surface 13t of the encapsulation 13. The antenna 44 is encapsulated by the encapsulation 13. The antenna 44 is exposed from the encapsulation body 13.

The antenna 44 includes a seed layer 441, a conductive layer 442, and a protective layer 443. The seed layer 441 may comprise Ti, TiCu, or other suitable materials. The seed layer 441 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 441 may include a material having a high magnetic permeability. Conductive layer 442 can include Cu or other suitable material. The conductive layer 442 is separated or spaced apart from the encapsulation 13 by a seed layer 441. Conductive layer 442 is surrounded by seed layer 441 from the sides and from the bottom. The protective layer 443 covers the seed layer 441 and the conductive layer 442. The protective layer 443 is close to the upper surface 44t of the antenna 44. The protective layer 443 may be an isolation layer or a conductive layer. The protective layer 443 may prevent the conductive layer 442 from oxidizing or being scratched during subsequent manufacturing or handling processes. In some embodiments, the protective layer 443 can include an insulating material, such as a solder resist layer, a conductive material, such as a surface finish or corrosion resistant material, or other suitable materials. In some embodiments, the protective layer 443 may include Ni, Au, Pd, their respective alloys, or other suitable materials. In some embodiments, the pattern of the antenna may be varied based on the particular application.

The shielding layer 45 is disposed on the upper surface 40t of the carrier 40. The shield layer 45 is disposed in an additional trench of the encapsulation 13. The barrier layer 45 is encapsulated by the encapsulation body 13. The shield layer 45 has an upper surface 45t and a side surface 45s substantially perpendicular to the upper surface 45 t. The upper surface 45t of the shield layer 45 is coplanar with the upper surface 13t of the encapsulation 13. The side surface 45s of the shielding layer 45 is coplanar with the side surface 40l of the carrier 40. The shielding layer 45 is in contact with the side face 13l of the capsule 13. The shield 45 surrounds the antenna 44. The shield layer 45 surrounds the encapsulation 13. The shield 45 is separated from the antenna 44 by the encapsulation 13.

The shielding layer 45 includes a seed layer 451, a conductive layer 452, and a protective layer 453. The seed layer 451 may comprise Ti, TiCu, or other suitable materials. The seed layer 451 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 451 may comprise a material having a high magnetic permeability. The conductive layer 452 may comprise Cu or other suitable material. The conductive layer 452 is separated or spaced apart from the encapsulation 13 by a seed layer 451. The protective layer 453 covers the seed layer 451 and the conductive layer 452. The protective layer 453 is proximate to the upper surface 45t of the shield layer 45. The protective layer 453 may be an isolation layer or a conductive layer. The protective layer 453 can prevent the conductive layer 452 from oxidizing or being scratched during a subsequent manufacturing or operating process. In some embodiments, the protective layer 453 can include an insulating material, such as a solder resist layer, a conductive material, such as a surface finish or corrosion resistant material, or other suitable material. In some embodiments, the protective layer 453 comprises Ni, Au, Pd, their corresponding alloys, or other suitable materials.

In some embodiments, the upper surface 13t of the encapsulation 13 may be higher than the upper surface 44t of the antenna 44 and the upper surface 45t of the shielding layer 45 with suitable manufacturing adjustments.

Fig. 5A-5H illustrate some embodiments of methods of manufacturing semiconductor device packages 1 according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure. The operations of the manufacturing method of the semiconductor device package 1 can be similarly applied to the semiconductor device packages of fig. 1B, 1C, 1D, 3, and 4.

Referring to fig. 5A, a method of manufacturing the semiconductor device package 1 includes providing a carrier 10'. The carrier 10' may be a pre-formed leadframe, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

Referring to fig. 5B, a half-etching operation is performed on the carrier 10' to form a suitable number of recesses to accommodate semiconductor devices, such as the semiconductor devices 11 and 12. Semiconductor devices 11 and 12 may be disposed on the upper surface 10 "t of the etched carrier 10" by adhesives 111 and 121, respectively. By a half-etching operation, the etched support 10 "may include a patterned surface at the upper surface 10" t, either patterned surface or hereinafter referred to as a patterned layer or patterned conductive layer.

Referring to fig. 5C, semiconductor devices 11 and 12 are bonded to etched carrier 10 "by conductive lines 112 and 122, respectively. The encapsulation 13 may be disposed on the upper surface 10 "t of the etched carrier 10". The encapsulation body 13 encapsulates the semiconductor devices 11 and 12. In some other embodiments, semiconductor devices 11 and 12 may be flip-chip bonded to carrier 10 ".

Referring to fig. 5D, trenches 13a and 13b are formed in the encapsulation body 13 by a laser removal operation (e.g., laser ablation) or any other suitable operation. As illustrated in fig. 5D, the groove 13b is formed between the compartment accommodating the semiconductor device 11 and the compartment accommodating the semiconductor device 12. The width of the trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of the trench 13b may be different from the depth of the trench 13 a. The width of the groove 13b may also be different from the width of the groove 13 a. In some embodiments, the depth of the trench 13b allows the upper surface 10 "t of the etched carrier 10" to be exposed from the encapsulation 13 when the trench 13a is positioned proximate to the encapsulation upper surface 13 t. In some embodiments, the depth of the trench 13b is greater than the depth of the trench 13 a. In some embodiments, the trench 13b may be subsequently formed with a shield layer and the trench 13a may be subsequently formed with an antenna structure.

The grooves 13a and 13b are formed by the upper surface of the encapsulation body 13. The trench 13a may protrude above the semiconductor devices 11 and 12. Trench 13b may be positioned between semiconductor device 11 and semiconductor device 12.

Referring to fig. 5E, a seed layer 51 may be formed on the outer surface of the encapsulation body 13. A seed layer 51 may be formed on a portion of the etched carrier 10 "exposed from the encapsulation 13. A seed layer 51 may be formed in the trenches 13a and 13b of the encapsulation body 13. The seed layer 51 may be formed by a sputtering operation. The seed layer 51 may comprise Ti, TiCu, or other suitable material. The seed layer 51 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 51 may comprise a material having a high magnetic permeability. A conductive layer 52 is then formed over the seed layer 51 by a plating operation (e.g., an electroplating or electroless plating operation) or other suitable operation. A conductive layer 52 is formed in the trenches 13a and 13 b. At the same time, the conductive layer 52 may be formed on the backside of the etched carrier 10 "such that the etched carrier 10" together with the newly deposited conductive layer 52 forms the composite carrier 10 "'. The original carrier 10' may comprise a conductive material such as copper; thus, forming the conductive layer 52 on the pristine support 10' of the present disclosure may be more advantageous in terms of plating operations than on organic support counterparts. For example, the conductive layer 52 formed on the etched carrier 10 "may have better thickness uniformity than the conductive layer formed on the organic carrier counterpart. In addition, the yield of forming the conductive layer 52 on the etched carrier 10 ″ may be greater than the yield on the organic carrier counterpart.

The boundary between the etched carrier 10 "and the conductive layer 52 can be observed. Conductive layer 52 comprises Cu or other suitable material. In some embodiments, the seed layer 51 may be formed by a sputtering operation. A sputtered seed layer may be selectively formed on the front side of the etched carrier 10 "and the encapsulation 13. As illustrated in fig. 5E, the carrier 10 "' may have a bilayer structure.

In some other embodiments, the seed layer 51 may be formed by an electroplating operation, an electroless plating operation, or other suitable operation. In such a case, the seed layer 51 will be formed on both the front side (e.g., the side with the semiconductor devices 11, 12 and the encapsulation 13) and the back side of the etched carrier 10 ". Thus, after forming the seed layer and the conductive layer 52, the carrier 10 "' may have a three-layer structure (not shown in fig. 5E), as illustrated in fig. 4.

Referring to fig. 5F, a portion of the seed layer 51 and the conductive layer 52 is removed by a grinding operation to form the antenna 14 and the shielding layer 15. The antenna 14 includes a seed layer 141 and a conductive layer 142. The shielding layer 15 includes a seed layer 151 and a conductive layer 152. After the grinding operation, the antenna 14, the shielding layer 15, and the upper surface of the encapsulation 13 may be substantially coplanar, as illustrated in fig. 5F. The antenna 14 is formed simultaneously with the shield layer 15.

In some embodiments, the upper surfaces of the antenna 14 and the shielding layer 15 may be recessed from the upper surface of the encapsulation 13 after grinding due to a flash etching operation after the grinding operation. Due to the flash etching operation, the grooves of the antenna 14 and the shielding layer 15 may appear as a concave structure. In this case, the upper surface of the etched antenna or etched shield layer may be lower than the upper surface of the encapsulation 13. This configuration of the antenna and shielding layer may be advantageous to avoid scratching during subsequent manufacturing or handling processes.

In some embodiments, a protective layer (not shown in fig. 5F) having a conductive material or an insulating material may be formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 15 by a plating operation, a spraying operation, or other suitable operation. The protective layer may comprise Ni, Au, Pd, alloys thereof, or other suitable materials. A protective layer having a dielectric or insulating material may be formed on the antenna 14 and the shield layer 15 by a spraying operation. The protective layer may comprise a solder resist layer or other suitable material.

Referring to fig. 5G, a half-etching operation is performed on the carrier 10 "', for example, on the rear side of the carrier 10" ', so that the rear side of the carrier 10 "' is patterned. After the back side half-etching operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. The back side half-etching operation of the carrier 10 "' may be performed after the antenna 14 and the shielding layer 15 are formed. The backside topography or pattern of the carrier 10 can be controlled during the backside half-etch operation. The carrier 10 comprises a conductive layer 101 proximate to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite the conductive layer 101. The recess 104 may be formed during a backside etch operation. In some embodiments, the recess 104 is designed to avoid a position under the protrusion of the semiconductor device 11, 12. Following the singulation operation of the semiconductor device package 1, as shown in fig. 5H, the location of the recess 104 may be adjacent to the backside periphery of the singulated semiconductor device package. In some embodiments, a protective layer may be formed on the upper surface of the antenna 14 and on the upper surface of the shielding layer 15 during, before, or after the half-etching operation of fig. 5G.

In some embodiments, after the half-etching operation, a surface finish material (e.g., Sn or NiPdAg) may be plated on the back surface of carrier 10 to protect the bottom side of carrier 10. In other embodiments, the surface finishing material may be formed by ink-jet printing a solder resist over the back surface of the carrier 10. In some embodiments, the surface modifying material may have a low absorption rate for electromagnetic waves.

Referring to fig. 5H, a singulation operation is performed to form the semiconductor device package 1. During the singulation operation, a suitable number of compartments may be separated or sawed by laser operation. When performing a laser sawing operation, the laser may be focused on the shielding layer 15, and after that operation, the shielding layer 25 in the individual singulated packages may be laterally exposed from the encapsulation 13. In some other embodiments, roller blades may be implemented to perform the aforementioned separation or sawing operations individually or in combination with laser blades.

Fig. 6A-6H illustrate some embodiments of methods of manufacturing semiconductor device packages 2, according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure. The operations of the manufacturing method of the semiconductor device package 2 can be similarly applied to the semiconductor device packages of fig. 2A, 3, and 4.

Referring to fig. 6A, a method of manufacturing the semiconductor device package 2 includes providing a carrier 10'. The carrier 10' may be a pre-formed leadframe, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

Referring to fig. 6B, a half-etching operation is performed on the carrier 10' to form a suitable number of recesses to accommodate semiconductor devices, such as the semiconductor devices 11 and 12. Semiconductor devices 11 and 12 may be disposed on the upper surface 10 "t of the etched carrier 10" by adhesives 111 and 121, respectively. By a half-etching operation, the etched support 10 "may include a patterned surface at the upper surface 10" t, either patterned surface or hereinafter referred to as a patterned layer or patterned conductive layer.

Referring to fig. 6C, semiconductor devices 11 and 12 are bonded to etched carrier 10 "by conductive lines 112 and 122, respectively. The encapsulation 13 may be disposed on the upper surface 10 "t of the etched carrier 10". The encapsulation body 13 encapsulates the semiconductor devices 11 and 12. In some other embodiments, semiconductor devices 11 and 12 may be flip-chip bonded to carrier 10 ".

Referring to fig. 6D, trenches 13a and 13b are formed in the encapsulation body 13 by a laser removal operation (e.g., laser ablation) or any other suitable operation. As illustrated in fig. 6D, several trenches 13b may be formed between the compartment accommodating the semiconductor device 11 and the compartment accommodating the semiconductor device 12. The width of the trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of the trench 13b may be different from the depth of the trench 13 a. The width of the groove 13b may also be different from the width of the groove 13 a. The width of the groove 13b may also be different from the width of the groove 13 a. In some embodiments, the depth of the trench 13b allows the upper surface 10 "t of the etched carrier 10" to be exposed from the encapsulation 13 when the trench 13a is positioned proximate to the encapsulation upper surface 13 t. In some embodiments, the depth of the trench 13b is greater than the depth of the trench 13 a. In some embodiments, the trench 13b may be subsequently formed with a shield layer and the trench 13a may be subsequently formed with an antenna structure.

Referring to fig. 6E, a seed layer 51 may be formed on the encapsulation body 13 following the contour of the trenches 13a and 13 b. A seed layer 51 may be formed on a portion of the etched carrier 10 "exposed from the encapsulation 13. A seed layer 51 may be formed in the trenches 13a and 13b of the encapsulation body 13. The seed layer 51 may be formed by a sputtering operation. The seed layer 51 may comprise Ti, TiCu, or other suitable material. The seed layer 51 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 51 may comprise a material having a high magnetic permeability. A conductive layer 52 is then formed on the seed layer 51 by a plating operation or other suitable operation. A conductive layer 52 may be formed in the trenches 13a and 13 b. At the same time, a conductive layer 52 may be formed on the backside of the etched carrier 10 "to form the carrier 10" ', such that the etched carrier 10 "together with the newly deposited conductive layer 52 form the composite carrier 10"'. The raw support 10 'may comprise a conductive material, such as copper, and thus, forming the conductive layer 52 on the raw support 10' of the present disclosure may be more advantageous in terms of a plating operation than on an organic support counterpart. For example, the conductive layer 52 formed on the etched carrier 10 "may have better thickness uniformity than the conductive layer formed on the organic carrier counterpart. In addition, the yield of forming the conductive layer 52 on the etched carrier 10 ″ may be greater than the yield on the organic carrier counterpart.

The boundary between the etched carrier 10 "and the conductive layer 52 can be observed. Conductive layer 52 comprises Cu or other suitable material. In some embodiments, the seed layer 51 may be formed by a sputtering operation, which may be selectively formed on the front side of the etched carrier 10 "and the encapsulation 13. As illustrated in fig. 6E, the carrier 10 "' may have a bilayer structure.

Referring to fig. 6F, a portion of the seed layer 51 and the conductive layer 52 is removed by a grinding operation to form the antenna 14 and the shielding layer 25. The antenna 14 includes a seed layer 141 and a conductive layer 142. The shielding layer 25 includes a seed layer 251 and a conductive layer 252. After the grinding operation, the antenna 14, the shielding layer 25, and the upper surface of the encapsulation 13 may be substantially coplanar, as illustrated in fig. 6F.

In some embodiments, the upper surfaces of the antenna 14 and the shield layer 25 may be recessed from the upper surface of the encapsulation 13 after grinding due to a flash etching operation after the grinding operation. Due to the flash etching operation, the grooves of the antenna 14 and the shielding layer 15 may appear as a concave structure. In this case, the upper surface of the etched antenna or etched shield layer will be lower than the upper surface of the encapsulation 13. This configuration of the antenna and shielding layer may be advantageous to avoid scratching during subsequent manufacturing or handling processes.

In some embodiments, a protective layer (not shown in fig. 6F) of conductive or insulating material may be formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 25 by a plating operation, a spraying operation, or other suitable operation. The protective layer may comprise Ni, Au, Pd, alloys thereof, or other suitable materials. A protective layer having a dielectric or insulating material may be formed on the antenna 14 and the shield layer 15 by a spraying operation. The protective layer may comprise a solder resist layer or other suitable material.

Referring to fig. 6G, a half-etching operation is performed on the carrier 10 "', for example, on the rear side of the carrier 10" ', so that the rear side of the carrier 10 "' is patterned. After the back side half-etching operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. The back side half-etching operation of the carrier 10 "' may be performed after the antenna 14 and the shielding layer 15 are formed. The backside topography or pattern of the carrier 10 can be controlled during the backside half-etch operation. The carrier 10 comprises a conductive layer 101 proximate to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite the conductive layer 101. The recess 104 may be formed during a backside etch operation. In some embodiments, the recess 104 may be designed to avoid a position under the protrusion of the semiconductor apparatus 11, 12. Following the singulation operation of the semiconductor device package 1, as shown in fig. 5H, the location of the recess 104 may be adjacent to the backside periphery of the singulated semiconductor device package. In some embodiments, a protective layer may be formed on the upper surface of the antenna 14 and on the upper surface of the shielding layer 15 during, before, or after the half-etching operation of fig. 6G.

Referring to fig. 6H, a singulation operation is performed to form the semiconductor device package 2. During the singulation operation, a suitable number of compartments may be separated or sawed by laser operation. When performing a laser sawing operation, the laser may be focused on the encapsulation 13 between adjacent shielding layers 25, and after that operation the shielding layers 25 in the individual singulated packages may be laterally encapsulated by the encapsulation 13. In some other embodiments, roller blades may be implemented to perform the aforementioned separation or sawing operations individually or in combination with laser blades.

Fig. 7 is a cross-sectional view of a semiconductor device package 7 according to some embodiments of the present disclosure. The semiconductor device package 7 includes a carrier 10, semiconductor devices 11, 12, and 76, an encapsulation body 13, a patterned conductive layer 74, an interconnection element 75, and an electronic component 77.

The configuration and materials of the carrier 10, the semiconductor devices 11 and 12, and the encapsulation body 13 are similar to those of fig. 1A. The encapsulation 13 has a plurality of trenches to accommodate the patterned conductive layer 74 and the interconnect elements 75. The trench that receives the patterned conductive layer 74 may be shallower than the trench that receives the interconnect element 75.

The patterned conductive layer 74 includes a conductive layer 741, a conductive layer 742, and a seed layer 743. Conductive layer 741 and conductive layer 742 may be traces. In some embodiments, the conductive layer 741 may be a conductive liner. The conductive layer 743 may include Ti, TiCu, or other suitable material. Seed layers 741 and 742 may comprise Cu or other suitable material. The conductive layer 741 is separated from the encapsulation 13 by the seed layer 743. The conductive layer 742 is separated from the encapsulation 13 by a seed layer 743. The conductive layers 741 and 742 are surrounded by the seed layer 743.

The patterned conductive layer 74 is embedded in the trenches of the encapsulant 13. The thickness of the patterned conductive layer 74 may be adjusted. In some embodiments, the upper surface of the patterned conductive layer 74 may be coplanar with the upper surface of the encapsulation 13. The upper surface of the patterned conductive layer 74 may be higher or lower than the upper surface of the encapsulation 13. In some comparative embodiments where only the bottom side of the patterned conductive layer is in contact with the encapsulation 13 (i.e., the patterned conductive layer is patterned on the upper surface of the encapsulation), the embedded patterned conductive layer 74 of embodiments of the invention has better adhesion to the encapsulation 13 by forming contacts at the bottom side and sides. Further, the pitch of the patterned conductive layers 74 (e.g., the distance between the center of one conductive layer 741 and the center of an adjacent conductive layer 741) may be easily controlled so as to match the pitch of the conductive bumps of the semiconductor device 76.

The interconnect element 75 includes a seed layer 751 and a conductive via 752. The seed layer 751 may comprise Ti, TiCu, or other suitable materials. The conductive vias 752 may comprise Cu or other suitable material. An interconnect element 75 electrically connects the patterned conductive layer 74 to the carrier 101. The interconnect element 75 is in contact with the patterned conductive layer 74 and the carrier 101.

The semiconductor device 76 is disposed on the upper surface 13t of the encapsulation body 13. The semiconductor device 76 includes conductive bumps 761. Semiconductor device 76 is electrically connected to patterned conductive layer 74 by conductive bumps 761. The conductive bump 761 is in contact with the conductive layer 741. Semiconductor device 76 may be flip-chip bonded to carrier 10. In some embodiments, semiconductor device 76 may be wire bonded to carrier 10 by conductive wires. Semiconductor device 76 may include a chip. Semiconductor apparatus 76 may comprise a wafer level chip scale package. The semiconductor device 76 is different from the semiconductor device 11 or 12. In some embodiments, semiconductor device 76 is free of any mold encapsulation over it.

The electronic component 77 may be disposed on the upper surface 13t of the encapsulation 13. An electronic component 77 is electrically connected to the patterned conductive layer 74. Electrical component 77 is in contact with conductive layer 742. The electronic component 77 may be in contact with the conductive layers 741 and 742. In some embodiments, electronic component 77 may be a passive component (including, for example, a capacitor, a resistor, or an inductor). The electronic component 77 may be electrically connected to the carrier 10. The electronic component 77 may be electrically connected to the semiconductor device 76. In some embodiments, semiconductor device 76 may receive a signal through electronic component 77 such that the signal will be stable.

Fig. 8 is a cross-sectional view of a semiconductor device package 8 according to some embodiments of the present disclosure. The semiconductor apparatus package 8 is similar to the semiconductor apparatus package 7 in fig. 7, except that the semiconductor apparatus 16 is disposed on the encapsulation body 13 and molded by the encapsulation body 73. The semiconductor device 16 and the electronic component 77 are protected by the encapsulation 73.

The semiconductor device 16 includes a conductive pad 163. The semiconductor device 16 has an active surface facing the encapsulation 13. Semiconductor device 16 is electrically connected to patterned conductive layer 74. The conductive pad 163 is in contact with the conductive layer 741. In some embodiments, semiconductor device 16 is electrically connected to electronic component 77. The semiconductor device 16 is electrically connected to the carrier 10. The semiconductor device 16 is electrically connected to the semiconductor device 11 or 12.

In some embodiments, the semiconductor device 16 may be wire bonded to the carrier 10. Semiconductor device 16 may be substantially the same as or different from semiconductor device 11 or 12. The semiconductor device package 8 may act as a multi-chip die.

Fig. 9A is a cross-sectional view of a semiconductor device package 9 according to some embodiments of the present disclosure. The semiconductor device package 9 is similar to the semiconductor device package 8 in fig. 8, except that the semiconductor device 16' is wire bonded to the carrier 10 and the antenna 94 and the shielding layer 95 is disposed in the trench of the encapsulation 73.

The encapsulation body 73 has an upper surface 73t opposite the upper surface 13t of the encapsulation body 13. The encapsulation 73 has a groove to accommodate the antenna 94. The encapsulation 73 further has additional grooves to accommodate the shielding layer 95.

The configuration and function of the antenna 94 is similar to that of the antenna 14 of fig. 1A. The antenna 94 is disposed on the upper surface 73t of the capsule 73. An antenna 94 is embedded in the encapsulation 73. The antenna 94 is encapsulated at least laterally by the encapsulation 73. The antenna 94 includes a seed layer 941 and a conductive layer 942. The seed layer 941 may include Ti, TiCu, or other suitable material. The seed layer 941 may include a magnetic material such as Ni, Fe, or stainless steel. The seed layer 941 may include a material having a high magnetic permeability. The conductive layer 942 may comprise Cu or other suitable material. The conductive layer 942 may be separated or spaced apart from the encapsulation 73 by a seed layer 941. Conductive layer 942 is surrounded from the sidewalls and bottom by seed layer 941.

The configuration and function of the shielding layer 95 is similar to that of the shielding layer 15 of fig. 1A. The shield layer 95 may be disposed on the patterned conductive layer 74. The shield layer 95 may be disposed in additional trenches of the encapsulation 73. The barrier layer 95 is encapsulated by the encapsulation body 73. The shield 95 may surround the antenna 94 and the semiconductor device 16'. The shield 95 is separated or spaced apart from the antenna 94 by the encapsulation 73.

Shield layer 95 includes seed layer 951 and conductive layer 952. Seed layer 951 may comprise Ti, TiCu, or other suitable material. The seed layer 951 may comprise a magnetic material, such as Ni, Fe, or stainless steel. Seed layer 951 may comprise a material having a high magnetic permeability. Conductive layer 952 may comprise Cu or other suitable material. Conductive layer 952 is separated or spaced apart from encapsulation 73 by seed layer 951.

The semiconductor device package 9 may also include similar advantages of the semiconductor device packages 1, 2, 3, and 4 of fig. 1A, 2A, 3, and 4.

Fig. 9B is a cross-sectional view of a semiconductor device package 9' according to some embodiments of the present disclosure. The semiconductor device package 9 'is similar to the semiconductor device package 9 in fig. 9A, except that a portion of the patterned conductive layer 74 (e.g., the portion surrounded by the dashed line) may act as an antenna, and the active surface of the semiconductor device 16 in the encapsulation 73 facing or in contact with the patterned conductive layer 74 and the shield layer 95' may pass through the encapsulation 73 and the encapsulation 13.

The configuration of the antenna, which may be part of the patterned conductive layer 74, may be substantially the same as the antenna 14 or 94 as previously described. An antenna is disposed on the encapsulation 13 and is configured to interact with either of the semiconductor devices 11 and 12. In some embodiments, the antenna may be disposed between conductive layers 741 and 742 of the patterned conductive layer 74. In some embodiments, the antenna can be adjacent to the conductive layer 742. The antenna may be adjacent to the conductive layer 741.

Shield layer 95' includes seed layer 951' and conductive layer 952 '. The shielding layer 95' extends from the upper surface 10t of the carrier 10 to the upper surface 73t of the encapsulation 73. In some embodiments, the shield layer 95 and the interconnect element 75 together act as a shield layer. The shield layer 95' may be disposed on the periphery of the carrier 10. The shield layer 95' may be disposed on the center of the carrier 10. The shield layer 95' may be disposed to surround any of the semiconductor apparatuses 11, 12, 16.

Fig. 10A-10H illustrate some embodiments of methods of manufacturing semiconductor device packages 7, according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure. The operation of the manufacture of the semiconductor device package 7 may be similar to that of the manufacture of the semiconductor device package 1 of fig. 5A to 5H.

Referring to fig. 10A, a method of manufacturing the semiconductor device package 7 includes providing a carrier 10'. The carrier 10' may be a pre-formed leadframe, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

Referring to fig. 10B, a half-etching operation is performed on the carrier 10' to form a suitable number of recesses to accommodate semiconductor devices, such as the semiconductor devices 11 and 12. By a half-etching operation, the etched support 10 "may include a patterned surface at the upper surface 10" t, either patterned surface or hereinafter referred to as a patterned layer or patterned conductive layer.

Referring to fig. 10C, semiconductor devices 11 and 12 are disposed on the upper surface 10 "t of the etched carrier 10" by adhesives 111 and 121, respectively. Semiconductor devices 11 and 12 are bonded to etched carrier 10 "by conductive lines 112 and 122, respectively. The encapsulation 13 is disposed on the upper surface 10 "t of the etched carrier 10". The encapsulation body 13 encapsulates the semiconductor devices 11 and 12.

Referring to fig. 10D, trenches 13a and 13b are formed in the encapsulation body 13 by a laser removal operation (e.g., laser ablation) or any other suitable operation. As illustrated in fig. 10D, the trench 13b is formed between the compartment accommodating the semiconductor device 11 and the compartment accommodating the semiconductor device 12. The width of the trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of the trench 13b may be different from the depth of the trench 13 a. The width of the groove 13b may also be different from the width of the groove 13 a. The width of the groove 13b may also be different from the width of the groove 13 a. In some embodiments, the depth of the trench 13b allows the upper surface 10 "t of the etched carrier 10" to be exposed from the encapsulation 13 when the trench 13a is positioned proximate to the encapsulation upper surface 13 t. In some embodiments, the depth of the trench 13b is greater than the depth of the trench 13 a. In some embodiments, the trench 13b may be subsequently formed with a shield layer and the trench 13a may be subsequently formed with an antenna structure.

Referring to fig. 10E, a seed layer 51 may be formed on the outer surface of the encapsulation body 13. A seed layer 51 may be formed on a portion of the etched carrier 10 "exposed from the encapsulation 13. A seed layer 51 may be formed in the trenches 13a and 13b of the encapsulation body 13. The seed layer 51 may be formed by a sputtering operation. The seed layer 51 may comprise Ti, TiCu, or other suitable material. The seed layer 51 may include a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 51 may comprise a material having a high magnetic permeability. A conductive layer 52 is then formed on the seed layer 51 by a plating operation or other suitable operation. A conductive layer 52 may be formed in the trenches 13a and 13 b. At the same time, a conductive layer 52 may be formed on the backside of the etched carrier 10 "to form the carrier 10" ', such that the etched carrier 10 "together with the newly deposited conductive layer 52 form the composite carrier 10"'. The original carrier 10' may comprise a conductive material such as copper; thus, forming the conductive layer 52 on the pristine support 10' of the present disclosure may be more advantageous in terms of plating operations than on organic support counterparts. For example, the conductive layer 52 formed on the etched carrier 10 "may have better thickness uniformity than the conductive layer formed on the organic carrier counterpart. In addition, the yield of forming the conductive layer 52 on the etched carrier 10 ″ may be greater than the yield on the organic carrier counterpart.

The boundary between the etched carrier 10 "and the conductive layer 52 can be observed. Conductive layer 52 comprises Cu or other suitable material. In some embodiments, the seed layer 51 may be formed by a sputtering operation. A sputtered seed layer may be selectively formed on the front side of the etched carrier 10 "and the encapsulation 13. As illustrated in fig. 10E, the carrier 10 "' may have a double-layer structure.

Referring to fig. 10F, a portion of seed layer 51 and conductive layer 52 are removed by a grinding operation to form patterned conductive layer 74. The patterned conductive layer 74 includes conductive layers 741 and 742 and a seed layer 743. The conductive layer 741 may be a conductive pad. Conductive layer 742 may be a conductive trace. After the grinding operation, the upper surface of the patterned conductive layer 74 and the upper surface of the encapsulation 13 may be substantially coplanar.

The interconnect element 75 includes a seed layer 751 and a conductive via 752. The seed layer 751 may comprise Ti, TiCu, or other suitable materials. The conductive vias 752 may comprise Cu or other suitable material. The patterned conductive layer 74 is electrically connected to the etched carrier 10 "by interconnect elements 75. The interconnect element 75 is formed simultaneously with the patterned conductive layer 74. The interconnect element 75 is formed in one piece with the patterned conductive layer 74.

In some embodiments, the upper surface of the patterned conductive layer 74 may be recessed from the upper surface of the encapsulation 13 after grinding due to a flash etching operation after the grinding operation. The grooves of the patterned conductive layer 74 may appear as recessed structures due to the flash etching operation. In this case, the upper surface of the patterned conductive layer 74 may be lower than the upper surface of the encapsulation 13.

In some embodiments, a protective layer (not shown in fig. 10F) of conductive or insulating material may be formed on the upper surface of the patterned conductive layer 74 by an electroplating operation, a spraying operation, or other suitable operation. The protective layer may comprise Ni, Au, Pd, alloys thereof, or other suitable materials.

Referring to fig. 10G, a half-etching operation is performed on the carrier 10' ″, for example, on the rear side of the carrier 10' ″ so that the rear side of the carrier 10' ″ is patterned. After the back side half-etching operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. A backside half-etch operation of carrier 10 "' may be performed after forming patterned conductive layer 74. The backside topography or pattern of the carrier 10 can be controlled during the backside half-etch operation. The carrier 10 comprises a conductive layer 101 proximate to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite the conductive layer 101. The recess 104 may be formed during a backside half-etching operation to expose the encapsulation 13 from the carrier 10' ″. In some embodiments, the recess 104 may be designed to avoid a position under the protrusion of the semiconductor apparatus 11, 12. Following the singulation operation of the semiconductor device package 7, as shown in fig. 10G, the location of the recess 104 may be adjacent to the backside periphery of the singulated semiconductor device package.

Referring to fig. 10H, a semiconductor device 76 is disposed on the upper surface 13t of the encapsulation body 13. The semiconductor device 76 is electrically connected to the patterned conductive layer 74 through a conductive pad 761. The conductive pad 761 can be in contact with the conductive layer 741 and/or the conductive layer 742. An electronic component 77 is disposed on an upper surface of the encapsulation 13. An electronic component 77 is electrically connected to the patterned conductive layer 74. The electronic component 77 may be in contact with the conductive layer 741 or the conductive layer 742. The electronic component 77 may be in contact with the conductive layers 741 and 742. In some embodiments, semiconductor device 76 may include a chip. Semiconductor apparatus 76 may comprise a wafer level chip scale package. The electronic components 77 may be passive components (including, for example, capacitors, resistors, or inductors). A singulation operation is performed to form the semiconductor device package 7.

Fig. 11A through 11I illustrate some embodiments of methods of manufacturing semiconductor device packages 8, according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure.

The operation of the fabrication of the semiconductor device package 8 of fig. 11A to 11F may be similar to the operation of the fabrication of the semiconductor device package 7 of fig. 10A to 10F.

Referring to fig. 11G, the attaching operation of the semiconductor device 16 and the electrical component 77 of fig. 11G is similar to that of fig. 10H except that the semiconductor device 16 is different from the semiconductor device 76.

Referring to fig. 11H, an encapsulation body 73 is disposed on the upper surface of the encapsulation body 13. The encapsulation body 73 encapsulates the semiconductor device 16 and the electrical components 77.

Referring to fig. 11I, the etching operation of fig. 11I is similar to the etching operation of fig. 10G. For example, a half-etching operation is performed on the carrier 10 "' on the rear side of the carrier 10" ' such that the rear side of the carrier 10 "' is patterned. After the back side half-etching operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. A singulation operation is performed to form the semiconductor device package 8.

Fig. 12A-12J illustrate some embodiments of methods of manufacturing semiconductor device packages 9 according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure.

The operation of the fabrication of the semiconductor device package 9 of fig. 12A to 12F may be similar to the operation of the fabrication of the semiconductor device package 7 of fig. 10A to 10F.

Referring to fig. 12G, the attaching operation of the semiconductor device 16 'is similar to that of the semiconductor device 11 or 12 except that the semiconductor device 16' is disposed on the encapsulation body 13. The semiconductor device 16' is wire bonded to the patterned conductive layer 74 by conductive lines 162. Conductive line 162 can be electrically connected to conductive layer 741 or conductive layer 742. The adhesive 161 is disposed between the encapsulation 13 and the semiconductor device 16'.

Referring to fig. 12H, an encapsulation body 73 is disposed on the upper surface of the encapsulation body 13. The encapsulation body 73 encapsulates the semiconductor device 16'.

Referring to fig. 12I, the array of the antenna 94 and the shielding layer 95 is similar to the array of the antenna 14 and the shielding layer 15 of fig. 5D to 5F. The configuration, function, and materials of the antenna 94 are similar to those of the antenna 14 of fig. 1A. The antenna 94 includes a seed layer 941 and a conductive layer 942. The configuration, function, and material of the shielding layer 95 are similar to those of the shielding layer 15 of fig. 1A. Shield layer 95 includes seed layer 951 and conductive layer 952.

Referring to fig. 12J, the etching operation of fig. 12J is similar to the etching operation of fig. 10G. For example, a half-etching operation is performed on the carrier 10 "' on the rear side of the carrier 10" ' such that the rear side of the carrier 10 "' is patterned. After the back side half-etching operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. A singulation operation is performed to form the semiconductor device package 9. In some embodiments, the half-etch operation illustrated in fig. 12J is performed after the antenna 94 and the shielding layer 95 are formed. In some comparative embodiments in which the half-etch operation illustrated in fig. 12J is performed prior to forming the antenna 94 and the shielding layer 95, the exposed encapsulant 73 at the back side of the carrier 10 "' may be further deposited with a conductive material during antenna and shielding layer formation and cause undesirable shorting in the semiconductor package structure.

As used herein, spatial descriptions are specified with respect to orientation of a component as shown in the associated figures, such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above …," "above …," and the like, with respect to a component or group of components, or a plane of a component or group of components. It is to be understood that the spatial descriptions used herein are for illustrative purposes only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the embodiments of the present disclosure are not offset by such arrangements.

As used herein, and not otherwise defined, the terms "substantially," "approximately," and "about" are used to describe and contemplate minor variations. When used in conjunction with an event or circumstance, the terms can encompass the occurrence of the event or circumstance specifically and the close approximation of the event or circumstance. For example, when used in conjunction with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may mean that the two surfaces lie along the same plane within a few microns, for example within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not to be construed in a limiting sense. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between the technology renditions in this disclosure and the actual devices. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.

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