阅读说明：本技术 半导体装置及制造半导体装置的方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 金泰基 新及補 孙山南 杜旺朱 于 2020-04-16 设计创作，主要内容包括：在一个实例中,一种半导体装置包括：重新分布层(RDL)衬底,所述RDL衬底具有顶表面和底表面,其中所述RDL衬底包括不含填料的介电材料；电子装置,所述电子装置位于所述RDL衬底的所述顶表面上；电互连件,所述电互连件位于所述RDL衬底的所述底表面上并且电耦接到所述电子装置；第一保护材料,所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；以及第二保护材料,所述第二保护材料接触所述电互连件的侧表面和所述RDL衬底的所述底表面。本文还公开了其它实例和相关方法。(In one example, a semiconductor device includes: a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material; an electronic device located on the top surface of the RDL substrate; an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device; a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate; and a second protective material contacting side surfaces of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.)

1. A semiconductor device, comprising:

a redistribution layer substrate having a top surface and a bottom surface, wherein the redistribution layer substrate comprises a filler-free dielectric material;

an electronic device located on the top surface of the redistribution layer substrate;

an electrical interconnect on the bottom surface of the redistribution layer substrate and electrically coupled to the electronic device;

a first protective material contacting a side surface of the electronic device and the top surface of the redistribution layer substrate; and

a second protective material contacting side surfaces of the electrical interconnect and the bottom surface of the redistribution layer substrate.

2. The semiconductor device of claim 1, wherein the electrical interconnect comprises a conductive post on the bottom surface of the redistribution layer substrate, a conductive post on the conductive post, and an interconnect tip on the conductive post.

3. The semiconductor device of claim 2, wherein the electrical interconnect further comprises a seed layer between the conductive posts and the conductive posts.

4. The semiconductor device of claim 1, wherein the electrical interconnect comprises under bump metal on the bottom surface of the redistribution layer substrate.

5. The semiconductor device of claim 1, wherein the electrical interconnect comprises a conductive post on the bottom surface of the redistribution layer substrate and a solder ball on the conductive post.

6. The semiconductor device of claim 1, wherein the redistribution layer substrate comprises a conductive layer and a dielectric layer.

7. The semiconductor device of claim 6, further comprising additional electrical interconnects located on the top surface of the redistribution layer substrate for coupling the electronic device to the electrical interconnects on the bottom surface of the redistribution layer substrate through the conductive layer.

8. The semiconductor device of claim 1, wherein the first protective material and the second protective material comprise the same material having the same coefficient of thermal expansion.

9. The semiconductor device of claim 1, wherein the first protective material and the second protective material comprise different materials having the same or similar coefficients of thermal expansion.

10. The semiconductor device of claim 1, wherein the first protective material has a first coefficient of thermal expansion and a first thickness and the second protective material has a second coefficient of thermal expansion and a second thickness such that warpage between the first protective material and the redistribution layer substrate counteracts warpage between the second protective material and the redistribution layer substrate.

11. A method for manufacturing a semiconductor device, the method comprising:

forming a base structure having conductive posts;

forming a redistribution layer substrate on the base structure;

placing an electronic device on a top surface of the redistribution layer substrate; and

forming a protective material contacting side surfaces of the electronic device and the top surface of the redistribution layer substrate.

12. The method of claim 11, wherein the conductive posts are formed using a plating operation and the base structure is formed using a molding operation after the plating operation.

13. The method of claim 11, wherein the redistribution layer substrate comprises a filler-free dielectric material and the conductive posts are formed using a plating operation, and the method further comprises forming conductive posts on the conductive posts using a second plating operation and forming interconnect tips on the conductive posts using a third plating operation.

14. The method of claim 11, wherein forming the redistribution layer substrate comprises:

forming a first dielectric layer on the base structure;

forming an opening in the dielectric layer to expose the conductive post; and

forming a conductive layer on the dielectric layer and the conductive posts.

15. The method of claim 11, wherein the base structure is formed on a first carrier using a first molding operation and the protective material is formed using a second molding operation, and further comprising:

attaching a second carrier to the protective material;

removing the first carrier; and

detaching the second carrier after said removing the first carrier.

16. A method for manufacturing a semiconductor device, the method comprising:

forming a redistribution layer substrate on a first carrier, the redistribution layer substrate having a top surface and a bottom surface;

placing an electronic device on the top surface of the redistribution layer substrate;

forming a first protective material using a first molding operation, wherein the first protective material contacts side surfaces of the electronic device and the top surface of the redistribution layer substrate;

attaching a second carrier to the first protective material;

removing the first carrier from the redistribution layer substrate;

forming conductive posts on the bottom surface of the redistribution layer substrate using a first plating operation; and

forming a second protective material using a second molding operation, wherein the second protective material contacts side surfaces of the conductive posts and the bottom surface of the redistribution layer substrate.

17. The method of claim 16, further comprising forming conductive pillars on the conductive posts using a second plating operation and forming interconnect tips on the conductive posts using a third plating operation.

18. The method of claim 16, further comprising forming a solder ball on the conductive post.

19. The method of claim 17, further comprising removing the second carrier after the third plating operation.

20. The method of claim 16, wherein the first carrier is removed using a grinding or etching operation.

Technical Field

The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for manufacturing semiconductor devices.

Background

Existing semiconductor packages and methods for forming semiconductor packages suffer from disadvantages such as excessive cost, reduced reliability, relatively low performance, or large package size. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure and reference to the drawings.

Disclosure of Invention

Various aspects of the present disclosure provide a semiconductor device, comprising: a redistribution layer substrate having a top surface and a bottom surface, wherein the redistribution layer substrate comprises a filler-free dielectric material; an electronic device located on the top surface of the redistribution layer substrate; an electrical interconnect on the bottom surface of the redistribution layer substrate and electrically coupled to the electronic device; a first protective material contacting a side surface of the electronic device and the top surface of the redistribution layer substrate; and a second protective material contacting side surfaces of the electrical interconnect and the bottom surface of the redistribution layer substrate. In the semiconductor device, the electrical interconnect includes a conductive post on the bottom surface of the redistribution layer substrate, a conductive post on the conductive post, and an interconnect tip on the conductive post. In the semiconductor device, the electrical interconnect further comprises a seed layer between the conductive posts and the conductive pillars. In the semiconductor device, the electrical interconnect comprises under bump metal on the bottom surface of the redistribution layer substrate. In the semiconductor device, the electrical interconnect includes a conductive post on the bottom surface of the redistribution layer substrate and a solder ball on the conductive post. In the semiconductor device, the redistribution layer substrate includes a conductive layer and a dielectric layer. The semiconductor device further includes additional electrical interconnects on the top surface of the redistribution layer substrate for coupling the electronic device to the electrical interconnects on the bottom surface of the redistribution layer substrate through the conductive layer. In the semiconductor device, the first protective material and the second protective material include the same material having the same thermal expansion coefficient. In the semiconductor device, the first protective material and the second protective material include different materials having the same or similar thermal expansion coefficients. In the semiconductor device, the first protective material has a first coefficient of thermal expansion and a first thickness, and the second protective material has a second coefficient of thermal expansion and a second thickness, such that warpage between the first protective material and the redistribution layer substrate counteracts warpage between the second protective material and the redistribution layer substrate.

Various aspects of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a base structure having conductive posts; forming a redistribution layer substrate on the base structure; placing an electronic device on a top surface of the redistribution layer substrate; and forming a protective material contacting a side surface of the electronic device and the top surface of the redistribution layer substrate. In the method, the conductive posts are formed using a plating operation, and the base structure is formed using a molding operation after the plating operation. In the method, the redistribution layer substrate includes a filler-free dielectric material and the conductive posts are formed using a plating operation, and the method further includes forming conductive posts on the conductive posts using a second plating operation and forming interconnect tips on the conductive posts using a third plating operation. In the method, forming the redistribution layer substrate comprises: forming a first dielectric layer on the base structure; forming an opening in the dielectric layer to expose the conductive post; and forming a conductive layer on the dielectric layer and the conductive posts. In the method, the base structure is formed on a first carrier using a first molding operation and the protective material is formed using a second molding operation, and the method further comprises: attaching a second carrier to the protective material; removing the first carrier; and detaching the second carrier after the removing of the first carrier.

Various aspects of the present disclosure provide a method for fabricating a semiconductor device, the method including forming a redistribution layer substrate on a first carrier, the redistribution layer substrate having a top surface and a bottom surface; placing an electronic device on the top surface of the redistribution layer substrate; forming a first protective material using a first molding operation, wherein the first protective material contacts side surfaces of the electronic device and the top surface of the redistribution layer substrate; attaching a second carrier to the first protective material; removing the first carrier from the redistribution layer substrate; forming conductive posts on the bottom surface of the redistribution layer substrate using a first plating operation; and forming a second protective material using a second molding operation, wherein the second protective material contacts side surfaces of the conductive posts and the bottom surface of the redistribution layer substrate. The method further includes forming conductive pillars on the conductive posts using a second plating operation and forming interconnect tips on the conductive posts using a third plating operation. The method further includes forming a solder ball on the conductive post. The method further includes removing the second carrier after the third plating operation. In the method, the first carrier is removed using a grinding or etching operation.

Drawings

Fig. 1 shows a cross-sectional view of an example semiconductor device.

Fig. 2A to 2L show cross-sectional views of an example method for manufacturing an example semiconductor device.

Fig. 3 illustrates a cross-sectional view of another example semiconductor device.

Fig. 4A to 4K show cross-sectional views of an example method for manufacturing another example semiconductor device.

Detailed Description

The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "such as" are non-limiting.

The drawings show a general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the disclosure. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of examples discussed in this disclosure. Like reference symbols in the various drawings indicate like elements.

The terms "or" and/or "include any single item or any combination of items in the list connected by" or "and/or". As used in this disclosure, the singular is intended to include the plural as well, unless the context clearly indicates otherwise.

The terms "comprising", "including", "containing" and/or "including" are open-ended terms and specify the presence of the stated features, but do not preclude the presence or addition of one or more other features.

The terms "first," "second," and the like may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in this disclosure could be termed a second element without departing from the teachings of the disclosure.

Unless otherwise specified, the term "coupled" may be used to describe two elements as being in direct contact with each other or to describe two elements as being indirectly connected through one or more other elements. For example, if element a is coupled to element B, element a may directly contact element B or be indirectly connected to element B through an intermediate element C. Similarly, the terms "on" or "upper" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

In one example, a semiconductor device includes: a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material; an electronic device located on the top surface of the RDL substrate; an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device; a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate; and a second protective material contacting side surfaces of the electrical interconnect and the bottom surface of the RDL substrate.

In another example, a method for manufacturing a semiconductor device includes: forming a base structure having conductive posts; forming a redistribution layer (RDL) substrate on the base structure; placing an electronic device on a top surface of the RDL substrate; and forming a protective material contacting a side surface of the electronic device and the top surface of the RDL substrate.

In another example, a method for manufacturing a semiconductor device includes: forming a redistribution layer (RDL) substrate on a first carrier, the RDL substrate having a top surface and a bottom surface; placing an electronic device on the top surface of the RDL substrate; forming a first protective material using a first molding operation, wherein the first protective material contacts a side surface of the electronic device and the top surface of the RDL substrate; attaching a second carrier to the first protective material; removing the first carrier from the RDL substrate; forming conductive posts on the bottom surface of the RDL substrate using a first plating operation; and forming a second protective material using a second molding operation, wherein the second protective material contacts side surfaces of the conductive posts and the bottom surface of the RDL substrate.

Other examples are included in the present disclosure. Such examples may be present in the drawings, claims, and/or specification of the present disclosure.

Fig. 1 shows a cross-sectional view of an example semiconductor device. In the example shown in fig. 1, the semiconductor device 100 may include a base structure 110, a substrate 120, an electronic device 130, an encapsulant 140, and an interconnection 150. In addition, the semiconductor device 100 may further include a dielectric layer 160 between the substrate 120 and the electronic device 130. In some examples, electronic device 130 may include active devices such as semiconductor dies or transistors, and in other examples, electronic device 130 may include passive devices such as resistors, capacitors, inductors, connectors, or equivalents.

The base structure 110 may include a conductive layer 112 and a dielectric layer 113. The substrate 120 may include dielectric layers 121a, 122a, 123a, and 124a and conductive layers 121b, 122b, 123b, 124b, 121c, 122c, 123c, 124c, and 124 d. The electronic device 130 may include interconnects 131 and 132. The encapsulant 140 may contact the top surface of the substrate 120 and the side surfaces of the electronic device 130. In addition, the interconnection 150 may include conductive layers 151, 152, and 153 and may be located on a bottom surface of the base structure 110.

The base structure 110, the substrate 120, the encapsulant 140, and the interconnects 150 may be referred to as a semiconductor package 190 or a package 190. In addition, the semiconductor package 190 may protect the electronic device 130 from external elements and/or environmental exposure. In addition, the semiconductor package 190 may provide electrical coupling between an external device (not shown) and the electronic device 130.

Fig. 2A to 2L show cross-sectional views of an example method for manufacturing an example semiconductor device. Fig. 2A illustrates a process of providing a carrier 171 at an early manufacturing stage.

In the example shown in fig. 2A, carrier 171 is substantially planar. In some examples, carrier 171 may also be referred to as a plate, wafer, panel, or tape. Additionally, in some examples, the carrier 171 may be made of any one or more of a metal (e.g., SUS), a wafer (e.g., silicon), a ceramic (e.g., alumina), a glass (e.g., soda-lime glass), or any equivalent. The thickness of carrier 171 may be in the range of about 500 μm to about 1500 μm and the width may be in the range of about 100mm to about 500 mm. During the processes of forming base structure 110, forming substrate 120, and attaching and encapsulating electronic device 130, carrier 171 may function to process multiple components in an integrated manner. In some examples, the carrier 171 may be universally applicable to all examples of the present disclosure.

Fig. 2B shows the process of forming conductive layers 111 and 112 at a later stage of fabrication. In the example shown in fig. 2B, a conductive layer 111 may be formed on a carrier 171. In some examples, the conductive layer 111 may be referred to as a seed layer or a base layer. In some examples, the seed layer 111 may be made of any of a variety of conductive materials (e.g., titanium, tungsten, titanium/tungsten, copper, gold, silver, palladium, nickel, or equivalents thereof). In addition, in some examples, the seed layer 111 may be formed using any of a variety of processes, such as sputtering, electroless plating (electroplating), electroplating, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or equivalents thereof. The seed layer 111 may be about 500 angstroms thickTo aboutWithin the range of (1). The seed layer 111 may facilitate the formation of the conductive layer 112 to a predetermined thickness at a later manufacturing stage.

In addition, in the example shown in fig. 2B, a relatively thick conductive layer 112 may be formed on the relatively thin seed layer 111. In some examples, a patterned mask (not shown) may be used to form a pattern on the seed layer 111, and the relatively thick conductive layer 112 may be formed only within the pattern. In some examples, conductive layer 112 may be referred to as a conductive stud or an under bump metallization. In some examples, the conductive studs 112 may be made of any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents thereof). The conductive posts 112 may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). After the conductive posts 112 are formed, the patterned mask may be removed. In addition, the relatively thin seed layer 111 formed around the relatively thick conductive pillars 112 may also be removed using, for example, a soft etch process. The thickness of the conductive posts 112 may be in the range of about 1 μm to about 10 μm. The conductive posts 112 can function to stack the substrate 120 on the conductive posts 112 and form the interconnects 150 under the conductive posts 112 at a later stage of fabrication.

Fig. 2C shows the process of forming the dielectric layer 113 at a later stage of fabrication. In the example shown in fig. 2C, the conductive posts 111 and 112 formed on the carrier 171 may be covered by a dielectric layer 113. In some examples, dielectric layer 113 may be formed using a molding operation, and dielectric layer 113 may contact the sides of conductive posts 112. In some examples, the dielectric layer 113 may cover the top and side surfaces of the conductive post 112, and the dielectric layer 113 may not cover the bottom surface of the conductive post 112. In some examples, the dielectric layer 113 may not cover the top surface of the conductive post 112 to allow the top surface of the conductive post 112 to be exposed to the outside through the dielectric layer 113. In some examples, the dielectric layer 113 may be referred to as an encapsulant, a sealant, an epoxy mold compound, a protective material, or an epoxy mold resin. In addition, in some examples, the encapsulant 113 may also be referred to as an encapsulation part, a molding part, a protection part, or a body. In some examples, encapsulant 113 may include, but is not limited to, organic resins, inorganic fillers, curing agents, catalysts, colorants, flame retardants, or equivalents of the foregoing. The encapsulant 113 may be formed by any of a variety of processes including a molding operation. In some examples, the encapsulant 113 may be formed by, but is not limited to, compression molding, transfer molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The thickness of the encapsulant 113 may be in the range of about 50 μm to about 100 μm. Encapsulant 113 may encapsulate conductive posts 111 and 112 to reduce or prevent substrate 120 from warping at a later stage.

Fig. 2D illustrates a process for removing portions of conductive posts 112 and encapsulant 113 at a later stage of fabrication. In the example shown in fig. 2D, the top surfaces of the conductive posts 112 and encapsulant 113 are removed, such as by grinding or etching, so that the top surfaces of the conductive posts 112 and encapsulant 113 are coplanar. In some examples, the top surfaces of the conductive posts 112 and encapsulant 113 may be coplanar by grinding and/or etching to improve planarity of the substrate 120 formed over the conductive posts 112 and encapsulant 113. In this manner, the base structure 110 may be completed, the substrate 120 may be formed on the base structure 110 later, and the interconnection 150 may be formed under the base structure 110.

Fig. 2E illustrates a process of forming the substrate 120 at a later stage of fabrication. In the example shown in fig. 2E, a substantially planar substrate 120 may be formed or deposited directly on the base structure 110. In one example, the dielectric layers 121a, 122a, 123a, and 124a and the conductive layers 121b, 122b, 123b, 124b, 121c, 122c, 123c, 124c, and 124d may be stacked multiple times on the base structure 110 to complete the substrate 120.

In some examples, the dielectric layer 121a may cover the top surface of the base structure 110. Since the top surface of the base structure 110 may be planar, the dielectric layer 121a may also be planar. In some examples, the dielectric layer 121a may be referred to as a passivation layer, an insulating layer, or a protective layer. The dielectric layer 121a may be made of various non-conductive materials (e.g., Si)₃N₄SiO2, SiON, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), Bismaleimide Triazine (BT), epoxy, phenolic, silicone, acrylate polymer, or equivalents thereof). In addition, the dielectric layer 121a may be formed using any of various processes (e.g., PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering, thermal oxidation, or equivalents thereof)And (5) forming. In some examples, the dielectric layer 121a may be patterned to form an opening that exposes the conductive post 112 while covering the encapsulant 113. The thickness of the dielectric layer 121a may be in the range of about 1 μm to about 10 μm, and the width of the opening may be in the range of about 5 μm to about 70 μm.

In some examples, the conductive layer 121b may be conformally formed on the dielectric layer 121a and the exposed conductive posts 112. In some examples, the conductive layer 121b may be referred to as a seed layer or a base layer. In some examples, the seed layer 121b may be formed on the top surface of the dielectric layer 121a, the sidewalls of the opening, and the top surface of the conductive stud 112.

In some examples, the seed layer 121b may be made of any of a variety of conductive materials (e.g., titanium, tungsten, titanium/tungsten, copper, gold, silver, palladium, nickel, or equivalents thereof). Additionally, in some examples, the seed layer 121b may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The thickness of the seed layer 121b may be aboutTo about

Within the range of (1). The seed layer 121b may facilitate the formation of the conductive layer 121c to a predetermined thickness at a later manufacturing stage.

Although not shown, a mask may be formed on the seed layer 121b and then patterned through a general photolithography process. In some examples, the seed layer 121b may be exposed to the outside through a patterned mask. In some examples, the patterned mask may include an opening that may expose a portion of the seed layer 121b to the outside. In some examples, the mask may be referred to as a photoresist or a resin.

In some examples, a relatively thick conductive layer 121c may be formed in openings of the patterned mask over exposed portions of the relatively thin seed layer 121 b. Here, since the pattern has been formed using the mask, the relatively thick conductive layer 121c may be formed only within the opening of the formed pattern. In some examples, the conductive layer 121c may be referred to as a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some examples, redistribution layer 121c may be made of any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents thereof). Redistribution layer 121c may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). After the redistribution layer 121c is formed, the patterned mask may be removed. In addition, the relatively thin seed layer 121b formed under the patterned mask may be removed using, for example, a soft etching process after the patterned mask is removed. The thickness of redistribution layer 121c may be in a range of about 2 μm to about 10 μm. Redistribution layer 121c may function to electrically connect interconnects 131 and 132 of electronic device 130 to conductive posts 112 of base structure 110.

The above process is repeated a plurality of times to form the substrate 120 on the base structure 110. Here, the conductive layer 124c formed on the topmost surface of the substrate 120 may be referred to as a conductive pad, a micro pad, or a bonding pad. In some examples, the conductive pad 124c may be formed to protrude from the top surface of the substrate 120 by a predetermined height. The width of the conductive pad 124c may be in the range of about 1 μm to about 80 μm.

In some examples, to prevent the conductive pad 124c from being oxidized, an antioxidant layer 124d may be further formed on the top surface of the conductive pad 124 c. In some examples, the antioxidant layer 124d may be referred to as a corrosion protection layer or a solder spread improvement layer. In some examples, the antioxidant layer 124d may be made of tin, gold, silver, nickel, palladium, or equivalents thereof. The antioxidant layer 124d may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The width of the antioxidant layer 124d may be in the range of about 1 μm to about 80 μm.

In some examples, the substrate 120 may be referred to as an interconnect structure, a build-up structure, a circuit stack structure, an RDL structure, or a printed circuit board. In the illustrated example of the present disclosure, a substrate 120 is shown that includes four dielectric layers 121a, 122a, 123a, and 124a, four conductive layers 121b, 122b, 123b, and 124b, and four conductive layers 121c, 122c, 123c, and 124 c. However, the number of layers may be less than or greater than four.

In the example of fig. 2, substrate 120 appears as a redistribution layer (RDL) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers that may be formed (a) layer-by-layer over an electronic device to which the RDL substrate is to be electrically coupled, or (b) layer-by-layer over a carrier that is completely or at least partially removed after coupling the electronic device and the RDL substrate together. RDL substrates can be fabricated layer by layer as wafer-level substrates in a wafer-level process on a circular wafer, and/or as panel-level substrates in a panel-level process on a rectangular or square panel carrier. The RDL substrate may be formed in an additive build-up process that may include one or more dielectric layers stacked alternately with one or more conductive layers defining respective conductive redistribution patterns or traces configured to collectively (a) fan out an electrical trace out of a footprint of the electronic device and/or (b) fan the electrical trace into the footprint of the electronic device. The conductive pattern may be formed using a plating process, such as an electroplating process or an electroless plating process. The conductive pattern may comprise a conductive material, such as copper or other plateable metal. The locations of the conductive patterns may be made using a photo-patterning process, such as a photolithography process and a photoresist material used to form a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photo-patterning process that may include a photolithographic mask through which light is exposed to features desired for the photo-pattern, such as vias in the dielectric layer. Thus, the dielectric layer may be made of a photo-definable organic dielectric material, such as Polyimide (PI), benzocyclobutene (BCB), or Polybenzoxazole (PBO). Such dielectric materials may be spun on or otherwise coated in liquid form, rather than attached in the form of a pre-formed film. To allow the desired light-defining features to be formed appropriately, thisThe photodefinable dielectric material may omit the structural reinforcing agent or may be free of fillers, without lines, woven fabrics, or other particles that might interfere with light from the photopatterning process. In some examples, such filler-free properties of the filler-free dielectric material may allow for a reduction in the thickness of the resulting dielectric layer. Although the photodefinable dielectric material described above can be an organic material, in other examples, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of the one or more inorganic dielectric layers may include silicon nitride (Si)₃N₄) Silicon oxide (SiO2) and/or SiON. The one or more inorganic dielectric layers may be formed by growing the inorganic dielectric layers using an oxidation or nitridation process rather than using a photo-defined organic dielectric material. Such inorganic dielectric layers may be free of fillers, no wires, woven fabrics, or other distinct inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including Bismaleimide Triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.

In other examples, substrate 120 may be a preformed substrate. The pre-formed substrate may be fabricated prior to attachment to the electronic device and may include a dielectric layer between respective conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer that may be attached in the form of a pre-formed film rather than in the form of a liquid, and may contain a resin with fillers such as wires, woven fabric and/or other inorganic particles for rigid and/or structural support. Because the dielectric layer is not photodefinable, features such as vias or openings can be formed by using a drill or laser. In some examples, the dielectric layer may include a prepreg or an ajinomoto build-up film (ABF). The preformed substrate may contain a permanent core structure or carrier, such as a dielectric material including Bismaleimide Triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the pre-formed substrate may be a coreless substrate omitting the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier that is removed after forming the dielectric and conductive layers and before attaching to the electronic device. The preformed substrate may be referred to as a Printed Circuit Board (PCB) or a laminate substrate. Such pre-formed substrates may be formed by a semi-additive process or a modified semi-additive process.

Fig. 2F illustrates the process of attaching the electronic device 130 at a later stage of manufacture. In the example shown in fig. 2F, electronic device 130 may be electrically connected to substrate 120. In some examples, a pick-and-place apparatus (not shown) may pick up the electronic device 130 to place the electronic device 130 on the conductive pad 124c of the substrate 120. Next, the electronic device 130 may be electrically connected to the substrate 120, for example, by batch reflow, thermal compression, or laser assisted bonding.

In some examples, the electronic device 130 may be referred to as a semiconductor die or semiconductor chip. Additionally, in some examples, the electronic device 130 may include at least one of a logic die, a micro-control unit, a memory, a digital signal processor, a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband system-on-a-chip processor, an application specific integrated circuit, or an equivalent thereof.

In some examples, the electronic device 130 may include an active region and an inactive region. Additionally, in some examples, the active region may be disposed facing the substrate 120. Additionally, in some examples, the active region may include interconnects 131. In some examples, the interconnect 131 may be referred to as a die pad, a bond pad, an aluminum pad, a conductive pillar, or a conductive post. The width of the interconnection 131 may be in the range of about 2 μm to about 80 μm.

In addition, each of the interconnects 131 may be connected to the conductive pad 124c and/or the antioxidant layer 124d of the substrate 120 by the low melting point material 132. In one example, the low melting point material 132 may include any one or more of Sn, Ag, Pb, Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, Sn-Ag-Cu, or any equivalent. The interconnection 131 of the electronic device 130 and the conductive pad 124c of the substrate 120 may be electrically connected to each other through the low melting point material 132.

In some examples, a dielectric layer 160 may be further filled between the substrate 120 and the electronic device 130. In some examples, the dielectric layer 160 may surround the interconnect 131, the low melting point material 132, the conductive pad 124c, and the antioxidant layer 124d of the electronic device 130. In some examples, the dielectric layer 160 may be referred to as an underfill, a Capillary Underfill (CUF), or a non-conductive paste. In some examples, the underfill 160 may be a resin without an inorganic filler. In some examples, after the electronic device 130 is electrically connected to the substrate 120, the underfill 160 may be injected into the gap between the electronic device 130 and the substrate 120 through a capillary and then cured. In some examples, the underfill 160 may be formed around the perimeter of the gap between the electronic device 130 and the substrate 120, and then the underfill 160 will fill the gap by capillary forces. In some instances, the underfill 160 may be dispensed first to cover the conductive pads 124c disposed on the substrate 120, and then the interconnects 131 and/or the low-melting point material 132 of the electronic device 130 may be electrically connected to the conductive pads 124c while passing through the underfill 160. The underfill 160 may prevent the electronic device 130 from being electrically disconnected from the substrate 120 due to physical impact or chemical impact.

Fig. 2G shows the encapsulation process at a later stage of fabrication. In the example shown in fig. 2G, the electronic device 130 may be encapsulated by an encapsulant 140. In some examples, the encapsulant 140 may contact the top and side surfaces of the electronic device 130 and may contact the underfill 160. However, in some examples, the encapsulant 140 may not contact the bottom surface of the electronic device 130 and the bottom surface of the underfill 160. In some examples, the encapsulant 140 may not contact the top surface of the electronic device 130 to allow the top surface of the electronic device 130 to be exposed to the outside through the encapsulant 140. In some examples, the encapsulant 140 may be referred to as an epoxy mold compound, an epoxy mold resin, a protective material, or an encapsulant. In addition, in some examples, the encapsulant 140 may be referred to as a molded part, a sealed part, an encapsulated part, a package, or a body. In some examples, the encapsulant 140 may include, but is not limited to, organic resins, inorganic fillers, curing agents, catalysts, colorants, or flame retardants. The encapsulant 140 may be formed by any of a variety of processes. In some examples, the encapsulant 140 may be formed by, but is not limited to, a molding operation, compression molding, transfer molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The thickness of the encapsulant 140 may be in the range of about 50 μm to about 1000 μm. The encapsulant 140 may encapsulate the electronic device 130 to protect the electronic device 130 from external elements and/or environmental exposure. In some examples, the encapsulant 140 may act as an underfill, such as a molded underfill formed between the substrate 120 and the electronic device 130.

In some examples, the material forming the encapsulant 140 may be the same as or different from the material of the base structure 110. When the material forming the encapsulant 140 encapsulating the electronic device 130 is the same as the material of the base structure 110, Coefficients of Thermal Expansion (CTE) of the upper and lower regions of the semiconductor device 100 may be substantially the same as each other to suppress warpage of the semiconductor device 100.

For example, the CTE of the substrate 120 may be different from the CTE of the encapsulant 140. Accordingly, the substrate 120 and the encapsulant 140 may tend to warp or bend in one direction due to heat applied during a manufacturing process of the semiconductor package or heat generated during electrical operation of the semiconductor package. However, encapsulants 113 and 140 can be selected to have the same or similar CTE, and can be formed on opposing upper and lower portions of substrate 120, respectively. Therefore, the expansion or warpage due to the difference between the CTE of the encapsulant 140 and the CTE of the substrate 120 tends to cancel the expansion or warpage due to the difference between the CTE of the encapsulant 113 and the CTE of the substrate 120. Therefore, even if heat is applied during the manufacturing process of the semiconductor package or heat is generated during the electrical operation of the semiconductor package, the amount of warpage of the semiconductor package that is bent in one direction can be suppressed or reduced. In some examples, the CTE of the substrate 120 may be greater than the CTE of the encapsulant 140 and greater than the CTE of the encapsulant 113.

There may also be instances where the encapsulant 140 forming the encapsulated electronic device 130 is a different material than the encapsulant 113 and/or the base structure 110, while still improving the warpage of the semiconductor device 100. For example, even if different from each other, the material or CTE of encapsulant 140 and the material or CTE of encapsulant 113 may be selected such that when the thickness of encapsulant 140, the thickness of encapsulant 113, and/or the presence of electronic device 130 are also considered, the net effect is that warpage due to the interface between substrate 120 and encapsulant 140 cancels warpage along the interface between substrate 120 and encapsulant 113.

Fig. 2H illustrates a process of removing a portion of the molded part 140 at a later stage of manufacture. In the example shown in fig. 2H, the molding member 140 may be ground and/or etched, thereby exposing the top surface of the electronic device 130 to the outside. The removal process may be performed until the thickness of the electronic device 130 becomes less than about 500 μm. As a result of the removal process, a top surface of the molded part 140 may be coplanar with a top surface of the electronic device 130.

Fig. 2I illustrates the process of attaching carrier 172 at a later stage of manufacture. In the example shown in fig. 2I, a carrier 172 may be attached to the molded component 140 and the top surface of the electronic device 130. In some examples, the carrier 172 may be attached to the molded part 140 and the top surface of the electronic device 130 using a temporary adhesive layer. The temporary bonding layer may be made of a material configured to lose its adhesiveness when exposed to high temperature or light. The upper carrier 172 may fix or support the device while removing the lower carrier 171. The upper carrier 172 may be substantially planar. In some examples, the upper carrier 172 may also be referred to as a plate, wafer, panel, or tape. Additionally, in some examples, the upper carrier 172 may be made of any one or more of a metal (e.g., SUS), a wafer (e.g., silicon), a ceramic (e.g., alumina), a glass (e.g., soda-lime glass), or any equivalent. The upper carrier 172 may have a thickness in the range of about 500 μm to about 1500 μm and a width in the range of about 100mm to about 500 mm.

Fig. 2J illustrates the process of removing carrier 171 at a later stage of fabrication. In the example shown in fig. 2J, the carrier 171 may be removed from the base structure 110. In some examples, carrier 171 can be removed by grinding and/or etching using a grinding operation and/or an etching operation. In some examples, the seed layer 111 formed on the bottom surface of the conductive stud 112 may also be removed when the grinding and/or etching is performed on the carrier 171. Accordingly, the bottom surface of the conductive post 112 may be exposed to the outside through the encapsulant 113. In some examples, a bottom surface of the conductive posts 112 may be coplanar with a bottom surface of the encapsulant 113.

Fig. 2K shows the process of removing carrier 172 at a later stage of fabrication. In the example shown in fig. 2K, the upper carrier 172 may also be removed. As described above, the top surface of the electronic device 130 and the top surface of the encapsulant 140 may be coplanar on the semiconductor device 100, while the bottom surface of the conductive posts 112 of the base structure 110 and the bottom surface of the encapsulant 113 may be coplanar under the semiconductor device 100. In some examples, carrier 172 may be removed using a grinding operation and/or an etching operation in the same manner or in a similar manner as carrier 171 is removed as discussed above with respect to fig. 2J.

Fig. 2L illustrates a process of forming the interconnect 150 at a later stage of fabrication. In the example shown in fig. 2L, a relatively thin conductive layer 151 may be formed on the entire bottom surface of the base structure 110, and a relatively thick conductive layer 152 may be formed on the relatively thin conductive layer 151. In some examples, the relatively thin conductive layer 151 may be referred to as a seed layer or a base layer. In some examples, the seed layer 151 may be formed on the bottom surface of the conductive posts 112 and the bottom surface of the encapsulant 113.

The seed layer 151 may be made of any of a variety of conductive materials (e.g., titanium, tungsten, titanium/tungsten, copper, gold, silver, palladium, nickel, or equivalents thereof). Additionally, in some examples, the seed layer 151 may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The seed layer 151 may be about thick

To about

Within the range of (1). Seed layer 151 may facilitate formation of conductive layer 152 to a predetermined thickness at a later manufacturing stage.

In some examples, a relatively thick conductive layer 152 may be formed on a relatively thin seed layer 151. In some examples, a patterned mask (not shown) may be used to form a pattern or opening on the seed layer 151, and the relatively thick conductive layer 152 may be formed only within the pattern or opening. In some examples, a relatively thick conductive layer 152 may be formed in a pattern of the patterned mask on the exposed portions of the relatively thin seed layer 151. Here, since the pattern has been formed using the mask, the relatively thick conductive layer 152 may be formed only within the opening of the formed pattern. In some examples, conductive layer 152 may be referred to as a conductive post or conductive stub. In some examples, conductive pillars 152 may be made of any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents thereof). Conductive pillars 152 can be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). After conductive pillars 152 are formed, the patterned mask can be removed. In addition, the relatively thin seed layer 151 formed around the relatively thick conductive pillars 152 may also be removed using, for example, a soft etch process. Conductive posts 152 may have a thickness in the range of about 5 μm to about 50 μm.

In some examples, interconnect tips 153 of a material having a relatively low melting point may be connected to conductive pillars 152. In some examples, the melting point of interconnect tips 153 may be lower than the melting point of conductive pillars 152. In some examples, the interconnect tip 153 may be referred to as a solder ball, solder bump, solder cap, conductive ball, conductive bump, or conductive cap. In some examples, after dispensing solder to the bottom surfaces of conductive pillars 152, interconnect tips 153 may be formed on the bottom surfaces of conductive pillars 152 by a batch reflow process. In some examples, the patterned mask used to form conductive pillars 152 may be reused to form interconnect tips 153. In some examples, interconnect tips 153 may be formed in a pattern or opening of the patterned mask over the exposed portions of conductive pillars 152. Here, since the pattern has been formed using the mask, the interconnection tip 153 may be formed only within the opening of the pattern. In some examples, the interconnect tip 153 may include any one or more of Sn, Ag, Pb, Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, Sn-Ag-Cu, or any equivalent. The interconnect tip 153 may have a thickness in the range of about 0.5 μm to about 30 μm and a width in the range of from about 2 μm to about 80 μm. After the formation of the interconnect tip 153, the patterned mask may be removed. In some examples, if interconnect tips 153 are formed using a patterned mask, seed layer 151 formed around conductive pillars 152 and interconnect tips 153 may now be removed using, but not limited to, a soft etch process.

As described above, the interconnection 150 including the seed layer 151, the conductive pillar 152, and the interconnection tip 153 may be completed. The interconnection 150 may function to electrically connect the semiconductor device 100 or the semiconductor package 190 to an external device (not shown). Although the interconnect 150 is shown as being formed after removal of the carrier 172, this is not a limitation of the present disclosure. In other examples, the interconnects 150 may be formed prior to removing the carrier 172.

Fig. 3 illustrates a cross-sectional view of another example semiconductor device. Due to differences in manufacturing processes, the semiconductor device 200 shown in fig. 3 may have a structure different from that of the semiconductor device 100 shown in fig. 1. In the example shown in fig. 3, the semiconductor device 200 may include a substrate 120, an electronic device 130, an encapsulant 140, a base structure 210, and an interconnection 150.

The substrate 120 may include dielectric layers 121a, 122a, 123a, and 124a and conductive layers 121b, 122b, 123b, 124b, 121c, 122c, 123c, 124c, and 124 d. The electronic device 130 may include interconnects 131 and 132. The encapsulant 140 may contact the top surface of the substrate 120 and the side surfaces of the electronic device 130. The base structure 210 may include conductive layers 211 and 212 and a dielectric layer 213. In addition, the interconnection 150 may be located on a bottom surface of the base structure 210.

The substrate 120, the encapsulant 140, the base structure 210, and the interconnects 150 may be referred to as a semiconductor package 290 or a package 290. The semiconductor package 290 may protect the electronic device 130 from external elements and/or environmental exposure. In addition, the semiconductor package 290 may provide electrical coupling between an external device (not shown) and the electronic device 130.

Fig. 4A to 4K show cross-sectional views of an example method for manufacturing another example semiconductor device. Fig. 4A shows a process of providing a carrier 271 at an early manufacturing stage.

In the example shown in fig. 4A, carrier 271 may have substantially the same shape and characteristics as carrier 171 shown in fig. 2A.

Fig. 4B illustrates a process of forming the substrate 120 at a later stage of fabrication. In the example shown in fig. 4B, a substantially planar substrate 120 may be formed or deposited directly on a carrier 271. In one example, the dielectric layers 121a, 122a, 123a, and 124a and the conductive layers 121b, 122b, 123b, 124b, 121c, 122c, 123c, 124c, and 124d may be sequentially stacked on one another on the carrier 271, thereby completing the substrate 120.

In some examples, dielectric layer 121a may cover the top surface of carrier 271. Since the top surface of the carrier 271 is formed to be planar, the dielectric layer 121a may also be formed to be planar. In some examples, the dielectric layer 121a may be referred to as a passivation layer, an insulating layer, or a protective layer. The dielectric layer 121a may be made of various non-conductive materials (e.g., Si)₃N₄、SiO₂SiON, Polyimide (PI), benzocyclobutene (BCB), Polybenzoxazole (PBO), Bismaleimide Triazine (BT), epoxy, phenolic, silicone, acrylate polymer, or equivalents thereof). In addition, the dielectric layer 121a may be formed using any of various processes (e.g., PVD, CVD, MOCVD, ALD, LPCVD, PECVD, printing, spin coating, spray coating, sintering, thermal oxidation, or equivalents thereof). In some examples, dielectric layer 121a may be patterned to form an opening that exposes a portion of carrier 271. The thickness of the dielectric layer 121a may be in the range of about 1 μm to about 10 μmAnd the width of the opening may be in the range of about 5 μm to about 70 μm.

In some examples, the conductive layer 121b can be formed entirely over the dielectric layer 121a and the exposed regions of the carrier 271. In some examples, the conductive layer 121b may be referred to as a seed layer or a base layer. In some examples, seed layers 121b may be formed on the top surface of the dielectric layer 121a, the sidewalls of the opening, and the top surface of the carrier 271, respectively, and all of the conductive layers 121b may be electrically connected to each other.

In some examples, the seed layer 121b may be made of any of a variety of conductive materials (e.g., titanium, tungsten, titanium/tungsten, copper, gold, silver, palladium, nickel, or equivalents thereof). Additionally, in some examples, the seed layer 121b may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The thickness of the seed layer 121b may be about

To aboutWithin the range of (1). The seed layer 121b may facilitate the formation of the conductive layer 121c to a predetermined thickness at a later manufacturing stage.

Although not shown, a mask may be formed on the seed layer 121b and then patterned through a general photolithography etching process. In some examples, the seed layer 121b may be exposed to the outside through a patterned mask. In some examples, the mask may be referred to as a photoresist or a resin.

In some examples, a relatively thick conductive layer 121c may be formed in openings of the patterned mask over exposed portions of the relatively thin seed layer 121 b. Here, since the pattern has been formed using the mask, the relatively thick conductive layer 121c may be formed only within the opening of the pattern. In some examples, the conductive layer 121c may be referred to as a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some examples, redistribution layer 121c may be made of any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents thereof). Redistribution layer 121c may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). After the redistribution layer 121c is formed, the patterned mask may be removed. In addition, the relatively thin seed layer 121b formed under the patterned mask may be removed using a soft etching process after the patterned mask is removed. The thickness of redistribution layer 121c may be in a range of about 2 μm to about 10 μm. The redistribution layer 121c may function as conductive posts 212 that electrically connect the interconnects 131 and 132 of the electronic device 130 to the base structure 210.

The above process may be repeated a plurality of times, thereby completing the substrate 120 on the carrier 271. Here, the conductive layer 124c formed on the topmost surface of the substrate 120 may be referred to as a conductive pad, a micro pad, or a bonding pad. In some examples, the conductive pad 124c may be formed to protrude from the top surface of the substrate 120 by a predetermined height. The width of the conductive pad 124c may be in the range of about 2 μm to about 80 μm.

In some examples, to prevent the conductive pad 124c from being oxidized, an antioxidant layer 124d may be further formed on the top surface of the conductive pad 124 c. In some examples, the antioxidant layer 124d may be made of tin, gold, silver, nickel, palladium, or equivalents thereof. The antioxidant layer 124d may be referred to as a corrosion prevention layer or a solder spread improvement layer. The antioxidant layer 124d may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The width of the antioxidant layer 124d may be in the range of about 1 μm to about 80 μm.

In some examples, the substrate 120 may be referred to as an interconnect structure, a build-up structure, a circuit stack structure, an RDL structure, or a printed circuit board. In the example illustrating the present disclosure, a substrate 120 is shown that includes four dielectric layers 121a, 122a, 123a, and 124a, four conductive layers 121b, 122b, 123b, and 124b, and four conductive layers 121c, 122c, 123c, and 124 c. However, the number of layers may be less than or greater than four.

Fig. 4C shows the process of attaching the electronic device 130 at a later stage of manufacture. In the example shown in fig. 4C, the process of attaching the electronic device 130 may be similar to the process of attaching the electronic device 130 shown in fig. 2F.

Fig. 4D shows the encapsulation process at a later stage of fabrication. In the example shown in fig. 4D, the encapsulation process may be the same as or similar to that of fig. 2G.

Fig. 4E shows the process of removing a portion of the molded part 140 at a later stage of manufacture. In the example shown in fig. 4E, the removal process may be the same as or similar to the removal process of fig. 2H.

Fig. 4F shows the process of attaching carrier 272 at a later stage of manufacture. The process of attaching carrier 272 shown in fig. 4F may be the same as or similar to the process of attaching carrier 272 in fig. 2I.

Fig. 4G shows the process of removing the carrier 271 at a later stage of manufacture. In the example shown in fig. 4G, the carrier 271 may be removed from the substrate 120. In some examples, carrier 271 can be removed by grinding and/or etching. In some examples, the seed layer 121b formed on the bottom surface of the substrate 120 may be removed when the grinding and/or etching is performed on the carrier 271. In some examples, the bottom surface of redistribution layer 121c may be removed. Accordingly, the bottom surface of the redistribution layer 121c of the substrate 120 may be exposed to the outside through the dielectric layer 121 a. In some examples, a bottom surface of redistribution layer 121c may be coplanar with a bottom surface of dielectric layer 121 a.

Fig. 4H illustrates a process of forming conductive layers 211 and 212 at a later stage of fabrication. In the example shown in fig. 4H, conductive layers 211 and 212 may be formed on the bottom surface of the substrate 120. In some examples, conductive layers 211 and 212 may be formed on the bottom surfaces of dielectric layer 121a and redistribution layer 121c of substrate 120. In some examples, conductive layer 211 may be referred to as a seed layer or a base layer. In some examples, the seed layer 211 may be made of any of a variety of conductive materials (e.g., titanium, tungsten, titanium/tungsten, copper, gold, silver, palladium, nickel, or equivalents thereof). In addition, in some instancesIn an example, the seed layer 211 may be formed using any of various processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). The seed layer 211 may be about thick

To aboutWithin the range of (1). The seed layer 211 may facilitate the formation of the conductive layer 212 to a predetermined thickness at a later manufacturing stage.

In addition, in the example shown in fig. 4H, a relatively thick conductive layer 212 may be formed on the relatively thin seed layer 211. In some examples, a patterned mask may be used to form a pattern or opening on the seed layer 211, and the conductive layer 212 may be formed only within the pattern or opening. In some examples, the conductive layer 212 may be formed in an opening of a patterned mask over an exposed portion of the seed layer 211. Here, since the pattern has been formed using the mask, the conductive layer 212 may be formed only within the opening of the formed pattern. In some examples, conductive layer 212 may be referred to as a conductive stud or an under bump metallization. In some examples, the conductive posts 212 may be made of any of a variety of conductive materials (e.g., copper, gold, silver, or equivalents thereof). Conductive posts 212 may be formed using any of a variety of processes (e.g., sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or equivalents thereof). After the conductive posts 212 are formed, the patterned mask may be removed. In addition, a soft etch process may also be used to remove the relatively thin seed layer formed around the relatively thick conductive pillars 212. The thickness of the conductive peg 212 may be in the range of about 1 μm to about 10 μm. The conductive posts 212 may be electrically connected to the interconnects 150 to be formed under the substrate 120 and/or the base structure 210 at a later stage of fabrication.

Fig. 4I illustrates a process of forming the dielectric layer 213 at a later stage of fabrication. In the example shown in fig. 4I, the conductive posts 212 formed under the substrate 120 may be covered by a dielectric layer 213. In some examples, the dielectric layer 213 may cover the bottom and side surfaces of the conductive post 212. However, the dielectric layer 213 may not cover the top surface of the conductive post 212. In some examples, the dielectric layer 213 may not cover the bottom surface of the conductive post 212, thereby allowing the bottom surface of the conductive post 212 to be exposed to the outside through the dielectric layer 213. In some examples, the dielectric layer 213 may be referred to as an encapsulant, a sealant, an epoxy molding compound, or an epoxy molding resin. In addition, in some examples, the encapsulant 213 may be referred to as an encapsulation member, a molded member, a protective member, or a body. In some examples, encapsulant 213 may include, but is not limited to, organic resins, inorganic fillers, curing agents, catalysts, colorants, flame retardants, or equivalents of the foregoing. The encapsulant 213 may be formed by any of a variety of processes. In some examples, the encapsulant 213 may be formed by, but is not limited to, compression molding, transfer molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film assisted molding. The thickness of the encapsulant 213 may be in the range of about 1 μm to about 10 μm. The encapsulant 213 may securely encapsulate the conductive posts 212 to reduce or prevent the substrate 120 from warping at a later stage.

Fig. 4J shows the removal process at a later stage of fabrication. In the example shown in fig. 4J, the bottom surfaces of the conductive posts 212 and the encapsulant 213 are ground or etched to expose the bottom surfaces of the conductive posts 212 to the outside through the bottom surface of the encapsulant 213. In some examples, the bottom surface of the conductive posts 212 and the bottom surface of the encapsulant 213 may be formed to be coplanar. As described above, at a later manufacturing stage, the base structure 210 may be completed and the interconnects 150 may be formed under the base structure 210.

Fig. 4K illustrates a process of forming the interconnect 150 at a later stage of fabrication. In the example shown in fig. 4K, the process of forming the interconnect 150 may be substantially the same as the process of forming the interconnect 150 shown in fig. 2K.

At the same time, carrier 272 may be removed. As described above, the top surface of the electronic device 130 may be coplanar with the top surface of the encapsulant 140 on the semiconductor device 200.

In summary, a semiconductor device includes: a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material; an electronic device located on the top surface of the RDL substrate; an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device; a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate; and a second protective material contacting side surfaces of the electrical interconnect and the bottom surface of the RDL substrate.

A method for manufacturing a semiconductor device includes: forming a base structure having conductive posts; forming a redistribution layer (RDL) substrate on the base structure; placing an electronic device on a top surface of the RDL substrate; and forming a protective material contacting a side surface of the electronic device and the top surface of the RDL substrate.

A method for manufacturing a semiconductor device includes: forming a redistribution layer (RDL) substrate on a first carrier, the RDL substrate having a top surface and a bottom surface; placing an electronic device on the top surface of the RDL substrate; forming a first protective material using a first molding operation, wherein the first protective material contacts a side surface of the electronic device and the top surface of the RDL substrate; attaching a second carrier to the first protective material; removing the first carrier from the RDL substrate; forming conductive posts on the bottom surface of the RDL substrate using a first plating operation; and forming a second protective material using a second molding operation, wherein the second protective material contacts side surfaces of the conductive posts and the bottom surface of the RDL substrate.

The present disclosure contains references to certain examples. However, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. Additionally, modifications may be made to the disclosed examples without departing from the scope of the disclosure. Therefore, it is intended that the disclosure not be limited to the disclosed examples, but that the disclosure will include all examples falling within the scope of the appended claims.