阅读说明：本技术 半导体封装件及其制备方法 (Semiconductor package and preparation method thereof ) 是由 苏国辉 于 2019-10-11 设计创作，主要内容包括：本公开提供一种半导体封装件及其制备方法。该半导体封装件包括一下半导体层、一上半导体层、一固定结构以及一模塑层。该下半导体层具有一贴合区以及一固定区,该固定区邻近该贴合区设置。该上半导体层配置在该贴合区上。该固定结构邻近该上半导体层配置。该固定结构具有至少一固定孔,该固定孔具有一开口,该开口相对应该固定区设置,且该开口具有一第一宽度。该模塑层覆盖该上半导体层的各侧壁。该模塑层具有至少一固定突出物,该固定突出物延伸进入该固定孔中,该固定突出物具有一第一扩张部,该第一扩张部位在该开口下方,且该第一扩张部具有一第二宽度,该第二宽度大于该第一宽度。(The present disclosure provides a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a lower semiconductor layer, an upper semiconductor layer, a fixed structure and a molding layer. The lower semiconductor layer has a bonding region and a fixing region disposed adjacent to the bonding region. The upper semiconductor layer is disposed on the bonding region. The fixed structure is disposed adjacent to the upper semiconductor layer. The fixing structure is provided with at least one fixing hole, the fixing hole is provided with an opening, the opening is arranged corresponding to the fixing area, and the opening is provided with a first width. The molding layer covers sidewalls of the upper semiconductor layer. The molding layer has at least one fixing protrusion extending into the fixing hole, the fixing protrusion has a first expansion portion below the opening, and the first expansion portion has a second width greater than the first width.)

1. A semiconductor package, comprising:

a lower semiconductor layer having a bonding region and a fixed region disposed adjacent to the bonding region;

an upper semiconductor layer disposed on the bonding region;

a fixing structure disposed adjacent to the upper semiconductor layer, wherein the fixing structure has at least one fixing hole, the fixing hole has an opening disposed corresponding to the fixing region, and the opening has a first width; and

a molding layer covering each sidewall of the upper semiconductor layer, wherein the molding layer has at least one fixing protrusion extending into the fixing hole, the fixing protrusion has a first expansion portion below the opening, and the first expansion portion has a second width greater than the first width.

2. The semiconductor package according to claim 1, wherein said upper semiconductor layer is a wafer stack having a plurality of semiconductor wafers.

3. The semiconductor package according to claim 1, wherein the mounting structure further comprises an oxide layer on the mounting region of the lower semiconductor layer, the molding layer disposed on the oxide layer.

4. The semiconductor package according to claim 3, wherein the at least one anchor hole is in the oxide layer.

5. The semiconductor package according to claim 1, wherein the at least one anchor hole is in the lower semiconductor layer.

6. The semiconductor package according to claim 5, wherein the fixing protrusion extends from a top surface of the lower semiconductor layer into the fixing hole.

7. The semiconductor package according to claim 1, further comprising an adhesive layer disposed between the lower semiconductor layer and the upper semiconductor layer.

8. The semiconductor package according to claim 1, further having a plurality of through-silicon vias electrically connecting a plurality of contact pads located under the lower semiconductor layer to the upper semiconductor layer.

9. The semiconductor package according to claim 1, wherein the fixing structure is disposed around the upper semiconductor layer.

10. The semiconductor package according to claim 9, wherein the fixing structure is a porous structure and has a plurality of fixing holes disposed around the upper semiconductor layer.

11. The semiconductor package according to claim 10, wherein the fixing hole is a blind hole.

12. A method for manufacturing a semiconductor package includes:

bonding an upper semiconductor layer on a bonding region of a lower semiconductor layer;

forming an oxide layer on a fixed region of the lower semiconductor layer adjacent to the bonding region;

forming at least one fixed hole in the oxide layer, wherein the fixed hole has an opening and a second expansion portion, the second expansion portion is located below the opening, the opening has a first width, and the second expansion portion has a second width, the second width is greater than the first width of the opening; and

a molding layer is formed to cover each sidewall of the upper semiconductor layer and fill up the at least one fixing hole.

13. The method of claim 12, wherein the at least one securing hole is formed by wet etching the oxide layer.

14. The method of claim 12, further comprising:

before forming the at least one fixing hole in the oxide layer, providing an etching mask on the oxide layer, wherein the etching mask has at least one etching through hole, and the at least one etching through hole is respectively arranged corresponding to the at least one opening of the fixing hole; and

the etch mask is removed after the at least one securing hole is formed.

15. The method of claim 12, further comprising:

the molding layer is cured.

16. The method of claim 12, further comprising:

an adhesive layer is formed between the upper semiconductor layer and the lower semiconductor layer.

17. A method for manufacturing a semiconductor package includes:

bonding an upper semiconductor layer on a bonding region of a lower semiconductor layer;

forming at least one fixed hole in a fixed region of the lower semiconductor layer, wherein the fixed hole has an opening and a second expanded portion, the second expanded portion is located below the opening, the opening has a first width, the second expanded portion has a second width, and the second width is greater than the first width of the opening; and

a molding layer is formed to cover each sidewall of the upper semiconductor layer and fill up the at least one fixing hole.

18. The method of claim 17, wherein the at least one securing hole is formed by wet etching the lower semiconductor layer.

19. The method of claim 17, further comprising:

before forming the at least one fixing hole in the fixing region of the lower semiconductor layer, providing an etching mask on the fixing region of the lower semiconductor layer, wherein the etching mask has at least one etching through hole respectively disposed corresponding to the at least one opening of the fixing hole; and

the etch mask is removed after the at least one securing hole is formed.

20. The method of claim 17, further comprising:

an adhesive layer is formed between the upper semiconductor layer and the lower semiconductor layer.

Technical Field

The present disclosure claims priority and benefit of 2019/04/19 application U.S. official application No. 16/389,167, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor package and a method of manufacturing the same. And more particularly, to a semiconductor package having a plurality of semiconductor layers and a molding layer and a method of fabricating the same.

Background

For many modern applications, semiconductor devices are essential. As electronic technology advances, the size of semiconductor devices continues to become smaller while providing integrated circuits with better functionality and larger numbers. Due to the miniaturization of the specifications of semiconductor devices, a conventional semiconductor package having a plurality of semiconductor layers is provided.

The conventional semiconductor package has a lower semiconductor layer and an upper semiconductor layer, and the upper semiconductor layer is disposed on a bonding region (attached region) of the lower semiconductor layer. A molding layer (molding layer) disposed around the upper semiconductor layer is disposed on a fixing region (fixing region) of the lower semiconductor layer.

However, nowadays, the fixed region becomes smaller and smaller, and the molding layer can be separated from the lower semiconductor layer.

The above description of "prior art" is merely provided as background, and is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is prior art.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor package. The semiconductor package comprises a lower semiconductor layer, an upper semiconductor layer, a fixed structure and a molding layer. The lower semiconductor layer has a bonding region and a fixing region disposed adjacent to the bonding region. The upper semiconductor layer is disposed on the bonding region. The fixing structure is disposed adjacent to the upper semiconductor layer, wherein the fixing structure has at least one fixing hole, the fixing hole has an opening, the opening is disposed corresponding to the fixing region, and the opening has a first width. The molding layer covers each sidewall of the upper semiconductor layer, wherein the molding layer has at least one fixing protrusion extending into the fixing hole, the fixing protrusion has a first expansion portion below the opening, and the first expansion portion has a second width greater than the first width.

According to some embodiments of the present disclosure, the upper semiconductor layer is a chip stack (chip stack) having a plurality of semiconductor chips.

According to some embodiments of the present disclosure, the fixed structure further has an oxide layer on the fixed region of the lower semiconductor layer, and the molding layer is disposed on the oxide layer.

According to some embodiments of the present disclosure, the at least one anchor hole is in the oxide layer.

According to some embodiments of the present disclosure, the at least one anchor hole is in the lower semiconductor layer.

According to some embodiments of the present disclosure, the fixing protrusion extends from a top surface of the lower semiconductor layer into the fixing hole.

According to some embodiments of the present disclosure, the semiconductor package further has an adhesive layer disposed between the lower semiconductor layer and the upper semiconductor layer.

According to some embodiments of the present disclosure, the semiconductor package further has a plurality of Through Silicon Vias (TSVs) electrically connecting a plurality of contact pads located under the lower semiconductor layer to the upper semiconductor layer.

According to some embodiments of the present disclosure, the fixing structure is disposed around the upper semiconductor layer.

According to some embodiments of the present disclosure, the fixing structure is a porous structure (porous structure) and has a plurality of fixing holes disposed around the upper semiconductor layer.

According to some embodiments of the present disclosure, the fixing holes are blind holes.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor package. The preparation method comprises the steps of attaching an upper semiconductor layer to an attachment region of a lower semiconductor layer; forming an oxide layer on a fixed region of the lower semiconductor layer adjacent to the bonding region; forming at least one fixed hole in the oxide layer, wherein the fixed hole has an opening and a second expansion portion, the second expansion portion is located below the opening, the opening has a first width, and the second expansion portion has a second width, the second width is greater than the first width of the opening; and forming a molding layer to cover each sidewall of the upper semiconductor layer and fill the at least one fixing hole.

According to some embodiments of the present disclosure, the at least one fixing hole is formed by wet etching the oxide layer.

According to some embodiments of the disclosure, the method of preparing further comprises: before forming the at least one fixing hole in the oxide layer, providing an etching mask on the oxide layer, wherein the etching mask has at least one etching through hole, and the at least one etching through hole is respectively arranged corresponding to the at least one opening of the fixing hole; and removing the etching mask after the at least one fixing hole is formed.

According to some embodiments of the disclosure, the method of preparing further comprises: curing (curing) the moulding layer.

According to some embodiments of the disclosure, the method of preparing further comprises: an adhesive layer (adhesive layer) is formed between the upper semiconductor layer and the lower semiconductor layer.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor package. The preparation method comprises the steps of attaching an upper semiconductor layer to an attachment region of a lower semiconductor layer; forming at least one fixed hole in a fixed region of the lower semiconductor layer, wherein the fixed hole has an opening and a second expanded portion, the second expanded portion is located below the opening, the opening has a first width, the second expanded portion has a second width, and the second width is greater than the first width of the opening; and forming a molding layer to cover each sidewall of the upper semiconductor layer and fill the at least one fixing hole.

According to some embodiments of the present disclosure, the at least one fixing hole is formed by wet etching the lower semiconductor layer.

According to some embodiments of the disclosure, the method of preparing further comprises: before forming the at least one fixing hole in the fixing region of the lower semiconductor layer, providing an etching mask on the fixing region of the lower semiconductor layer, wherein the etching mask has at least one etching through hole respectively disposed corresponding to the at least one opening of the fixing hole; and removing the etching mask after the at least one fixing hole is formed.

According to some embodiments of the disclosure, the method of preparing further comprises: the molding layer is cured.

According to some embodiments of the disclosure, the method of preparing further comprises: an adhesive layer is formed between the upper semiconductor layer and the lower semiconductor layer.

Due to the design of the semiconductor package of the present disclosure, the semiconductor package has a fixing structure (fixing structures) and a plurality of fixing protrusions (fixing protrusions) to reinforce the adhesive strength (adhesive strength) between the molding layer (molding layer) and the lower semiconductor layer.

In addition, the width of the fixing protrusion of the molding layer is greater than the width of the opening of the fixing hole, so that the molding layer can be more stably adhered and fixed to the fixing hole of the lower semiconductor layer.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure may be more fully understood by reference to the following description of embodiments, taken together with the appended claims, in which like reference numerals refer to like elements.

Fig. 1 is a flow chart illustrating a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

Fig. 2 is a schematic structural diagram of a semiconductor package manufactured by the manufacturing method of fig. 1 according to some embodiments of the present disclosure.

Fig. 3 to 5 are partially enlarged schematic views illustrating a semiconductor package manufactured by the manufacturing method of fig. 1 at different manufacturing stages according to some embodiments of the present disclosure.

Fig. 6 is a schematic structural diagram of a semiconductor package according to some embodiments of the present disclosure.

Fig. 7 is a schematic plan view of a semiconductor package according to some embodiments of the present disclosure.

Fig. 8 is a flow chart illustrating a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

Fig. 9 is a schematic structural diagram of a semiconductor package manufactured by the manufacturing method of fig. 8 according to some embodiments of the present disclosure.

Fig. 10 to 12 are partially enlarged schematic views illustrating a semiconductor package manufactured by the manufacturing method of fig. 8 at different manufacturing stages according to some embodiments of the present disclosure.

Fig. 13 is a schematic structural diagram of a semiconductor package according to some embodiments of the present disclosure.

Fig. 14 is a schematic structural diagram of a semiconductor package according to some embodiments of the present disclosure.

Wherein the reference numerals are as follows:

100 preparation method

s101 operation

s103 operation

s105 operation

s107 operation

s109 operation

s111 operation

200 semiconductor package

210 upper semiconductor layer

211 side wall

220 lower semiconductor layer

221 top surface

222 attachment region

223 fixation area

224 fixing structure

225 oxide layer

227 fixing hole

228 opening

230 first width

231 second expansion part

233 second width

237 through silicon via

240 adhesive layer

250 etching mask

251 etching through hole

260 molding layer

261 fixed projection

263 first expansion part

270 contact pad

700 preparation method

s701 operation

s703 operation

s705 operation

s707 operation

s709 operation

800 semiconductor package

824 fixing structure

Detailed Description

The following description of the present disclosure, which is accompanied by the accompanying drawings incorporated in and forming a part of the specification, illustrates embodiments of the present disclosure, however, the present disclosure is not limited to the embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

References to "one embodiment," "an example embodiment," "other embodiments," "another embodiment," etc., indicate that the embodiment described in this disclosure may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, repeated usage of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It will be apparent that the implementation of the disclosure does not limit the specific details known to those skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details. The scope of the present disclosure is not limited by the detailed description but is defined by the claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a flow chart illustrating a method 100 for fabricating a semiconductor package according to some embodiments of the present disclosure. Fig. 2 is a schematic structural diagram of a semiconductor package manufactured by the manufacturing method 100 of fig. 1 according to some embodiments of the present disclosure. Fig. 3 to 5 are partially enlarged schematic views illustrating a semiconductor package manufactured by the manufacturing method 100 of fig. 1 at different manufacturing stages according to some embodiments of the present disclosure. Fig. 6 is a schematic structural diagram of a semiconductor package 200 according to some embodiments of the present disclosure. Fig. 7 is a schematic plan view of a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method 100 of manufacturing the semiconductor package 200 of fig. 1 has a plurality of operations (s101, s103, s105, s107, s109, and s111), and the following description and the accompanying drawings are not to be considered as limiting the sequence of the operations.

In operation s101, as shown in fig. 2, an upper semiconductor layer 210 is bonded to a bonding region 222 of a lower semiconductor layer 220. In some embodiments, an adhesive layer (adhesive layer)240 is formed between the upper semiconductor layer 210 and the lower semiconductor layer 220 to adhere the upper semiconductor layer 210 to the lower semiconductor layer 220. In some embodiments, the upper semiconductor layer 210 is a chip stack (chip stack) having a plurality of semiconductor chips, such as memory chips (e.g., DRAMs). In some embodiments, the lower semiconductor layer 220 may be a controller chip.

In operation s103, as shown in fig. 2, an oxide layer 225 is formed on a fixed region 223 of the lower semiconductor layer 220. The fastening region 223 is disposed adjacent to the landing region 222. In some embodiments, the oxide layer 225 comprises a silicon oxide material.

In operation s105, as shown in fig. 3, an etching mask (etching mask)250 is provided on the oxide layer 225. In some embodiments, the etching mask 250 has at least one etching via (etching via) 251. In some embodiments, the etch mask 250 has a plurality of etch perforations 251.

In operation s107, as shown in fig. 4, at least one fixing hole (fixing hole)227 is formed in the oxide layer 225. In some embodiments, a plurality of fixing holes 227 are formed.

In some embodiments, the securing holes 227 are formed by an anisotropic (anisotropic) etching process. In some embodiments, the oxide layer 225 is wet etched through the etch vias 251. In this way, an undercut effect occurs below the etch mask 250. Each fixing hole 227 has an opening (opening)228 and a second expansion portion (second expansion portion)231, and the second expansion portion 231 is located below the opening 228. In some embodiments, the openings 228 are disposed corresponding to the etched through holes 251, respectively. The opening 228 has a first width 230, and the second expansion 231 has a second width 233. The second width 233 of the second expanded portion 231 is greater than the first width 230 of the opening 228.

In operation s109, the etching mask is removed as shown in fig. 5. In some embodiments, the etch mask may be removed by other etching processes or a Chemical Mechanical Planarization (CMP) process.

In operation s111, as shown in fig. 5, a molding layer (molding layer)260 is formed. In this method, fixing protrusions (fixing protrusions)261 of the molding layer 260 are formed and extend into the fixing holes 227. Each of the fixing protrusions 261 has a first expansion portion 263, the first expansion portion 263 is disposed corresponding to the second expansion portion 231, and the first expansion portion 263 has a second width 233. That is, the first and second expanded portions 263 and 231 have the same width.

As shown in fig. 6, the molding layer 260 covers each sidewall (side walls)211 of the upper semiconductor layer 210. In some embodiments, the molding layer 260 is cured by a thermal curing process. In some embodiments, the molding layer 260 comprises an epoxy compound (epoxy compound) material.

Due to the operations described above, a semiconductor package 200 as shown in fig. 6 is provided. The lower semiconductor layer 220 has a bonding region 222 and a fixed region 223, and the fixed region 223 is disposed adjacent to the bonding region 222. The upper semiconductor layer 210 is disposed on the bonding region 222. The upper semiconductor layer 210 is a wafer stack having a plurality of semiconductor wafers. The adhesive layer 240 is disposed between the lower semiconductor layer 220 and the upper semiconductor layer 210. A plurality of Through Silicon Vias (TSVs)237 are formed in the lower semiconductor layer 220 to electrically connect contact pads 270 located below the lower semiconductor layer 220 to the upper semiconductor layer 210. A fastening structure 224 is disposed adjacent the upper semiconductor layer 210. The fixing structure 224 has at least one fixing hole 227. The molding layer 260 covers each sidewall 211 of the upper semiconductor layer 210.

As shown in fig. 7, the fixed structure 224 is disposed around the upper semiconductor layer 210. The fixing structure 224 is a porous structure, and the fixing structure 224 has a plurality of fixing holes 227, and the fixing holes 227 are disposed around the upper semiconductor layer 210.

As shown in fig. 5, each fixing hole 227 has an opening 228, and the opening 228 is disposed corresponding to the fixing region 223 (fig. 6). Opening 228 has a first width 230. The fixed structure 240 further has an oxide layer 225, and the oxide layer 225 is located on the fixed region 223 of the lower semiconductor layer 220. The molding layer 260 is disposed on the oxide layer 225. At least one fixing hole 227 is formed in the oxide layer 225. The fixing holes 227 are blind holes (holes). The molding layer 260 has at least one fixing protrusion 261, and the fixing protrusion 261 extends into the fixing hole 270. The fixing protrusions 261 have first expanded portions 263, the first expanded portions 263 are located below the opening 228, and each of the first expanded portions 263 has a second width 233, the second width 233 being greater than the first width 230.

Fig. 8 is a flow chart illustrating a method 700 for fabricating a semiconductor package according to some embodiments of the present disclosure. Fig. 9 is a schematic structural diagram of a semiconductor package manufactured by the manufacturing method of fig. 8 according to some embodiments of the present disclosure. Fig. 10 to 12 are partially enlarged schematic views illustrating a semiconductor package manufactured by the manufacturing method of fig. 8 at different manufacturing stages according to some embodiments of the present disclosure. Fig. 13 is a schematic structural diagram of a semiconductor package 800 according to some embodiments of the present disclosure. Fig. 14 is a schematic structural diagram of a semiconductor package according to some embodiments of the present disclosure. In some embodiments, the method 700 of manufacturing a semiconductor package 800 of fig. 8 has a plurality of operations (s701, s703, s705, s707, and s109), and the following description and the accompanying drawings are not to be considered as limiting the sequence of the operations.

In operation s701, as shown in fig. 9, an upper semiconductor layer 210 is bonded on a bonding region 222 of a lower semiconductor layer 220. In some embodiments, an adhesive layer 240 is formed between the upper semiconductor layer 210 and the lower semiconductor layer 220 to adhere the upper semiconductor layer 210 to the lower semiconductor layer 220.

In some embodiments, the upper semiconductor layer 210 is a wafer stack having a plurality of semiconductor wafers, such as memory wafers (e.g., DRAM). In some embodiments, the lower semiconductor layer 220 may be a controller die.

In operation s703, an etch mask 250 is provided on a fixed region 223 of the lower semiconductor layer 220, as shown in fig. 10. In some embodiments, the securing region 223 is disposed adjacent to the conforming region 222. The etching mask 250 has at least one etching through hole 251. In some embodiments, the etch mask 250 has a plurality of etch perforations 251.

After providing the etch mask 250, in operation s705, as shown in fig. 11, at least one anchor hole 227 is formed in the anchor region 223 of the lower semiconductor layer 220. In some embodiments, a plurality of fixing holes 227 are formed.

In some embodiments, the securing holes 227 are formed by an anisotropic etch process. In some embodiments, the lower semiconductor layer 220 is wet etched through the etch through holes 251. In this manner, a undercutting effect occurs below the etch mask 250. Each fixing hole 227 has an opening 228 and a second expansion portion 231, and the second expansion portion 231 is located below the opening 228.

In some embodiments, the openings 228 are disposed corresponding to the etched through holes 251, respectively. Each opening 228 has a first width 230 and the second flared portion 231 has a second width 233. The second width 233 of the second expanded portion 231 is greater than the first width 230 of the opening 228.

In operation s707, as shown in fig. 12, after the fixing holes 227 are formed, the etching mask is removed. In some embodiments, the etch mask may be removed by other etching processes or a chemical mechanical planarization process.

In operation s709, as shown in fig. 12, a molding layer 260 is formed. The molding layer 260 fills the fixing holes 227. In this manner, the fixing protrusions 261 of the molding layer 260 are formed and extend into the fixing holes 227. Each of the fixing protrusions 261 has a first expanded portion 263, the first expanded portion 263 is disposed corresponding to the second expanded portion 231, and the first expanded portion 263 of the fixing protrusion 261 has the second width 233. In some embodiments, the first expanded portion 263 of the fixing protrusion 261 has the same width as the second expanded portion 231 of the fixing hole 227.

As shown in fig. 13, the molding layer 260 covers each sidewall 211 of the upper semiconductor layer 210. In some embodiments, the molding layer 260 is cured by a thermal curing process. In some embodiments, the molding layer 260 contains an epoxy compound material.

Due to the operations described above, a semiconductor package 800 as shown in fig. 13 is provided. The lower semiconductor layer 220 has a bonding region 222 and a fixed region 223, and the fixed region 223 is disposed adjacent to the bonding region 222. The upper semiconductor layer 210 is disposed on the bonding region 222 of the lower semiconductor layer 220. The upper semiconductor layer 210 is a wafer stack having a plurality of semiconductor wafers. The adhesive layer 240 is disposed between the lower semiconductor layer 220 and the upper semiconductor layer 210. A plurality of Through Silicon Vias (TSVs)237 are formed in the lower semiconductor layer 220 to electrically connect a plurality of contact pads 270 located below the lower semiconductor layer 220 to the upper semiconductor layer 210. A fixed structure 824 is disposed adjacent the upper semiconductor layer 210. The fixing structure 824 has at least one fixing hole 227. The molding layer 260 covers each sidewall 211 of the upper semiconductor layer 210.

As shown in fig. 14, a fixed structure 824 is disposed around the upper semiconductor layer 210. The fixing structure 824 is a porous structure, and the fixing structure 824 has a plurality of fixing holes 227, and the fixing holes 227 are disposed around the upper semiconductor layer 210.

As shown in fig. 12, each fixing hole 227 has an opening 228, and the opening 228 is disposed corresponding to the fixing region. Opening 228 has a first width 230. The at least one fixing hole 227 is located in the lower semiconductor layer 220. The fixing holes 227 are blind holes. The molding layer 260 has at least one fixing protrusion 261, and the fixing protrusion 261 extends into the fixing hole 227. The fixing protrusion 261 extends from a top surface 221 of the lower semiconductor layer 220 into the fixing hole 227. The fixing protrusions 261 have first expanded portions 263, the first expanded portions 263 are located below the openings 228, and each of the first expanded portions 263 has a second width 233, the second width 233 being greater than the first width 230.

In summary, due to the structure of the semiconductor package of the present disclosure, the semiconductor package has a fixing structure and a plurality of fixing protrusions to enhance the adhesive strength (adhesive strength) between the molding layer and the lower semiconductor layer.

Furthermore, the width of the fixing protrusion of the molding layer is greater than the width of the opening of the fixing hole, so that the molding layer can be more stably adhered and fixed to the fixing hole of the lower semiconductor layer.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

An embodiment of the present disclosure provides a semiconductor package. The semiconductor package comprises a lower semiconductor layer, an upper semiconductor layer, a fixed structure and a molding layer. The lower semiconductor layer has a bonding region and a fixing region disposed adjacent to the bonding region. The upper semiconductor layer is disposed on the bonding region. The fixing structure is disposed adjacent to the upper semiconductor layer, wherein the fixing structure has at least one fixing hole, the fixing hole has an opening, the opening is disposed corresponding to the fixing region, and the opening has a first width. The molding layer covers each sidewall of the upper semiconductor layer, wherein the molding layer has at least one fixing protrusion extending into the fixing hole, the fixing protrusion has a first expansion portion below the opening, and the first expansion portion has a second width greater than the first width.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor package. The preparation method comprises the steps of attaching an upper semiconductor layer to an attachment region of a lower semiconductor layer; forming an oxide layer on a fixed region of the lower semiconductor layer adjacent to the bonding region; forming at least one fixed hole in the oxide layer, wherein the fixed hole has an opening and a second expansion portion, the second expansion portion is located below the opening, the opening has a first width, and the second expansion portion has a second width, the second width is greater than the first width of the opening; and forming a molding layer to cover each sidewall of the upper semiconductor layer and fill the at least one fixing hole.

Another embodiment of the present disclosure provides a method of manufacturing a semiconductor package. The preparation method comprises the steps of attaching an upper semiconductor layer to an attachment region of a lower semiconductor layer; forming at least one fixed hole in a fixed region of the lower semiconductor layer, wherein the fixed hole has an opening and a second expanded portion, the second expanded portion is located below the opening, the opening has a first width, the second expanded portion has a second width, and the second width is greater than the first width of the opening; and forming a molding layer to cover each sidewall of the upper semiconductor layer and fill the at least one fixing hole.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this application.