Semiconductor packaging piece and manufacturing method thereof
阅读说明:本技术 一种半导体封装件及其制造方法 (Semiconductor packaging piece and manufacturing method thereof ) 是由 戴建业 刘伟 韦仕贡 张彦秀 于 2020-07-29 设计创作,主要内容包括:本发明公开一种半导体封装件及其制造方法。该半导体封装件包括:半导体芯片,其表面设有多个外接端子;引线框架,其具有多个用于与外部电路连接的管脚;连接部,其包括作为连接线路的多条引线以及用于承载多条引线的绝缘基材层,其中引线的一端与外接端子连接,另一端与管脚连接;以及封装胶体,其包覆半导体芯片、引线框架和连接部,管脚暴露于封装胶体的外侧。本发明通过连接部上的引线连接半导体芯片的外接端子与引线框架外围的管脚,即利用连接部电连接代替了金属焊线电连接,从而省略了焊线工序,解决了金属焊线焊接不良所带来产品良率低的问题。(The invention discloses a semiconductor package and a manufacturing method thereof. The semiconductor package includes: a semiconductor chip having a plurality of external terminals on a surface thereof; a lead frame having a plurality of pins for connection with an external circuit; the connecting part comprises a plurality of leads serving as connecting lines and an insulating substrate layer used for bearing the leads, wherein one ends of the leads are connected with the external terminals, and the other ends of the leads are connected with the pins; and the packaging colloid covers the semiconductor chip, the lead frame and the connecting part, and the pins are exposed to the outer side of the packaging colloid. The lead on the connecting part is connected with the external terminal of the semiconductor chip and the peripheral pin of the lead frame, namely the connecting part is electrically connected to replace a metal welding wire, so that the welding wire process is omitted, and the problem of low product yield caused by poor welding of the metal welding wire is solved.)
1. A semiconductor package, comprising:
a semiconductor chip having a plurality of external terminals on a surface thereof;
a lead frame having a plurality of pins for connection with an external circuit;
the connecting part comprises a plurality of leads serving as connecting lines and an insulating substrate layer used for bearing the leads, wherein one ends of the leads are connected with the external terminals, and the other ends of the leads are connected with the pins; and
and the packaging colloid covers the semiconductor chip, the lead frame and the connecting part, and the pins are exposed to the outer side of the packaging colloid.
2. The semiconductor package of claim 1, wherein the insulating substrate layer has first and second opposing surfaces, wherein the first surface is proximate to the semiconductor chip and the second surface is proximate to the lead frame;
the leads comprise a first lead positioned on the first surface, a second lead positioned on the second surface and a connecting wire positioned in the insulating base material layer;
one end of the first lead is connected with an external terminal of the semiconductor chip, and the other end of the first lead is connected with the connecting wire; one end of the second lead is connected with the pin of the lead frame, and the other end of the second lead is connected with the connecting wire.
3. The semiconductor package of claim 1, wherein the insulating substrate layer has first and second opposing surfaces, wherein the first surface is proximate to the semiconductor chip and the second surface is proximate to the lead frame;
one end of the lead is exposed on the first surface and connected with an external terminal of the semiconductor chip, the other end of the lead is exposed on the second surface and connected with a pin of the lead frame, and the other part of the lead is positioned in the insulating base material layer.
4. The semiconductor package part according to claim 2 or 3, wherein the second surface of the insulating substrate layer is provided with an adhesive layer, and the insulating substrate layer is attached to the surface of the lead frame through the adhesive layer.
5. The semiconductor package according to any one of claims 1 to 3, wherein both ends of the lead are provided with pads for connection with an external terminal of the semiconductor chip and a pin of the lead frame, respectively.
6. The semiconductor package according to claim 5, wherein the surface of the pad protrudes from the surface of the insulating substrate layer.
7. The semiconductor package according to any one of claims 1 to 6, wherein the connection portion is a flexible circuit board.
8. A method for manufacturing a semiconductor package, comprising the steps of:
fixing a connecting part on the surface of a lead frame, wherein the connecting part comprises a plurality of leads serving as connecting lines and an insulating substrate layer for bearing the leads;
connecting one end of the lead with an external terminal of a semiconductor chip, and connecting the other end of the lead with a pin of the lead frame;
and encapsulating the semiconductor chip, the lead frame and the connecting part by using an encapsulating colloid, and at least exposing the pin of the lead frame.
9. The method of manufacturing according to claim 8, further comprising the step of fabricating the connection portion:
forming a plurality of leads in the insulating base material layer;
and a pad for connecting an external terminal is formed at one end of the lead, and a pad for connecting a pin is formed at the other end of the lead.
10. The manufacturing method according to claim 8 or 9, wherein the connecting portion is a flexible circuit board.
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor packaging piece and a manufacturing method thereof.
Background
In a conventional semiconductor package using a lead frame as a chip carrier, such as a Quad Flat Package (QFP) and a quad flat no-lead (QFN) semiconductor package, a semiconductor chip is bonded to a lead frame having a chip pad and a plurality of pins, an external terminal on the surface of the chip is electrically connected to the pins on the lead frame through a plurality of metal bonding wires, and finally the chip and the metal bonding wires are encapsulated by an encapsulant to form the semiconductor package.
As the market demand for consumer electronics performance continues to increase, higher demands are placed on the performance of semiconductor chips and semiconductor packages. Taking medium and high-end consumer electronic products as an example, in a QFN product used by the product, the number of pins around a lead frame is basically not less than 60, and the number of metal bonding wires is basically more than 100. In the actual packaging process, the bending and poor welding of the bonding wires in the wire bonding process are important factors that lead to low yield of QFN products, and the yield of the QFN products is lower as the number of the metal bonding wires increases.
Disclosure of Invention
The invention aims to provide a semiconductor packaging piece and a manufacturing method thereof, wherein the semiconductor packaging piece can avoid the bending of a welding wire, reduce the abnormal occurrence frequency of a welding spot and improve the long-term use reliability of the semiconductor packaging piece.
According to an aspect of the present invention, there is provided a semiconductor package including: a semiconductor chip having a plurality of external terminals on a surface thereof; a lead frame having a plurality of pins for connection with an external circuit; the connecting part comprises a plurality of leads serving as connecting lines and an insulating substrate layer used for bearing the leads, wherein one ends of the leads are connected with the external terminals, and the other ends of the leads are connected with the pins; and the packaging colloid covers the semiconductor chip, the lead frame and the connecting part, and the pins are exposed to the outer side of the packaging colloid.
Further, the insulating base material layer is provided with a first surface and a second surface which are opposite, wherein the first surface is close to the semiconductor chip, and the second surface is close to the lead frame; the leads comprise a first lead positioned on the first surface, a second lead positioned on the second surface and a connecting wire positioned in the insulating base material layer; one end of the first lead is connected with an external terminal of the semiconductor chip, and the other end of the first lead is connected with the connecting wire; one end of the second lead is connected with the pin of the lead frame, and the other end of the second lead is connected with the connecting wire.
Further, the insulating base material layer is provided with a first surface and a second surface which are opposite, wherein the first surface is close to the semiconductor chip, and the second surface is close to the lead frame; one end of the lead is exposed on the first surface and connected with an external terminal of the semiconductor chip, the other end of the lead is exposed on the second surface and connected with a pin of the lead frame, and the other part of the lead is positioned in the insulating base material layer.
Further, the connecting portion is provided with a positioning point for positioning with the semiconductor chip.
Furthermore, an insulating layer for wrapping the lead is arranged on the surface of the insulating base material layer.
Furthermore, the second surface of the insulating substrate layer is provided with an adhesive layer, and the insulating substrate layer is attached to the surface of the lead frame through the adhesive layer.
Further, both ends of the lead are provided with pads for connection with an external terminal of the semiconductor chip and a pin of the lead frame, respectively.
Further, the surface of the bonding pad protrudes out of the surface of the insulating base material layer.
Further, the surface of the bonding pad is plated with nickel or tin metal.
In the semiconductor package described above, the connection portion is a flexible circuit board.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, including the steps of: fixing a connecting part on the surface of the lead frame, wherein the connecting part comprises a plurality of leads serving as connecting lines and an insulating base material layer for bearing the leads; connecting one end of a lead with an external terminal of the semiconductor chip, and connecting the other end of the lead with a pin of the lead frame; and the semiconductor chip, the lead frame and the connecting part are coated by the packaging colloid, and at least the pins of the lead frame are exposed.
Further, the method also comprises the following steps of: forming a plurality of leads in the insulating base material layer; a pad for connecting an external terminal is formed at one end of the lead, and a pad for connecting a pin is formed at the other end of the lead.
Further, the connecting portion is a flexible circuit board.
The invention has the following beneficial effects:
the semiconductor packaging piece provided by the invention adopts the lead in the connecting part to connect the external terminal of the semiconductor chip and the pin of the lead frame, namely, the connecting part is electrically connected to replace the traditional metal welding wire, so that the welding wire process is omitted, and the problem of low product yield caused by poor welding of the welding wire and the metal welding wire is solved. In addition, the connecting part is adopted to replace metal welding wire for electric connection, so that the electric connection of the connecting part can be completed through mounting, reflow soldering and other processes in the processing process.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a semiconductor package in an embodiment of the invention.
Fig. 2 is a schematic view showing a connection structure of a lead frame and a connection portion in the embodiment of the present invention.
Fig. 3 shows a cross-sectional view of a connection structure of the semiconductor chip, the connection portion, and the lead frame in the embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
As shown in fig. 1 to 3, an embodiment of the present invention provides a semiconductor package similar to a QFN package structure, which includes: a
The surface of the
The
The
The encapsulant is used to encapsulate the
In the conventional process, the
In the semiconductor package provided by the embodiment of the invention, the
In the conventional process, the electrical connection (bonding) of the metal bonding wire is mainly completed by using bonding equipment and a bonding pin (a tooling fixture of the bonding wire process) under the action of specific environment (power, pressure, time and temperature). In the welding process, the problems of infirm welding points, insufficient welding and the like often occur. The above problems are difficult to find during operation and during electrical performance testing. However, in the long-term use process of the product, the welding is not firm, and the welding spot of the cold welding falls off, so that poor contact is caused, and finally the function of the product is lost or even the product fails.
In the invention, the connecting
Specifically, the
In one embodiment, the
In this embodiment, the specific formation manner of the first lead, the second lead, and the connecting wire is not particularly limited. In one implementation, the first lead and the second lead are attached to the surface of the
In another embodiment, the
As shown in fig. 2, the connecting
In one embodiment, the surface of the connecting
In one embodiment, an adhesive layer is further disposed between the second surface of the insulating
In this embodiment, how to realize the electrical connection between the lead 32 and the
In one embodiment, the surface of the
In a preferred embodiment, the
Since the flexible circuit board has good elasticity, the flexible circuit board is used as the connecting
The invention also discloses a manufacturing method of the semiconductor packaging piece, and with reference to fig. 1 to 3, the manufacturing method comprises the following steps:
fixing a connecting
one end of the
the
In one embodiment, the method further comprises the following steps:
chip grinding and scribing: according to the product requirements, the processed wafer grinding plate is thinned to the required thickness, and then the thinned wafer is cut into single chips (die), namely the
Film pasting on the back: a protective film is attached to the back surface of the
The connecting
Chip mounting: the
This step may also be referred to as Flip Chip bonding, which belongs to Flip Chip bonding (Flip Chip), and in the specific implementation process, the electrical connection between the
Reflow soldering: the
In the specific implementation of this step, the reflow device may be used to melt and solidify the metal between the
Washing with water: and residues left during welding are cleaned by a washing machine, so that the reliability of plastic packaging is ensured.
Plastic packaging: the melted encapsulant is wrapped around the front surfaces of the
The appearance of the semiconductor product after plastic packaging is similar to that of the traditional QFN packaging product, and the back of the
In one embodiment, the method further includes a ball-mounting process, in which solder balls are fixed on the back surface of the
Further, a step of preparing the
The flexible circuit board in the embodiment generally only needs to be manufactured by a single panel, and the existing mature manufacturing process can be adopted. It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.