阅读说明：本技术 通过封装衬底中的介电材料配置设计的最佳信号布线性能 (Optimized signal routing performance through dielectric material configuration design in package substrate ) 是由 钱治国 段刚 K.艾金 孔*莹 孔莹 于 2020-03-23 设计创作，主要内容包括：通过封装衬底中的介电材料配置设计的最佳信号布线性能。实施例包括封装衬底和形成封装衬底的方法。一种封装衬底包括：在第一电介质中的第一导电层、在第一电介质上方的第二电介质、以及在第二电介质中的第二导电层,其中第二导电层包括第一迹线和第二迹线。该封装衬底还包括在第二电介质上方的第三导电层,以及在第一和第二电介质中的高介电常数(Dk)和低DK区,其中高Dk区围绕第一迹线,并且其中低Dk区围绕第二迹线。高Dk区可以处于第一导电层与第三导电层之间。低Dk区可以处于第一导电层与第三导电层之间。该封装衬底可以包括在第一和第二电介质中的介电区,其中该介电区将高Dk区和低Dk区分离。(The designed optimal signal routing performance is configured by the dielectric material in the package substrate. Embodiments include a package substrate and a method of forming a package substrate. A package substrate comprising: a first conductive layer in the first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, wherein the second conductive layer includes a first trace and a second trace. The package substrate also includes a third conductive layer over the second dielectric, and high dielectric constant (Dk) and low Dk regions in the first and second dielectrics, wherein the high Dk region surrounds the first trace, and wherein the low Dk region surrounds the second trace. The high Dk region may be between the first conductive layer and the third conductive layer. The low Dk region may be between the first conductive layer and the third conductive layer. The package substrate may include a dielectric region in the first and second dielectrics, wherein the dielectric region separates the high Dk region and the low Dk region.)

1. A package substrate, comprising:

a first conductive layer in the first dielectric;

a second dielectric over the first dielectric;

a second conductive layer in the second dielectric, wherein the second conductive layer comprises a plurality of first traces and a plurality of second traces;

a third conductive layer over the second dielectric; and

a high dielectric constant (Dk) region and a low Dk region in the first and second dielectrics, wherein the high Dk region surrounds the plurality of first traces and wherein the low Dk region surrounds the plurality of second traces.

2. The package substrate of claim 1, wherein the high Dk region is between the first conductive layer and the third conductive layer.

3. The package substrate of claim 1, wherein the high Dk region is between the first conductive layer and the third conductive layer.

4. The package substrate of claim 1, 2 or 3, further comprising a dielectric region in the first and second dielectrics, wherein the dielectric region separates the high Dk region and the low Dk region.

5. The package substrate of claim 4, wherein the high Dk region comprises a first material having a first Dk value, wherein the dielectric region comprises a second material having a second Dk value, wherein the low Dk region comprises a third material having a third Dk value, wherein the first Dk value of the high Dk region is greater than the third Dk value of the low Dk region, and wherein the second Dk values of the first and second dielectrics are between the first Dk value and the third Dk value.

6. The package substrate of claim 5, wherein the third Dk value is between 3.3 and 3.5.

7. The package substrate of claim 1, 2, or 3, wherein the plurality of first traces are a plurality of single-ended routing traces, and wherein the plurality of second traces are a plurality of differential routing traces.

8. The package substrate of claim 6, wherein a width and a line spacing of the plurality of single-ended routing traces are less than a width and a line spacing of the plurality of differential routing traces.

9. The package substrate of claim 1, 2 or 3, further comprising a plurality of vias in the first and second dielectrics, wherein the plurality of vias couple the conductive pads of the second conductive layer to the first and second conductive layers.

10. A semiconductor package, comprising:

a package substrate;

a plurality of dielectric regions in the encapsulation substrate, wherein the plurality of dielectric regions includes a high Dk region, a low Dk region, and a dielectric region; and

a die on the package substrate, wherein the die has a first edge with a first input/output (I/O) routing area, and a second edge with a second I/O routing area, wherein the first I/O routing area of the first edge is opposite the second I/O routing area of the second edge, and wherein the high Dk region comprises the first I/O routing area and the low Dk region comprises the second I/O routing area.

11. The semiconductor package of claim 10, wherein the package substrate further comprises:

a first conductive layer in the first dielectric;

a second dielectric over the first dielectric;

a second conductive layer in the second dielectric, wherein the second conductive layer comprises a plurality of first traces and a plurality of second traces, wherein the plurality of first traces are located in the first I/O routing area, and wherein the plurality of second traces are located in the second I/O routing area;

a third conductive layer over the second dielectric; and

a high Dk region and a low Dk region in the first and second dielectrics, wherein the high Dk region surrounds the plurality of first traces and wherein the low Dk region surrounds the plurality of second traces.

12. The semiconductor package of claim 11, wherein the high Dk region is between the first and third conductive layers.

13. The semiconductor package of claim 11, wherein the low Dk region is between the first conductive layer and the third conductive layer.

14. A semiconductor package according to claim 11, 12 or 13, wherein the dielectric region is in the first and second dielectrics, wherein the dielectric region separates the high Dk region and the low Dk region.

15. The semiconductor package of claim 14, wherein the high Dk region comprises a first material having a first Dk value, wherein the dielectric region comprises a second material having a second Dk value, wherein the low Dk region comprises a third material having a third Dk value, wherein the first Dk value of the high Dk region is greater than the third Dk value of the low Dk region, and wherein the second Dk values of the first and second dielectrics are between the first Dk value and the third Dk value.

16. The semiconductor package of claim 15, wherein the third Dk value is between 3.3 and 3.5.

17. The semiconductor package of claim 11, 12 or 13, wherein the plurality of first traces are a plurality of single-ended routing traces, and wherein the plurality of second traces are a plurality of differential routing traces.

18. The semiconductor package of claim 17, wherein a width and a line spacing of the plurality of single-ended routing traces are less than a width and a line spacing of the plurality of differential routing traces.

19. The semiconductor package of claim 11, 12 or 13, further comprising a plurality of vias in the first and second dielectrics, wherein the plurality of vias couple the conductive pads of the second conductive layer to the first and second conductive layers.

20. A method for forming a package substrate, comprising:

disposing a first high Dk region and a first low Dk region over the first conductive layer;

disposing a first dielectric over the first conductive layer and surrounding first high and low Dk regions;

disposing a second conductive layer over the first dielectric and the first high and low Dk regions, wherein the second conductive layer comprises a plurality of first traces and a plurality of second traces, and wherein the plurality of first traces are over the first high Dk region and the plurality of second traces are over the first low Dk region;

disposing a second high Dk region directly over the first high Dk region and the plurality of first traces, and disposing a second low Dk region directly over the first low Dk region and the plurality of second traces;

disposing a second dielectric over the second conductive layer and surrounding second high and low Dk regions; and

disposing a third conductive layer over the second dielectric and second high and low Dk regions, wherein the first and second high Dk regions completely surround the plurality of first traces, and wherein the first and second low Dk regions completely surround the plurality of second traces.

21. The method of claim 20, wherein the first and second high Dk regions are between the first conductive layer and the third conductive layer, and wherein the first and second low Dk regions are between the first conductive layer and the third conductive layer.

22. The method of claim 20 or 21, further comprising:

a dielectric region in the first and second dielectrics, wherein the dielectric region separates the first and second high Dk regions from the first and second low Dk regions; and

a plurality of vias in the first and second dielectrics, wherein the plurality of vias couple the conductive pads of the second conductive layer to the first and second conductive layers.

23. The method of claim 22, wherein the first and second high Dk regions comprise a first material having a first Dk value, wherein the dielectric region comprises a second material having a second Dk value, wherein the first and second low Dk regions comprise a third material having a third Dk value, wherein the first Dk value of the first and second high Dk regions is greater than the third Dk value of the first and second low Dk regions, wherein the second Dk value of the first and second dielectrics is between the first Dk value and the third Dk value, and wherein the third Dk value is between 3.3 and 3.5.

24. The method of claim 22, wherein the plurality of first traces are a plurality of single-ended routing traces, wherein the plurality of second traces are a plurality of differential routing traces, and wherein a width and a line spacing of the plurality of single-ended routing traces are less than a width and a line spacing of the plurality of differential routing traces.

25. The method of claim 20 or 21, wherein providing the first and second high and low Dk regions is accomplished with a pick and place process or a stack of photoimageable dielectrics.

Technical Field

Background

Scaling of features in Integrated Circuits (ICs) has been a driving force behind the evolving semiconductor industry over the last few decades. Scaling to smaller and smaller features enables increased functional unit density to be achieved over the limited real estate (real) of semiconductor devices. However, the drive to scale these ICs (including the package substrate) while optimizing the performance of each device is not without problems.

Drawings

The embodiments described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar features. Furthermore, some conventional details have been omitted so as not to obscure the inventive concepts described herein.

Fig. 1 is an illustration of a plan view and a cross-sectional view of a semiconductor package having a package substrate including a single-ended input/output (I/O) interface, a differential I/O interface, and a plurality of permittivity (Dk) regions within a dielectric, in accordance with an embodiment.

Fig. 2A-2C are illustrations of perspective views of a process flow to form a semiconductor package having a package substrate including a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric, according to some embodiments.

Fig. 3A-3D are illustrations of cross-sectional views of a process flow of forming a semiconductor package with a package substrate including a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric using pick and place methods, according to some embodiments.

Fig. 4A-4G are illustrations of cross-sectional views of a process flow to form a semiconductor package having a package substrate including a single-ended I/O interface, a differential I/O interface, a photoimageable dielectric, and a plurality of Dk regions within the dielectric, in accordance with some embodiments.

Fig. 5 is a diagram illustrating a schematic block diagram of a computer system utilizing a semiconductor package having a package substrate including a single-ended I/O interface, a differential I/O interface, and a plurality of Dk regions within a dielectric, according to one embodiment.

Embodiments relate to packaging semiconductor devices. More particularly, embodiments relate to semiconductor devices having regions of different dielectric constants (Dk) within a single dielectric layer.