Flip chip package
阅读说明:本技术 倒装芯片封装 (Flip chip package ) 是由 郑百盛 杜文杰 于 2019-05-09 设计创作,主要内容包括:一种倒装芯片封装,包括一基板、接合在基板上的一芯片本体以及连接于芯片本体与基板之间的多个凸块。基板包括多个输入导线以及多个输出导线。芯片本体包括第一封装单元以及第二封装单元。第一封装单元包括第一封环以及多个第一焊垫,第二封装单元包括第二封环以及多个第二焊垫,芯片本体在第一封环与第二封环之间连续地延伸。各输入导线具有与芯片本体重叠的一端以及位于基板的一第一接合区域的另一端,各输出导线具有与芯片本体重叠的一端以及位于基板的一第二接合区域的另一端。第一接合区域以及第二接合区域位于芯片本体的相对侧。(A flip chip package includes a substrate, a chip body bonded on the substrate, and a plurality of bumps connected between the chip body and the substrate. The substrate includes a plurality of input conductive lines and a plurality of output conductive lines. The chip body comprises a first packaging unit and a second packaging unit. The first packaging unit comprises a first sealing ring and a plurality of first welding pads, the second packaging unit comprises a second sealing ring and a plurality of second welding pads, and the chip body continuously extends between the first sealing ring and the second sealing ring. Each input lead has one end overlapped with the chip body and the other end positioned in a first bonding area of the substrate, and each output lead has one end overlapped with the chip body and the other end positioned in a second bonding area of the substrate. The first bonding region and the second bonding region are located on opposite sides of the chip body.)
1. A flip chip package comprising:
a substrate including a plurality of input conductive lines and a plurality of output conductive lines;
a chip body bonded on the substrate, wherein the chip body comprises a first packaging unit and a second packaging unit, the first packaging unit comprises a first seal ring and a plurality of first welding pads positioned in an area surrounded by the first seal ring, the second packaging unit comprises a second seal ring and a plurality of second welding pads positioned in an area surrounded by the second seal ring, and the chip body continuously extends between the first seal ring and the second seal ring; and
a plurality of bumps connected between the chip body and the substrate,
each input lead has one end overlapped with the chip body and the other end located in a first bonding area of the substrate, each output lead has one end overlapped with the chip body and the other end located in a second bonding area of the substrate, and the first bonding area and the second bonding area are located on opposite sides of the chip body.
2. The flip chip package of claim 1, wherein the first bonding pads are arranged in a ring-shaped path, the ring-shaped path being located in the region surrounded by the first seal ring.
3. The flip chip package of claim 1, wherein the first bonding pads are disposed in an annular path surrounded by the second seal ring.
4. The flip chip package of claim 1, wherein one of the bumps is an interconnection bump extending between the first package unit and the second package unit, one end of the interconnection bump being connected to one of the first pads, the other end of the interconnection bump being connected to one of the second pads.
5. The flip chip package of claim 1, wherein the substrate further comprises an interconnection lead connected to a first one of the first pads and a second one of the second pads.
6. The flip chip package of claim 1, wherein the first seal ring and the second seal ring are separated by a distance between 50 microns and 200 microns.
7. The flip chip package of claim 1, wherein the first pads comprise a plurality of first input pads, the second pads comprise a plurality of second input pads, the first input pads are respectively connected to input wires of one portion of the input wires, and the second input pads are respectively connected to input wires of another portion of the input wires.
8. The flip chip package of claim 7, wherein a first pad of the first pads is a first dummy pad, the first dummy pad being closer to the second seal ring than the first input pads, and a second pad of the second pads is a second dummy pad, the second dummy pad being closer to the first seal ring than the second input pads.
9. The flip chip package of claim 1, wherein the length of the chip body is between 28 millimeters and 66 millimeters.
10. The flip chip package of claim 1, wherein a distance between a first pad of the first pads farthest from the second seal ring and a second pad of the second pads farthest from the first seal ring is between 27 mm and 65 mm.
11. The flip chip package of claim 1, wherein a distance between a first pad of the first pads closest to the second seal ring and a second pad of the second pads closest to the first seal ring is between 55 microns and 1000 microns.
12. The flip chip package of claim 1, wherein the chip body further comprises a peripheral circuit between the first seal ring and the second seal ring.
13. A flip chip package comprising:
a substrate including a plurality of input conductive lines and a plurality of output conductive lines;
a chip body bonded on the substrate, wherein the chip body comprises a first packaging unit and a second packaging unit, the first packaging unit comprises a plurality of first bonding pads arranged in a first annular path, the second packaging unit comprises a plurality of second bonding pads arranged in a second annular path, and the distance between a first bonding pad closest to the second bonding pads in the first bonding pads and a second bonding pad closest to the first bonding pads in the second bonding pads is between 55 micrometers and 1000 micrometers; and
a plurality of bumps connected between the chip body and the substrate,
each input lead has one end overlapped with the chip body and the other end located in a first bonding area of the substrate, each output lead has one end overlapped with the chip body and the other end located in a second bonding area of the substrate, and the first bonding area and the second bonding area are located on opposite sides of the chip body.
14. The flip chip package of claim 13, wherein one of the bumps is an interconnect bump extending between the first package unit and the second package unit, one end of the interconnect bump being connected to one of the first pads, the other end of the interconnect bump being connected to one of the second pads.
15. The flip chip package of claim 13, wherein the substrate further comprises an interconnection lead, one end of the interconnection lead is connected to one of the first pads, and the other end of the interconnection lead is connected to one of the second pads.
16. The flip chip package of claim 13, wherein the length of the chip body is between 28 millimeters and 66 millimeters.
17. The flip chip package of claim 13, wherein a distance between a first one of the first pads furthest from the second pads and a second one of the second pads furthest from the first pads is between 27 mm and 65 mm.
18. The flip chip package of claim 13, wherein the chip body further comprises a peripheral circuit located in a region between the first pads and the second pads.
19. The flip chip package of claim 13, wherein the first pads comprise a plurality of first input pads, the second pads comprise a plurality of second input pads, the first input pads are respectively connected to input wires of one portion of the input wires, and the second input pads are respectively connected to input wires of another portion of the input wires.
20. The flip chip package of claim 19, wherein a first pad of the first pads is a first dummy pad that is closer to the second pads than the first input pads, and a second pad of the second pads is a second dummy pad that is closer to the first pads than the second input pads.
[ technical field ] A method for producing a semiconductor device
The present invention relates to a semiconductor package, and more particularly, to a flip chip package.
[ background of the invention ]
In High resolution electronic device applications, a High Output Pin Count (High Output Pin Count) Integrated Circuit (IC) chip is increasingly required. Among various packaging technologies, Flip Chip Bonding (Flip Chip Bonding) Technology is often used for high output pin count integrated circuit chips, because the Flip Chip Bonding Technology utilizes solder/gold/copper stud bumps (Cu pillar bumps) disposed on the active surface of the Chip to facilitate a large number of contacts and a high contact density on the Chip package. Solder/gold/copper pillar bumps may provide a shorter transmission path between the chip and the carrier substrate (carrier substrate) compared to wire-bonding technology to provide the desired performance.
However, the contact density of an integrated circuit chip is not easily changed due to the limitations of process limitations and manufacturing costs. Chip packaging techniques still need to be improved in order to provide higher output pin counts in small volume packages.
[ summary of the invention ]
The present invention provides a flip chip package (flip chip) having a high output pin count and a small volume.
The flip chip package comprises a substrate, a chip body bonded on the substrate, and a plurality of bumps connected between the chip body and the substrate. The substrate includes a plurality of input conductive lines and a plurality of output conductive lines. The chip body comprises a first packaging unit and a second packaging unit. The first packaging unit comprises a first sealing ring and a plurality of first welding pads positioned in an area surrounded by the first sealing ring, and the second packaging unit comprises a second sealing ring and a plurality of second welding pads positioned in an area surrounded by the second sealing ring. The chip body extends continuously between the first seal ring and the second seal ring. Each input lead is provided with one end overlapped with the chip body and the other end positioned in a first bonding area of the substrate, and each output lead is provided with one end overlapped with the chip body and the other end positioned in a second bonding area of the substrate. The first bonding region and the second bonding region are located on opposite sides of the chip body.
In an embodiment of the invention, the first pads are disposed in a ring-shaped path, and the ring-shaped path is located in the region surrounded by the first seal ring.
In an embodiment of the invention, the first bonding pads are disposed in a loop path surrounded by the second seal ring.
The flip chip package comprises a substrate, a chip body bonded on the substrate, and a plurality of bumps connected between the chip body and the substrate. The substrate includes a plurality of input conductive lines and a plurality of output conductive lines. The chip body comprises a first packaging unit and a second packaging unit. The first packaging unit comprises a plurality of first welding pads arranged in a first annular path, and the second packaging unit comprises a plurality of second welding pads arranged in a second annular path. The distance between a first pad of the first pads closest to the second pads and a second pad of the second pads closest to the first pads is between 55 microns and 1000 microns. Each input lead is provided with one end overlapped with the chip body and the other end positioned in a first bonding area of the substrate, and each output lead is provided with one end overlapped with the chip body and the other end positioned in a second bonding area of the substrate. The first bonding region and the second bonding region are located on opposite sides of the chip body.
In an embodiment of the invention, the bumps include an interconnection bump extending between the first package unit and the second package unit, one end of the interconnection bump is connected to one of the first pads, and the other end of the interconnection bump is connected to one of the second pads.
In an embodiment of the invention, the substrate further includes an interconnection wire, one end of the interconnection wire is connected to one of the first pads, and the other end of the interconnection wire is connected to one of the second pads.
In an embodiment of the present invention, the first seal ring and the second seal ring are separated by a distance between 50 microns and 200 microns.
In an embodiment of the invention, the first pads include a plurality of first input pads, the second pads include a plurality of second input pads, the first input pads are respectively connected to one portion of the input wires, and the second input pads are respectively connected to another portion of the input wires.
In an embodiment of the invention, a first pad of the first pads is a first dummy pad, the first dummy pad is closer to the second seal ring than the first input pads, a second pad of the second pads is a second dummy pad, and the second dummy pad is closer to the first seal ring than the second input pads.
In an embodiment of the invention, the length of the chip body is between 28 mm and 66 mm.
In an embodiment of the invention, a distance between a first pad of the first pads farthest from the second seal ring and a second pad of the second pads farthest from the first seal ring is between 27 mm and 65 mm.
In an embodiment of the invention, a distance between a first pad of the first pads closest to the second seal ring and a second pad of the second pads closest to the first seal ring is between 55 micrometers and 1000 micrometers.
In an embodiment of the invention, the chip body further includes a peripheral circuit located between the first seal ring and the second seal ring.
Based on the above, the single chip body in the flip chip package of the embodiment of the invention includes more than one package unit to provide higher contact density of the flip chip package without excessively expanding the volume of the flip chip package. Accordingly, the flip chip package of the embodiments of the invention can provide a high output pin count in a small volume.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
[ description of the drawings ]
Fig. 1 is a schematic cross-sectional view of a flip-chip package according to an embodiment of the invention.
Fig. 2 is a schematic plan view of a flip chip package according to an embodiment of the invention.
Fig. 3 is a schematic plan view of a flip chip package according to another embodiment of the invention.
Fig. 4 is a schematic plan view of a flip chip package according to another embodiment of the invention.
Fig. 5 is a partial schematic plan view of a flip chip package according to another embodiment of the invention.
Fig. 6 is a schematic plan view of a flip chip package according to another embodiment of the invention.
[ notation ] to show
100. 200, 300, 400, 500, 600: flip chip package
110. 210, 310: substrate
112: conducting wire
120. 220, 620: chip body
120A, 220A, 620A: first packaging unit
120B, 220B, 620B: second packaging unit
120S: active surface
122A: first semiconductor assembly
122B: second semiconductor component
124A, 224Ax, 624A, 624 Ay: first bonding pad
124B, 224B, 624B, 224Bx, 624 By: second bonding pad
130: bump
212A, 312A: input conductor
212B, 312B: output conductor
216: interconnection wire
226. 626: peripheral circuit
432: interconnection bump
B1: first bonding region
B2: second bonding region
d1, d2, d 3: distance between two adjacent plates
DPA: first dummy pad
DPB: second virtual solder pad
IPA: first input pad
IPB: second input pad
L220: length of
OPA: first output pad
OPB: second output pad
PR 1: a first annular path
PR 2: second loop path
R1, R2, CR: region(s)
S1: first side
S2: second side
SR 1: first seal ring
SR 2: second seal ring
WSR: width of
[ detailed description ] embodiments
Fig. 1 is a schematic cross-sectional view of a flip chip package (flip chip package) according to an embodiment of the invention. Referring to fig. 1, a flip chip package 100 may include a substrate 110, a chip body 120 bonded to the substrate 110, and a plurality of bumps (bumps) 130. The chip body 120 is bonded to the substrate 110 by the bump 130, and an active surface (active surface)120S of the chip body 120 faces the substrate 110. The bumps 130 may be gold bumps, solder bumps, copper bumps, or other similar metal bumps. The chip body 120 may be electrically connected to the substrate 110 through the bump 130 by an eutectic bonding (epitaxial bonding) method, an Anisotropic Conductive Film (ACF) bonding method, or a surface-mount technology (SMT) reflow method. The substrate 110 may be a Flexible Printed Circuit (FPC) Film, a Ball Grid Array (BGA) substrate, a Chip On Film (COF) Tape (Tape), or a Chip On Glass (COG) Glass substrate, and includes a plurality of conductive lines 112 formed thereon. The chip body 120 may include a first package unit 120A and a second package unit 120B.
The first package unit 120A includes a first semiconductor device 122A and a plurality of first pads (pads) 124A for providing an electrical transmission path for the first semiconductor device 122A. The second packaging unit 120B includes a second semiconductor device 122B and a plurality of second pads 124B for providing an electrical transmission path for the second semiconductor device 122B. The first semiconductor device 122A and the second semiconductor device 122B may be, for example, dies (die) having corresponding circuit layouts, respectively. Specifically, the first package unit 120A and the second package unit 120B are packaged (encapsulated) and singulated (singulated) to form a single chip body 120.
The first bonding pad 124A and the second bonding pad 124B are respectively connected to the bump 130, so that the first semiconductor device 122A and the second semiconductor device 122B can be electrically connected to the conductive wire 112 through the first bonding pad 124A, the second bonding pad 124B and the bump 130. The cross-section of the flip chip package 100 shown in fig. 1 may be used to illustrate the arrangement of the semiconductor elements, the pads, the bumps, and the wires, but the present invention is not limited thereto. In other embodiments, the flip chip package may include other components not illustrated in fig. 1.
Fig. 2 is a schematic plan view of a flip chip package according to an embodiment of the invention. In fig. 2, the
As shown in fig. 2, the
Specifically, the plan view of the flip chip package shown in fig. 2 may be taken as an example of the plan layout of the flip chip package 100 of fig. 1. Specifically, the input
Although fig. 2 does not illustrate a semiconductor device, the
In the process of manufacturing the
In the present embodiment, the length L220 of the
In addition, the
The
Compared to a package body including a single package unit, the
Fig. 3 is a schematic plan view of a flip chip package according to another embodiment of the invention. In the embodiment of fig. 3, the flip chip package 300 may include a substrate 310, a
Specifically, in the present embodiment, all of the input wires 312A extend from the first side S1 of the
Similar to the
The
Fig. 4 is a schematic plan view of a flip chip package according to another embodiment of the invention. In the embodiment of fig. 4, the flip chip package 400 is similar to the
Fig. 5 is a partial schematic plan view of a flip chip package according to another embodiment of the invention. In the embodiment of fig. 5, the flip chip package 500 is similar to the
Fig. 6 is a schematic plan view of a flip chip package according to another embodiment of the invention. In the embodiment of fig. 6. The
In the present embodiment, the
One end of each
In addition, the
In summary, the flip chip packaged chip body of the embodiment of the invention has two or more package units packaged in a single package, so as to provide more output channels and facilitate the application of high resolution electronic devices. The flip chip package according to the embodiment of the present invention may be manufactured through a bonding process, so that the manufacturing of the flip chip package may be simplified for a single chip body having a plurality of package units. In addition, the single chip body of the embodiment of the invention integrally comprises two packaging units, thereby facilitating the size miniaturization.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
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