阅读说明：本技术 半导体装置及半导体装置的制造方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 竹本康男 于 2019-08-28 设计创作，主要内容包括：本发明涉及一种半导体装置及半导体装置的制造方法。根据一个实施方式,实施方式的半导体装置(100)具备：第一布线层(1),具有第一面、及与第一面对向的第二面；第一半导体元件(2),搭载于第一布线层(1)的第一面侧；导电性柱(3),设置于第一布线层(1)的第一面侧,具有第一半导体元件(2)的厚度以上的高度；第二布线层(5),具有第三面、及与第三面对向的第四面,设置于导电性柱(3)上,且在第四面侧接合于导电性柱(3)；第二半导体元件(6),搭载于第二布线层(5)的第三面侧,通过第一接合线(7)与第二布线层(5)连接；第一密封材(4),将第一布线层(1)的第一面、第一半导体元件(2)、导电性柱(3)及第二布线层(5)的第四面密封；及第二密封材(8),将第二布线层(5)的第三面、第二半导体元件(6)及第一接合线(7)密封。(The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. According to one embodiment, a semiconductor device (100) includes: a first wiring layer (1) having a first surface and a second surface facing the first surface; a first semiconductor element (2) mounted on the first surface side of the first wiring layer (1); a conductive post (3) provided on the first surface side of the first wiring layer (1) and having a height equal to or greater than the thickness of the first semiconductor element (2); a second wiring layer (5) having a third surface and a fourth surface facing the third surface, provided on the conductive pillar (3), and bonded to the conductive pillar (3) on the fourth surface side; a second semiconductor element (6) mounted on the third surface side of the second wiring layer (5) and connected to the second wiring layer (5) by a first bonding wire (7); a first sealing material (4) which seals the first surface of the first wiring layer (1), the first semiconductor element (2), the conductive post (3), and the fourth surface of the second wiring layer (5); and a second sealing material (8) for sealing the third surface of the second wiring layer (5), the second semiconductor element (6), and the first bonding wire (7).)

1. A semiconductor device includes: a first wiring layer having a first surface and a second surface opposed to the first surface; a first semiconductor element mounted on the first surface side of the first wiring layer; a conductive pillar provided on the first surface side of the first wiring layer and having a height equal to or greater than the thickness of the first semiconductor element; a second wiring layer having a third surface and a fourth surface facing the third surface, provided on the conductive pillar, and bonded to the conductive pillar on the fourth surface side; a second semiconductor element mounted on the third surface side of the second wiring layer and connected to the second wiring layer by a first bonding wire; a first sealing material sealing a first surface of the first wiring layer, the first semiconductor element, the conductive pillar, and a fourth surface of the second wiring layer; and a second sealing material sealing a third surface of the second wiring layer, the second semiconductor element, and the first bonding wire.

2. The semiconductor device according to claim 1, wherein the first semiconductor element is a controller element and the second semiconductor element is a memory element.

3. The semiconductor device according to claim 2, further comprising a memory element in which 1 or more third semiconductor elements are mounted on the second semiconductor element; and the second semiconductor element and the third semiconductor element are connected by a second bonding wire.

4. The semiconductor device according to claim 2, further comprising a memory element which is a fourth semiconductor element mounted on the third surface of the second wiring layer; and the fourth semiconductor element and the second wiring layer are connected by a third bonding wire.

5. A method of manufacturing a semiconductor device, comprising:

a first step of providing a first wiring layer, a first semiconductor element, a conductive pillar, and a first sealing material on a glass substrate; a second step of forming a second wiring layer, a second semiconductor element, a first bonding wire, and a second sealing material on the first sealing material after the first step; and a step of, after the second step, peeling the substrate and forming an electrode portion on the peeled surface of the substrate.

Technical Field

The embodiments described herein all relate to a semiconductor device and a method for manufacturing the semiconductor device.

Background

Various package layouts are studied for semiconductor devices using nonvolatile memory chips. Semiconductor devices of nonvolatile memories are required to have characteristics such as large capacity, miniaturization, and high speed of reading and writing.

Disclosure of Invention

Embodiments of the invention provide a semiconductor device and a method for manufacturing the semiconductor device, which can realize miniaturization and thinning.

According to an embodiment, a semiconductor device and a method for manufacturing the semiconductor device includes: a first wiring layer having a first surface and a second surface opposed to the first surface; a first semiconductor element mounted on the first surface side of the first wiring layer; a conductive pillar provided on the first surface side of the first wiring layer and having a height equal to or greater than the thickness of the first semiconductor element; a second wiring layer having a third surface and a fourth surface facing the third surface, provided on the conductive pillar, and bonded to the conductive pillar on the fourth surface side; a second semiconductor element mounted on the third surface side of the second wiring layer and connected to the second wiring layer via a first bonding wire; a first sealing material sealing a first surface of the first wiring layer, the first semiconductor element, the conductive pillar, and a fourth surface of the second wiring layer; and a second sealing material sealing the third surface of the second wiring layer, the second semiconductor element, and the first bonding wire.

According to the above configuration, a semiconductor device and a method for manufacturing the semiconductor device can be provided, which can be reduced in size and thickness.

Drawings

Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment.

Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment.

Fig. 3 is a step diagram of a semiconductor device according to an embodiment.

Fig. 4 is a step diagram of a semiconductor device according to an embodiment.

Fig. 5 is a step diagram of a semiconductor device according to an embodiment.

Fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment.

Fig. 7 is a step diagram of a semiconductor device according to an embodiment.

Fig. 8 is a step diagram of a semiconductor device according to an embodiment.

Fig. 9 is a cross-sectional view of a semiconductor device of an embodiment.

Fig. 10 is a cross-sectional view of a semiconductor device of an embodiment.

Fig. 11 is a sectional view of a semiconductor device of an embodiment.

Detailed Description

The following describes embodiments with reference to the drawings.

In the present specification, a plurality of expressions are given to a plurality of elements. These expressions are merely exemplary in nature, and do not deny the fact that the elements are expressed by other expressions. Elements not denoted by a plurality of expressions may be expressed by other expressions.

The drawings are schematic, and the relationship between the thickness and the planar size, the ratio of the thicknesses of the respective layers, and the like may be different from actual ones. In addition, the drawings may include portions having different dimensional relationships or ratios from each other.

(first embodiment) fig. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 is a semiconductor package. More specifically, the semiconductor device 100 is integrally formed of a single BGA type package of semiconductor elements of different types, which are so-called BGA-SSD (Ball grid array-Solid State Drive), for example.

The semiconductor device 100 of fig. 1 includes a first wiring layer 1, a first semiconductor element 2, a conductive pillar 3, a first sealing material 4, a second wiring layer 5, a second semiconductor element 6, a first bonding wire 7, a second sealing material 8, and an electrode portion 9.

The first wiring layer 1 is provided in the semiconductor device 100, and holds the first semiconductor element 2 and the like. The first wiring layer 1 is a so-called rewiring layer. The first wiring layer 1 includes a wiring made of a conductive member such as Cu in the resin layer. The first wiring layer 1 has a first surface and a second surface opposed to the first surface. The first surface of the first wiring layer 1 is a surface on which the first semiconductor element 2 is mounted. On the first surface of the first wiring layer 1, a conductive post 3 is also formed. The first semiconductor element 2 and the conductive post are electrically connected to the wiring of the first wiring layer 1 by being directly connected to each other. The first surface of the first wiring layer 1 is sealed with a sealing material 4. Further, a pad portion connected to the conductive pillar 3 and a pad portion connected to the first semiconductor element 2 are provided on the first surface of the first wiring layer 1, and an electrode portion 9 composed of a plurality of hemispherical electrodes is provided on the second surface. In the case of LGA (land Grid Array), the electrode portion may be a flat electrode, and any kind of electrode may be used as long as it can be electrically connected to the outside of the semiconductor device 100.

The first semiconductor element 2 is mounted on the first surface side of the first wiring layer 1. The first semiconductor element 2 is disposed between the first wiring layer 1 and the second wiring layer 5. The first semiconductor element 2 is a so-called flip chip, and the first semiconductor element 2 has a bump electrode on the first surface side of the first wiring layer 1, and the bump electrode is connected to a pad portion formed on the wiring of the first wiring layer 1. The first semiconductor element 2 is, for example, a controller element that controls the second semiconductor element 6.

The conductive pillar 3 is a wiring connecting the first wiring layer 1 and the second wiring layer 5. The conductive pillar 3 is disposed between the first wiring layer 1 and the second wiring layer 5, and is directly connected to both the first wiring layer 1 and the second wiring layer 5. As shown in fig. 1, at least 2 or more conductive pillars 3 are included in the semiconductor device 100, and the first semiconductor element 2 is located between the conductive pillars 3. The conductive pillar 3 is joined to the first surface side wiring of the first wiring layer 1 and to the fourth surface of the second wiring layer 5. The conductive pillars 3 are made of a conductive metal such as Cu. The height of the conductive pillar 3 (the distance from the first wiring layer 1 to the second wiring layer 5) is equal to or greater than the thickness of the first semiconductor element. When the wiring of the first wiring layer 1 is composed of Cu and the conductive pillar 3 is composed of Cu, Cu is bonded to each other.

The first sealing material 4 seals the first surface of the first wiring layer 1, the first semiconductor element 2, the conductive post 3, and the fourth surface of the second wiring layer 5 facing the first wiring layer 1. The first sealing material 4 is, for example, a mold resin.

The second wiring layer 5 is provided in the semiconductor device 100 and holds the second semiconductor element 6 and the like. The second wiring layer 5 is a so-called rewiring layer. The second wiring layer 5 connects the first semiconductor element 2 and the second semiconductor element 6 via the conductive pillar 3 and the first bonding wire 7. The second wiring layer 5 also has a structure in which wiring is formed in the resin layer, as in the first wiring layer 1. The second wiring layer 5 has a third surface and a fourth surface facing the third surface. On the third surface side of the second wiring layer 5, a second semiconductor element 6 is mounted. The fourth surface side of the second wiring layer 5 is bonded to the conductive post 3.

By directly connecting the second wiring layer 5 and the conductive pillars 3 without via solder balls or the like, the height can be reduced by the amount corresponding to the bonding members such as solder balls. In the case where the first semiconductor element side and the second semiconductor element side are fabricated as respective sub-packages, and then the sub-packages are bonded, for example, a glass epoxy substrate is used for at least any one of the sub-packages from the viewpoint of strength. If an inorganic wiring substrate such as a glass epoxy substrate is not used for all the sub-packages, the strength is insufficient when the sub-packages are manufactured or the strength is insufficient when the sub-packages are bonded. Therefore, if an inorganic wiring layer such as a glass epoxy substrate is not used, it is not practical to bond the sub-packages to obtain 1 package. Since the semiconductor device 100 according to the embodiment is not obtained by bonding the sub-package, no gap is generated between the second wiring layer 5 and the first sealing material 4.

The second wiring layer 5 and the first sealing material 4 covering the first semiconductor element 2 are arranged in 1 straight line in the stacking direction of the layers. The second sealing material sealing the first wiring layer 1 and the second semiconductor element 5 is arranged in a 1-line arrangement in the stacking direction of the layers.

The second semiconductor element 6 is mounted on the third surface side of the second wiring layer 5. The electrode pads provided on the surface of the second semiconductor element 6 facing the second wiring layer 5 on the side facing toward are connected to the second wiring layer 5. The second semiconductor element 6 is located between the second wiring layer 5 and the second sealing material 8. The second semiconductor element 6 is fixed by an adhesive layer such as a die bond film provided on the second wiring layer 5, for example. The second semiconductor element 6 and the second wiring layer 5 are connected by a first bonding wire 7. The second semiconductor element 6 is, for example, a memory element. The memory element may be a nonvolatile memory element or a combination of a nonvolatile memory element and a volatile memory element. As the nonvolatile memory element, a NAND memory chip, a phase change memory chip, a resistance change memory chip, a ferroelectric memory chip, a magnetic memory chip, or the like can be used. As the volatile Memory element, a DRAM (Dynamic Random Access Memory) chip or the like can be used.

The first bonding wire 7 is a wire connecting the second wiring layer 5 and the second semiconductor element 6. The first bonding wire 7 is connected to the wiring of the second wiring layer 5. The first bonding wire 7 is, for example, a wire of Au or the like.

The second sealing material 8 seals the third surface of the second wiring layer 5, the second semiconductor element 6, and the first bonding wire 7. The second sealing material 8 is, for example, a mold resin.

The electrode portion 9 is an electrode provided on the second surface side of the first wiring layer 1. The electrode portion 9 is, for example, a ball pad electrode.

Next, a method for manufacturing the semiconductor device 100 will be described. In the description of the manufacturing method, reference will be made to a part of the step diagrams. The method of manufacturing the semiconductor device 100 includes: a first step of providing a first wiring layer 1, a first semiconductor element 2, a conductive post 3, and a first sealing material 4 on a substrate; a second step of forming a second wiring layer 5, a second semiconductor element 6, a first bonding wire 7, and a second sealing material 8 on the first sealing material 4 after the first step; and a step of, after the second step, peeling the glass substrate and forming an electrode portion 9 on the peeled surface of the substrate.

Fig. 2 is a flowchart illustrating a method of manufacturing the semiconductor device 100. The manufacturing method shown in the flowchart of fig. 2 is an example of a manufacturing method of the semiconductor device 100. As shown in fig. 2, the method of manufacturing the semiconductor device 100 more specifically includes the following steps: forming a first wiring layer 1 on a substrate 10; providing a first semiconductor element 2 on the first wiring layer 1; forming a first sealant 4; forming a hole H in the first sealing material 4; embedding a conductive material into the hole H; carrying out planarization treatment; forming a second wiring layer 5 on the first sealing material 4; a second semiconductor element 6 is provided on the second wiring layer 5, and wiring is performed by wire bonding; forming a second sealant 8; the substrate 10 is peeled off by reversing the substrate to form the electrode portion 9.

First, a first wiring layer 1 is formed on a substrate 10. A wiring member is formed on the substrate 10, and patterning is performed to form a resin layer. The resin layer is further patterned to further form a conductive member, and patterning processing and the like are performed, thereby obtaining the first wiring layer 1. As a material of the wiring member, Al or Cu can be used. The wiring may be formed by sputtering or plating. The resin layer may be made of photosensitive polyimide or the like. A pad portion to be connected to the first semiconductor element 2 and a pad portion to be connected to the conductive post 3 are formed in the first wiring layer 1. Then, the first semiconductor element 2 manufactured by another process is disposed on the first surface of the first wiring layer 1, and the pad portion of the first wiring layer 1 and the bump electrode of the first semiconductor element 2 are connected by flip chip. Then, the first surface of the first wiring layer 1 and the first semiconductor element 2 are sealed with the first sealing material 4, and a hole H is formed in the first sealing material 4 by laser processing, dry etching processing, or the like, thereby obtaining a member shown in the step diagram of fig. 3.

Then, a conductive material as a material of the conductive pillar 3 is embedded in the hole H of the member shown in the step diagram of fig. 3, and the conductive pillar 3 and the first sealing material 4 are planarized, thereby obtaining the member shown in the step diagram of fig. 4. In this case, the conductive posts 3 may be formed by plating, or the conductive posts 3 may be formed by embedding a conductive material in the holes by screen printing, ink jet, or the like. After the planarization treatment, the conductive material in the hole H becomes the conductive pillar 3. The conductive material is buried, and the conductive pillar 3 is electrically connected to the first wiring layer 1. More specifically, the wiring material of the first wiring layer 1 is bonded to the conductive post 3.

Further, the planarization process may not be performed, and for example, the conductive pillar 3 may slightly protrude or be recessed from the first sealing material 4. In the next step of forming the second wiring layer 5, it is sufficient if the conductive pillars 3 and the wirings of the second wiring layer 5 can be electrically connected.

Then, a second wiring layer 5 is formed on the first sealing material 4 of the member shown in the step diagram of fig. 4, and the conductive pillar 3 is electrically connected to the second wiring layer 5. A wiring member is formed on the conductive pillar 3 and the first sealing material 4, and a resin layer is formed by patterning. The resin layer is further patterned to further form a conductive member, and patterning processing and the like are performed, thereby obtaining the second wiring layer 5. As a material of the wiring member, Al or Cu can be used. The wiring may be formed by sputtering or plating. The resin layer may be made of photosensitive polyimide or the like. On the third surface of the second wiring layer 5, a pad portion to be connected to a pad formed on the second semiconductor element 6 is formed, and on the fourth surface, a pad portion to be connected to the conductive pillar 3 is formed. Then, the second semiconductor element 6 is provided on the second wiring layer 5, and the pad portion of the second semiconductor element 6 and the pad portion of the second wiring layer 5 are connected by the first bonding wire 7. The second wiring layer 5 and the second semiconductor element 6 may be bonded by an adhesive film such as a die bond film, or may be bonded by a liquid adhesive or the like.

Then, the third surface of the second wiring layer 5, the second semiconductor element 6, and the first bonding wire 7 are sealed with the second sealing material 8, and are optionally subjected to planarization processing. Then, as shown in the step diagram of fig. 5, the substrate 10 is peeled off. The resulting member may be reversed before and after the substrate 10 is peeled off. Then, hemispherical electrode portions 9 are formed at the surface of the first wiring layer 1 from which the substrate 10 has been peeled off, whereby the semiconductor device 100 of fig. 1 is obtained.

The substrate 10 is not particularly limited as long as it has sufficient strength in the process, and typically, a glass plate may be used. In addition, silicon may be used. In addition, a peeling agent may be applied in advance on the substrate 10 so as to easily peel the first wiring layer 1 from the substrate 10. Before the first wiring layer 1 is formed on the substrate 10, a peeling layer having high light absorption may be formed. In this case, the substrate 10 may have, for example, a light-transmitting property, and when the substrate 10 is peeled, the peeling layer may be peeled by thermal decomposition by irradiating the substrate 10 with laser light.

An example of another manufacturing method of the semiconductor device 100 will be described with reference to the flowchart of fig. 6 and the step diagrams of fig. 7 and 8. As shown in fig. 2, the method of manufacturing the semiconductor device 100 more specifically includes the following steps: forming a first wiring layer 1 on a substrate 10; providing a first semiconductor element 2 on the first wiring layer 1; forming a sacrificial layer 11; forming a hole H in the sacrificial layer 11; embedding a conductive material into the hole H; removing the sacrificial layer 11; forming a first sealant 4; carrying out planarization treatment; forming a second wiring layer 5 on the first sealing material 4; a second semiconductor element 6 is provided on the second wiring layer 5, and wiring is performed by wire bonding; forming a second sealant 8; the substrate 10 is peeled off by reversing the substrate to form the electrode portion 9.

First, a first wiring layer 1 is formed on a substrate 10. A wiring member is formed on the substrate 10, and patterning is performed to form a resin layer. The resin layer is further patterned to further form a conductive member, and patterning processing and the like are performed, thereby obtaining the first wiring layer 1. Then, the first semiconductor element 2 manufactured by another process is provided on the first surface of the first wiring layer 1, and the first wiring layer 1 and the first semiconductor element 2 are wired. Then, the sacrifice layer 11 is formed. The sacrifice layer 11 is subjected to etching or the like to form a hole H in the sacrifice layer 11, thereby obtaining a component shown in the step diagram of fig. 7.

Then, a conductive material as a material of the conductive pillar 3 is embedded in the hole H of the member shown in the step diagram of fig. 7. Then, the sacrifice layer 11 is removed, thereby obtaining a component shown in the step diagram of fig. 8. In this case, the conductive posts 3 may be formed by plating, or the conductive posts 3 may be formed by embedding a conductive material in the holes by screen printing, ink jet, or the like.

Then, the first sealing material 4 is formed, and planarization processing is performed, thereby obtaining a member shown in the step diagram of fig. 4. Thereafter, the same as described above, thereby obtaining the semiconductor device 100 of fig. 1.

(second embodiment) the semiconductor device of the second embodiment is a modification of the semiconductor device of the first embodiment. Fig. 9 is a schematic cross-sectional view of a semiconductor device 101 according to a second embodiment. In the semiconductor device 101 of fig. 9, the front surface of the first semiconductor element 2 is in contact with the fourth surface of the second wiring layer 5. In the semiconductor device 101 according to the second embodiment and the semiconductor device 100 according to the first embodiment, the thickness of the first sealing material 4 is small and the conductive pillar 3 is low. The thickness of the first sealing material 4 is reduced to such an extent that the surface of the first semiconductor element 2 on the second wiring layer 5 side is in contact with or is about to be in contact with the second wiring layer 5. In addition to these, other aspects are common to the first embodiment and the second embodiment. Descriptions of common contents between the first embodiment and the second embodiment are omitted.

By making the first sealing material 4 thin, the height of the semiconductor device 100 can be kept low. As the memory device has increased in capacity and the controller device has been advanced in function, the package size of the memory tends to increase, but the size of the package itself is also limited, and therefore a semiconductor device satisfying the required function while suppressing the package size can be provided.

(third embodiment) the semiconductor device of the third embodiment is a modification of the semiconductor device of the first embodiment. Fig. 10 is a schematic cross-sectional view of a semiconductor device 102 according to a third embodiment. The semiconductor device 102 in fig. 10 includes 1 or more third semiconductor elements 12 mounted on the second semiconductor element 6. The second semiconductor element 6 and the third semiconductor element 12 are connected by a second bonding wire 13. In addition to these, the other aspects are common to the first embodiment and the third embodiment. Descriptions of common contents between the first embodiment and the third embodiment are omitted.

In fig. 10, 1 third semiconductor element 12 is provided on the second semiconductor element 6, but it is also possible to design that 2 or more third semiconductor elements 12 are further stacked. The second semiconductor element 6 and the third semiconductor element 12 are bonded to each other by an adhesive layer such as a die bond film, not shown.

The third surface of the second wiring layer 5, the third semiconductor element 12, and the second bonding wire 13 are sealed by the second sealing material 8. The second semiconductor device 6 and the third semiconductor device 12 are preferably semiconductor devices having the same function. When the second semiconductor element 6 and the third semiconductor element 12 are memory elements, for example, a memory chip with a large capacity can be obtained while suppressing the package height.

(fourth embodiment) the semiconductor device of the fourth embodiment is a modification of the semiconductor device of the first embodiment. Fig. 11 is a schematic cross-sectional view of a semiconductor device 103 according to a fourth embodiment. The semiconductor device 103 according to the fourth embodiment has a fourth semiconductor element mounted on the third surface of the second wiring layer 5. The fourth semiconductor element 14 and the second wiring layer 5 are connected by a third bonding wire 15. The second semiconductor element 6 and the fourth semiconductor element 14 in the second wiring layer 5 are mounted in parallel. The fourth semiconductor element and the third bonding wire 15 are also sealed by the second sealing material 8. In addition to these, the other aspects are common to the first embodiment and the fourth embodiment. Descriptions of common contents between the first embodiment and the fourth embodiment are omitted.

The second semiconductor element 6 and the fourth semiconductor element 14 may be the same element or different elements. For example, a NAND memory may be used as the second semiconductor element 6, and a DRAM may be used as the fourth semiconductor element 14. NAND is slower in reading and writing than DRAM, and thus, by using DRAM as a cache, reading and writing of the semiconductor device 100 can be speeded up. Both the second semiconductor element 6 and the fourth semiconductor element 14 can be laminated as in the semiconductor device 102 of the third embodiment, and such a structure is preferable from the viewpoint of increasing the capacity. For example, a NAND memory is used as both the second semiconductor element 6 and the fourth semiconductor element 14, and writing into the second semiconductor element 6 and the fourth semiconductor element 14 is performed alternately, whereby the writing speed can be increased. The semiconductor device 103 according to the fourth embodiment can also have a large capacity and high-speed read/write functions while suppressing the package height.

Several variations of the method for manufacturing the semiconductor devices 100 to 103 according to the embodiment will be described below. After the conductive post 3 is formed, the first surface of the first wiring layer 1, the first semiconductor element 2, and the conductive post 3 may be sealed with the first sealing material 4, and then subjected to planarization treatment, thereby obtaining a member shown in the step diagram of fig. 4. In this case, the conductive posts 3 may be formed by a known electrolytic plating method.

After the sacrificial layer pillar is formed at a position where the conductive pillar 3 is to be formed, the first surface of the first wiring layer 1, the first semiconductor element 2, and the sacrificial layer pillar may be sealed with the first sealing material 4, and then a planarization process may be performed to dissolve the sacrificial layer, thereby obtaining the component shown in the step diagram of fig. 3.

Various methods other than the above may be employed to obtain the components shown in fig. 3 or 4.

The conductive pillars 3 may be formed by plating with Ni, Au, or the like, in addition to Cu. Alternatively, the conductive paste may be formed by embedding various conductive pastes such as Ag paste.

While several embodiments of the present invention have been described above, these embodiments are presented as examples only, and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.