阅读说明：本技术 半导体设备封装及其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 陈湘祺 林政男 于 2019-05-06 设计创作，主要内容包括：本发明涉及一种半导体设备封装,其包含第一衬底、第二衬底、电接触和支撑元件。所述第一衬底具有第一表面。所述第二衬底具有面向所述第一衬底的所述第一表面的第一表面。所述电接触安置于所述第一衬底与所述第二衬底之间。所述支撑元件安置于所述第一衬底与所述第二衬底之间。所述支撑元件包含热固性材料。(The invention relates to a semiconductor device package comprising a first substrate, a second substrate, electrical contacts and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support member comprises a thermoset material.)

1. A semiconductor device package, comprising:

a first substrate having a first surface;

a second substrate having a first surface facing the first surface of the first substrate;

an electrical contact disposed between the first substrate and the second substrate; and

a support element disposed between the first substrate and the second substrate, wherein the support element comprises a thermoset material.

2. The semiconductor device package of claim 1, wherein the support element comprises a cured B-stage adhesive.

3. The semiconductor device package of claim 1, wherein the curing temperature of the support element is higher than the melting point of the electrical contact.

4. The semiconductor device package of claim 1, wherein

The first surface of the first substrate includes a conductive pad; and is

The first surface of the second substrate includes a conductive pad; and the electrical contacts are in contact with the electrically conductive pads of the first and second substrates.

5. The semiconductor device package of claim 1, wherein the first surface of the first substrate comprises a solder resist and the first surface of the second substrate comprises a solder resist; wherein the support element is in contact with the solder resist of the first substrate and the second substrate.

6. The semiconductor device package of claim 1, further comprising:

a first antenna pattern disposed on the first surface of the first substrate;

a second antenna pattern disposed on the first surface of the second substrate and corresponding to the first antenna pattern,

wherein the first antenna pattern or the second antenna pattern has a horizontal displacement relative to either of the electrical contact and the support element.

7. The semiconductor device package of claim 1, further comprising a plurality of support elements, wherein the support elements are disposed along an edge of the first surface of the first substrate.

8. The semiconductor apparatus package of claim 1, further comprising a plurality of support elements, wherein the support elements are disposed adjacent to a center of the first surface of the first substrate.

9. The semiconductor device package of claim 1, wherein the support element has concave sidewalls.

10. The semiconductor device package of claim 1, wherein the support element is adhered to the first substrate and the second substrate.

11. A semiconductor device package, comprising:

a first substrate having a first surface;

a second substrate having a first surface facing the first surface of the first substrate;

an electrical contact disposed between the first substrate and the second substrate; and

a support element disposed between the first substrate and the second substrate, wherein a curing temperature of the support element is higher than a melting point of the electrical contact.

12. The semiconductor device package of claim 11, wherein the support element comprises a cured B-stage adhesive.

13. The semiconductor device package of claim 11, wherein the support element comprises an epoxy.

14. The semiconductor device package of claim 11, wherein

The first surface of the first substrate comprises a conductive pad and a solder resist covering a portion of the conductive pad; and is

The first surface of the second substrate includes a conductive pad and a solder resist covering a portion of the conductive pad.

15. The semiconductor device package of claim 11, wherein the first surface of the first substrate comprises a solder resist and the first surface of the second substrate comprises a solder resist; wherein the support element is in contact with the solder resist of the first substrate and the second substrate.

16. The semiconductor device package of claim 1, further comprising:

a first antenna pattern disposed on the first surface of the first substrate;

a second antenna pattern disposed on the first surface of the second substrate and corresponding to the first antenna pattern,

wherein the first antenna pattern or the second antenna pattern has a horizontal displacement relative to either of the electrical contact and the support element.

17. The semiconductor device package of claim 11, further comprising a plurality of support elements, wherein the support elements are disposed along an edge of the first surface of the first substrate.

18. The semiconductor apparatus package of claim 11, further comprising a plurality of support elements, wherein the support elements are disposed adjacent to a center of the first surface of the first substrate.

19. The semiconductor device package of claim 11, wherein the support element has a concave sidewall.

20. The semiconductor device package of claim 11, wherein the support element is adhered to the first substrate and the second substrate.

21. A method of manufacturing a semiconductor device package, comprising:

(a) providing a first substrate having a first surface;

(b) disposing one or more support elements on the first surface of the first substrate;

(c) disposing a second substrate on the support element, the second substrate having one or more electrical contacts on a first surface of the second substrate facing the first surface of the first substrate;

(d) providing a first temperature to melt the electrical contact; and

(e) providing a second temperature to cure the support element;

wherein the second temperature is higher than the first temperature.

22. The method of claim 21, wherein in operation (d), the electrical contacts are configured to align conductive pads on the first surface of the first substrate with corresponding conductive pads on the first surface of the second substrate.

23. The method of claim 21, wherein

In operation (d), the electrical contact melts at the first temperature to bring the first substrate closer to the second substrate; and is

In operation (e), the support element is cured at the second temperature to maintain a distance between the first substrate and the second substrate.

Technical Field

The present disclosure relates generally to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including two substrates to define a cavity and a method of manufacturing the same.

Background

The development of mobile communication has caused a demand for high data rate and stable communication quality, and high frequency wireless transmission (e.g., 28GHz or 60GHz) has become one of the most important topics in the mobile communication industry. To enable such high frequency wireless transmission, signals may be transmitted in a frequency band having a wavelength ("millimeter wave") of about ten millimeters to about one millimeter. However, signal attenuation is a problem in millimeter wave transmission.

Disclosure of Invention

In one or more embodiments, according to one aspect, a semiconductor apparatus package includes a first substrate, a second substrate electrical contact, and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support member comprises a thermoset material.

In one or more embodiments, according to another aspect, a semiconductor apparatus package includes a first substrate, a second substrate, electrical contacts, and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The curing temperature of the support member is higher than the melting point of the electrical contact.

In one or more embodiments, according to another aspect, a method of fabricating a semiconductor device package includes (a) providing a first substrate having a first surface; (b) disposing one or more support elements on a first surface of a first substrate; (c) disposing a second substrate on the support element, the second substrate having one or more electrical contacts on a first surface of the second substrate facing the first surface of the first substrate; (d) providing a first temperature to melt the electrical contact; and (e) providing a second temperature to cure the support member. The second temperature is higher than the first temperature.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features may not be drawn to scale and that the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1B illustrates a top view of the substrate shown in fig. 1A, according to some embodiments of the present disclosure.

Fig. 1C illustrates a top view of the substrate shown in fig. 1A, according to some embodiments of the present disclosure.

Fig. 1D illustrates a top view of the substrate shown in fig. 1A, according to some embodiments of the present disclosure.

Fig. 1E illustrates a top view of the substrate shown in fig. 1A, according to some embodiments of the present disclosure.

Fig. 1F illustrates an enlarged view of a portion of the support element shown in fig. 1A, according to some embodiments of the present disclosure.

Fig. 2A, 2B, and 2C illustrate methods of manufacturing semiconductor device packages according to some embodiments of the present disclosure.

Fig. 3A, 3B, 3C, 3D, 3E, and 3F illustrate methods of manufacturing semiconductor device packages according to some embodiments of the present disclosure.

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like elements. The present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Detailed Description

Fig. 1A illustrates a cross-sectional view of a semiconductor device package 1, according to some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, a substrate 11, one or more electrical contacts 12, one or more support elements 13, an antenna pattern 14, an antenna pattern 15, and an electronic component 16.

The substrate 10 may be, for example, a printed circuit board such as a paper copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate. The substrate 10 may include an interconnect structure 10r such as a redistribution layer (RDL) or a ground element. In some embodiments, the substrate 10 may be a single layer substrate or a multilayer substrate comprising a core layer and conductive materials and/or structures disposed on a surface 101 (also referred to as a top surface or first surface) and a surface 102 (also referred to as a bottom surface or second surface) of the substrate 10. The conductive material and/or structure may comprise a plurality of traces. The substrate 10 may include one or more conductive pads 10c proximate to, adjacent to, or embedded in the surface of the substrate 10 and exposed at the surface of the substrate. The substrate 10 may include a solder mask 10r (or solder mask) on the surface 101 of the substrate 10 to completely expose or expose at least a portion of the conductive pad 10c for electrical connection. For example, the solder resist 10r may cover a portion of the conductive pad 10 c.

The antenna pattern 14 is disposed on a surface 101 of the substrate 10. In some embodiments, the antenna pattern 14 includes a plurality of antenna elements. For example, the antenna pattern 14 may include an array of antenna elements. In some embodiments, antenna pattern 14 may comprise an M × N array of antenna elements, where M and N are integers greater than 0.

The electronic component 16 is disposed on the surface 102 of the substrate 10. In some embodiments, the electronic component 16 is electrically connected to the antenna pattern 14 via an interconnect structure 10r within the substrate 10. The electronic component 16 may be a chip or die including a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit device may include active devices such as transistors and/or inactive devices such as resistors, capacitors, inductors, or combinations thereof. The electronic components 16 may be electrically connected to the substrate 10 (e.g., to conductive pads), and the electrical connection may be accomplished by means of flip chip or wire bonding techniques.

The substrate 11 is disposed on the substrate 10 and spaced apart from the substrate 10. In some embodiments, substrate 11 may be the same as or different from substrate 10 depending on design specifications. The substrate 11 has a surface 111 and a surface 112 opposite the surface 111. Surface 112 of substrate 11 faces surface 101 of substrate 10. In some embodiments, surface 111 of substrate 11 is referred to as a top surface or second surface, and surface 112 of substrate 11 is referred to as a bottom surface or first surface. In some embodiments, surface 101 of substrate 10 is parallel to surface 112 of substrate 11. The substrate 11 may include one or more conductive pads 11c proximate to, adjacent to, or embedded in the surface of the substrate 11 and exposed at the surface of the substrate. The substrate 11 may include a solder mask 11r (or solder mask) on the surface 112 of the substrate 11 to expose at least a portion of the conductive pads 11c for electrical connection.

The antenna pattern 15 is disposed on a surface 112 of the substrate 11. The antenna pattern 15 is disposed on a surface 112 of the substrate 11 corresponding to (e.g., disposed over) the antenna pattern 14 disposed on the surface 101 of the substrate 10. For example, the antenna pattern 15 faces the antenna pattern 14. For example, the antenna pattern 15 may be aligned with the antenna pattern 14. In some embodiments, the antenna pattern 15 includes a plurality of antenna elements. For example, the antenna pattern 15 may include an array of antenna elements. In some embodiments, the antenna pattern 15 may comprise an M × N array of antenna elements, where M and N are integers greater than 0. In some embodiments, the antenna pattern may also be disposed on the surface 111 of the substrate depending on design specifications.

Electrical contacts 12 are disposed between substrate 10 and substrate 11. The electrical contacts 12 are disposed between the surface 101 of the substrate 10 and the surface 112 of the substrate 11. Electrical contacts 12 are disposed on conductive pads 10c of substrate 10 and conductive pads 11c of substrate 11. The electrical contact 12 is in contact with the conductive pad 10c of the substrate 10 and the conductive pad 11c of the substrate 11. In some embodiments, the melting point of the electrical contact is in the range of about 217 ℃ to about 225 ℃. In some embodiments, the electrical contacts 12 may be or include solder balls.

The support elements 13 are disposed between the substrates 10. The support element 13 is disposed between the surface 101 of the substrate 10 and the surface 112 of the substrate 11. The support member 13 is disposed on the solder resist 10r of the substrate 10 and the solder resist 11r of the substrate 11. The support member 13 is in contact with the solder resist 10r of the substrate 10 and the solder resist 11r of the substrate 11. The support element 13 is adhered to the substrate 10 and the substrate 11. In some embodiments, the support member 13 has a relatively strong adhesion or solder resists 10r and 11r to the substrate 10 and the substrate 11 to prevent the substrate 11 from peeling or peeling off the substrate 10 in a subsequent process.

In some embodiments, the curing temperature of the support element 13 is higher than the melting point of the electrical contact 12. In some embodiments, the curing temperature of the support member 13 is about 225 ℃ or higher. In some embodiments, the glass transition temperature (Tg) is about 115 ℃. In some embodiments, the support member 13 may comprise a thermoset material, such as an epoxy. In some embodiments, the support member 13 may comprise a B-staged adhesive or a cured B-staged adhesive. In some embodiments, support element 13 may comprise a material that is at class a at room temperature or a temperature less than its Tg (e.g., 115 ℃), then becomes class B at a temperature in the range of its Tg (e.g., 115 ℃) to its curing temperature (e.g., 225 ℃) and becomes class C at a temperature above its curing temperature (225 ℃). In some embodiments, the time required for the manufacturing process to heat the support element 13 from its glass transition temperature to its curing temperature is about 200 seconds. In some embodiments, the viscosity of the support member is about 360Pa · s.

As shown in fig. 1A, since the electrical contacts 12 and the support elements 13 are disposed between the substrates 10 and 11 to define a height, distance, one or more cavities (e.g., air cavities) therebetween, the gain, bandwidth, and radiation efficiency of the antenna patterns 14 and 15 may be improved by facilitating resonance between the antenna patterns 14 and 15. To achieve a desired level of resonance, the tolerance of the height H11 (e.g., the distance between the antenna pattern 14 and the antenna pattern 15) and the height H11 of the air cavity may be controlled within a certain range. For example, the height H11 of the air cavity may be in the range of about 230 micrometers (μm) to about 280 μm with a tolerance of less than ± 28 μm. In some embodiments, the height H11 of the air cavity is determined based on the design (e.g., bandwidth or performance) of the antenna patterns 14 and 15.

In some embodiments, the electrical contact 12 or the support element 13 may not horizontally overlap with the antenna pattern 14 or 15, which may avoid interfering with the electromagnetic wave transmission between the antenna patterns 14 and 15. For example, the electrical contact 12 or the support element 13 may have a horizontal displacement with respect to the antenna pattern 14 or 15. For example, the electrical contact 12 or the support element 13 is horizontally spaced apart from the antenna pattern 14 or 15. For example, the projection of the electrical contact 12 or the support element 13 onto the surface 101 of the substrate 10 may not overlap with the projection of the antenna pattern 14 or 15 onto the surface 101 of the substrate 10.

In some comparative embodiments, the support element 13 may be omitted and only electrical contacts (e.g., solder balls) are used to support the substrate 11. However, the size (e.g., height) of the solder balls may be reduced after each reflow process. Thus, it may be difficult to control the size of each solder ball after the reflow process, and to control the uniformity of all solder balls (which may be desirable). Therefore, there may be large tolerances for the solder balls. For example, it may be desirable to have a solder ball height corresponding to that height, and the problems described above may cause a range of variation (e.g., ± about 50 μm or greater) that is greater than desired, which may reduce the resonant efficiency of the antenna pattern. Thus, the solder balls can be applied to a stacked structure having a relatively low demand for high precision.

In some comparative embodiments, the support element 13 may be implemented by a solid spacer. For example, the spacers are disposed between the substrate 10 and the substrate 11. However, the spacers will remain in a solid state during the manufacturing process, and thus the shape or height of the spacers is substantially fixed. Therefore, it is difficult to control the amount of solder balls and the height, distance, or cavity between the substrates 10 and 11 during the manufacturing process, which may interfere with the connection or adhesion between the substrates 10 and 11.

According to some embodiments of the present disclosure, the support element 13 is implemented by a thermosetting material. During the manufacturing process of the semiconductor device package 1, the process temperature gradually increases, the electrical contacts 12 start to melt when the temperature reaches their melting point (e.g., about 217 ℃ to about 225 ℃), and then the support members 13 solidify while the temperature remains elevated to reach their solidification temperature (e.g., about 225 ℃). During the melting process of the electrical contact 12, the melted electrical contact may firmly adhere to the conductive pads 10c and 11c of the substrates 10 and 11 and bring the substrates 10 and 11 closer together, thereby providing a self-aligning function for the conductive pads 10c and 11c of the substrates 10 and 11. In addition, when the process temperature reaches the curing temperature of the support element 13, the support element 13 is cured or solidified, and remains in a cured or solidified state even if the process temperature is reduced in subsequent manufacturing steps, which may allow the air cavities defined by the electrical contacts 12 and the support element 13 to have a relatively stable and precisely controlled height compared to the air cavities defined by the solder balls alone. Furthermore, the height and shape of the support element 13 may be adjusted before the curing temperature of the support element 13 is reached, which may flexibly and accurately control the height of the air cavity defined by the electrical contacts 12 and the support element 13 to a desired value.

Fig. 1B illustrates a top view of the substrate 10 of the semiconductor device package 1 in fig. 1A, according to some embodiments of the present disclosure. As shown in fig. 1B, the support elements 13 are arranged adjacent to the edge of the substrate 10. The support elements 13 are spaced apart from each other. For example, there is a gap between each of two adjacent support elements 13. In some embodiments, the support element 13 is spaced apart from the electrical contact 12.

Fig. 1C illustrates a top view of the substrate 10 of the semiconductor device package 1 in fig. 1A, according to some embodiments of the present disclosure. The arrangement of the support element 13 and the electrical contacts 12 in fig. 1C is similar to fig. 1B, except that in fig. 1C the support element 13 is further arranged adjacent to the center of the substrate 10 (which may provide better or stable support capability). In some embodiments, the support element 13 is arranged adjacent to an edge of the substrate 10, and the center of the substrate 10 is formed of the same material. Alternatively, the support element 13 is arranged adjacent to the edge of the substrate 10 and the center of the substrate 10 is formed of a different material, which may prevent bending problems.

Fig. 1D illustrates a top view of the substrate 10 of the semiconductor device package 1 in fig. 1A, according to some embodiments of the present disclosure. The arrangement of the support elements 13 and electrical contacts 12 in fig. 1D is similar to that of fig. 1B, except that in fig. 1D, the support elements 13 are arranged to form a wall structure around the edge of the substrate 10, which may prevent bowing problems.

Fig. 1E illustrates a top view of the substrate 10 of the semiconductor device package 1 in fig. 1A, according to some embodiments of the present disclosure. The arrangement of the support elements 13 and electrical contacts 12 in fig. 1E is similar to that of fig. 1C, except that in fig. 1E, the support elements 13 are arranged to form a wall structure around the edge of the substrate 10 (which may provide better or stable support capability).

Fig. 1F illustrates an enlarged view of a portion of the semiconductor device package 1 circled in fig. 1A by a dotted rectangle a, according to some embodiments of the present disclosure. As shown in fig. 1F, the support element 13 has a concave side wall 13 a. For example, the side wall 13a of the support member 13 is recessed inward. For example, the support element 13 has a neck-shaped side wall. For example, the thickness of the support member 13 in contact with the solder resist 10r or 11r is greater than the thickness of the middle portion of the support member 13.

Fig. 2A, 2B, and 2C are cross-sectional views of a semiconductor structure at various stages of fabrication, according to some embodiments of the present disclosure. The figures have been simplified to provide a better understanding of various aspects of the disclosure. In some embodiments, the method illustrated in fig. 2A, 2B, and 2C is used to form the substrate 11 and electrical contacts 12 in fig. 1A.

Referring to fig. 2A, a strip of substrate comprising substrate 11 is provided. A substrate 11 having a conductive pad 11c, a solder resist 11r and an antenna pattern 15 is provided. Electrical contacts 12 (e.g., solder balls) are disposed or mounted on the conductive pads 11c of the substrate 11.

Referring to fig. 2B, a singulation process is performed to separate individual substrates as shown in fig. 2C. That is, singulation is performed on a substrate strip containing the substrate 11. Singulation may be performed, for example, by using a dicing saw, laser, or other suitable cutting technique.

Fig. 3A, 3B, 3C, 3D, 3E, and 3F are cross-sectional views of semiconductor structures at various stages of fabrication, according to some embodiments of the present disclosure. The figures have been simplified to provide a better understanding of various aspects of the disclosure. In some embodiments, the methods illustrated in fig. 3A, 3B, 3C, 3D, 3E, and 3F are used to form the semiconductor device package 1 in fig. 1A.

Referring to fig. 3A, a strip of substrate comprising substrate 10 is provided. A substrate 10 having a conductive pad 10c, a solder resist 10r and an antenna pattern 14 is provided. Electronic components 16 and solder balls are placed or mounted on surface 102 of substrate 10. The structure in fig. 3A is then flipped as shown in fig. 3B.

Referring to fig. 3C, a thermosetting material 13' (a-grade adhesive or B-grade adhesive) is applied on the solder resist 10C of the substrate 10. In some embodiments, the thermoset material 13' is in the form of a gel or glue at room temperature or a temperature below its Tg (e.g., 115 ℃). For example, the thermoset material 13' is in class a. The structure in fig. 2C is disposed on a surface 101 of the substrate 10. For example, the electrical contact 12 is disposed or placed on the conductive pad 10c of the substrate 10.

Referring to fig. 3D, a thermal process is performed on the structure in fig. 3C. For example, the structure in fig. 3C is heated. In some embodiments, when the process temperature reaches the melting point of the electrical contact 12 (e.g., 217 ℃), the electrical contact 12 begins to melt to firmly adhere to the conductive pads 10c and 11c of the substrates 10 and 11 and bring the substrates 10 and 11 closer together, thereby providing a self-aligning function for the conductive pads 10c and 11c of the substrates 10 and 11. When the process temperature remains elevated to reach the curing temperature of the thermoset material 13 '(e.g., about 225 ℃), the thermoset material 13' cures or solidifies to form the support member 13. For example, the thermoset material 13' is in class C. The support element 13 remains in a solidified or solidified state even if the process temperature is reduced in subsequent manufacturing steps, thereby allowing the air cavity defined by the electrical contacts 12 and the support element 13 to have a relatively stable height. Furthermore, the height or shape of the support element 13 may be adjusted before the curing temperature of the support element 13 has been reached, which may flexibly and accurately control the height of the air cavity defined by the electrical contacts 12 and the support element 13 to a desired value. In some embodiments, the time required for the manufacturing process to heat the support element 13 from its glass transition temperature (e.g., 115 ℃) to its curing temperature is about 200 seconds.

Referring to fig. 3E, singulation may be performed to separate individual semiconductor packages as shown in fig. 3F. That is, singulation is performed on a substrate strip containing the substrate 10. Singulation may be performed, for example, by using a dicing saw, laser, or other suitable cutting technique.

As used herein, the terms "approximately," "substantially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation of less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% of the mean of the values, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ± 10 ° from 0 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° from 90 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.

Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm.

As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to transfer electrical current. Conductive materials generally indicate those materials that exhibit little or zero resistance to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the conductive material has a conductivity greater than about 10⁴S/m (e.g. toLess than 10⁵S/m or at least 10⁶S/m) of the above-mentioned material. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of the material is measured at room temperature.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass both the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the art reproduction in the present disclosure and the actual device due to variables in the manufacturing process, and the like. Other embodiments of the disclosure may exist that are not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.