Semiconductor packaging device
阅读说明:本技术 一种半导体封装器件 (Semiconductor packaging device ) 是由 谢建友 马晓波 于 2020-05-28 设计创作,主要内容包括:本申请公开了一种半导体封装器件,该半导体封装器件包括:基板、主芯片、导电件、塑封层、第一封装模块和键合线;其中主芯片位于基板的一侧,且主芯片的非功能面朝向基板;导电件位于主芯片功能面上的连接焊盘上,与连接焊盘电连接;塑封层覆盖主芯片和导电件的侧面;第一封装模块位于基板的一侧且与主芯片同层设置;键合线的两端分别与导电件从塑封层中露出的表面和第一封装模块电连接。通过上述方式,半导体封装器件的主芯片的功能面保护在塑封层之下,主芯片表面的气密性更好,导电件与主芯片的功能面上的连接焊盘电连接并与第一封装模块电连接,连接结构更稳定可靠。(The application discloses semiconductor package device, this semiconductor package device includes: the chip packaging structure comprises a substrate, a main chip, a conductive piece, a plastic packaging layer, a first packaging module and a bonding wire; the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surface of the conductive piece; the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip; and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic packaging layer and the first packaging module. Through the mode, the functional surface of the main chip of the semiconductor packaging device is protected below the plastic packaging layer, the air tightness of the surface of the main chip is better, the conductive piece is electrically connected with the connecting pad on the functional surface of the main chip and electrically connected with the first packaging module, and the connecting structure is more stable and reliable.)
1. A semiconductor package device, comprising:
a substrate;
the chip comprises a main chip, a conductive piece and a plastic package layer, wherein the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surfaces of the conductive pieces;
the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip;
and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic packaging layer and the first packaging module.
2. The semiconductor package device of claim 1,
the plastic packaging layer is provided with a first opening at a position corresponding to the connecting pad, the conductive piece is a conductive column, and the conductive column fills the first opening.
3. The semiconductor package device of claim 1,
the position department that the plastic envelope layer corresponds the connection pad is provided with first opening, electrically conductive piece includes:
sputtering a metal layer to cover the inner wall of the first opening;
and the conductive column is positioned on the sputtering metal layer and fills the first opening.
4. The semiconductor package device of claim 1, further comprising: and the soft plating layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the soft plating layer.
5. The semiconductor package device of claim 4,
the soft coating comprises a nickel layer and a gold layer which are sequentially stacked, wherein the nickel layer is positioned between the conductive piece and the gold layer.
6. The semiconductor package device of claim 1, further comprising:
and the solder layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the solder layer.
7. The semiconductor package device of claim 1, further comprising:
and the non-conductive adhesive layer is positioned on the surface of one side, facing the substrate, of the main chip and the surface of one side, facing the substrate, of the first packaging module.
8. The semiconductor package device of claim 1, further comprising:
the protective shell is positioned on one side of the substrate, and the main chip, the conductive piece, the plastic package layer, the first packaging module and the bonding wire are contained in the containing space of the protective shell.
9. The semiconductor package device of claim 1, wherein the bonding wire is one of a gold wire, a silver wire, a copper wire, an aluminum wire, and an aluminum-clad copper wire.
10. The semiconductor package device of claim 1, wherein the first package module is a pre-packaged mems and the main chip is an asic chip.
Technical Field
The present application relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor package device.
Background
In the existing system-level packaging, a plurality of active elements or passive elements which have different functions and are prepared by different processes are packaged firstly, then are connected with a chip in a routing mode after being manufactured into a packaging module, and are glued at bonding points of routing on a functional surface of the chip, but the strength and the air tightness of the gluing position are poor, the influences of stress and water vapor are great, and the reliability of the formed semiconductor packaging device is low.
Disclosure of Invention
The technical problem that this application mainly solved provides a semiconductor package device, can make the gas tightness on main chip surface better with the protection of the functional surface of main chip under the plastic envelope layer, and electrically conductive piece is connected with the connection pad electricity on the functional surface of main chip and is connected with first encapsulation module electricity, makes connection structure more reliable and more stable.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: the chip packaging structure comprises a substrate, a main chip, a conductive piece, a plastic packaging layer, a first packaging module and a bonding wire; the main chip is positioned on one side of the substrate, and the non-functional surface of the main chip faces the substrate; the conductive piece is positioned on the connecting bonding pad on the functional surface of the main chip and is electrically connected with the connecting bonding pad; the plastic packaging layer covers the main chip and the side surfaces of the conductive pieces; the first packaging module is positioned on one side of the substrate and arranged on the same layer with the main chip; and two ends of the bonding wire are respectively electrically connected with the surface of the conductive piece exposed from the plastic package layer and the first packaging module.
The plastic packaging layer is provided with a first opening at a position corresponding to the connecting pad, the conductive piece is a conductive column, and the conductive column fills the first opening.
Wherein, the position department that the plastic envelope layer corresponds the connection pad is provided with first opening, electrically conductive piece includes: sputtering a metal layer to cover the inner wall of the first opening; and the conductive column is positioned on the sputtering metal layer and fills the first opening.
Wherein the semiconductor package device further comprises: and the soft plating layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the soft plating layer.
The soft coating comprises a nickel layer and a gold layer which are sequentially stacked, wherein the nickel layer is positioned between the conductive piece and the gold layer.
Wherein the semiconductor package device further comprises: further comprising: and the solder layer is positioned on the surface of the conductive piece exposed from the plastic packaging layer, and the bonding wire is electrically connected with the solder layer.
Wherein the semiconductor package device further comprises: further comprising: and the non-conductive adhesive layer is positioned on the surface of one side, facing the substrate, of the main chip and the surface of one side, facing the substrate, of the first packaging module.
Wherein the semiconductor package device further comprises: further comprising: the protective shell is positioned on one side of the substrate, and the main chip, the conductive piece, the plastic package layer, the first packaging module and the bonding wire are contained in the containing space of the protective shell.
The bonding wire is one of a gold wire, a silver wire, a copper wire, an aluminum wire and an aluminum-clad copper wire.
The first packaging module is a pre-packaged micro-electro-mechanical system, and the main chip is an application-specific integrated chip.
The beneficial effect of this application is: the utility model provides a semiconductor package device, its main chip protection is under the plastic envelope layer, and the functional surface of main chip is not directly exposed, has improved the gas tightness of main chip functional surface to electrically conductive on the connection pad on the main chip functional surface, pass through the bonding wire electricity with the first encapsulation module that has packaged in advance and be connected, improved main chip and first encapsulation module connection structure's stability, reduced the influence of stress, make and connect more reliably.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of a semiconductor package device according to an embodiment of the present application;
FIG. 2 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of FIG. 1;
FIG. 3 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 2;
FIG. 4 is a schematic flowchart of an embodiment corresponding to step S101 in FIG. 2;
FIG. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 4;
FIG. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 4;
FIG. 5c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 4;
FIG. 6 is a flowchart illustrating an embodiment corresponding to step S204 in FIG. 4;
FIG. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in FIG. 6;
FIG. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 6;
FIG. 8 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 2;
FIG. 9 is a schematic structural diagram of another embodiment of a semiconductor package device of the present application;
FIG. 10 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of FIG. 9;
FIG. 11 is a schematic structural diagram of an embodiment corresponding to step S401 in FIG. 10;
FIG. 12 is a flowchart illustrating an embodiment corresponding to step S402 in FIG. 10;
FIG. 13a is a schematic structural diagram of an embodiment corresponding to step S501 in FIG. 12;
FIG. 13b is a schematic structural diagram of an embodiment corresponding to step S502 in FIG. 12;
FIG. 14 is a schematic structural diagram of yet another embodiment of a semiconductor package device of the present application;
FIG. 15 is a schematic structural diagram of yet another embodiment of a semiconductor package device of the present application;
fig. 16 is a schematic flow chart diagram of one embodiment of forming the semiconductor package device of fig. 15;
FIG. 17a is a schematic structural diagram of an embodiment corresponding to step S601 in FIG. 16;
FIG. 17b is a schematic structural diagram of an embodiment corresponding to step S602 in FIG. 16;
FIG. 17c is a schematic structural diagram of an embodiment corresponding to step S603 in FIG. 16;
FIG. 17d is a schematic structural diagram of an embodiment corresponding to step S604 in FIG. 16;
fig. 17e is a schematic structural diagram of an embodiment corresponding to the step S604 in fig. 16.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a semiconductor package device 300 according to the present application, including: substrate 20,
Specifically, the
In the semiconductor package device 300 provided by this embodiment, the
Specifically, referring to fig. 2, fig. 2 is a schematic flow chart of an embodiment of forming the semiconductor package device of fig. 1, including:
step S101: and forming a conductive piece on the connecting bonding pad on the functional surface of the main chip, forming a plastic package layer on the side surface and the functional surface of the main chip, and exposing one end of the conductive piece from the plastic package layer.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 2, wherein molding layers 14 are disposed on two sides and functional surfaces of a
In an application manner, please refer to fig. 4 in combination with fig. 1, where fig. 4 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 2, and step S101 specifically includes:
step S201: and forming photoresist on the functional surface of the main chip, and forming a first opening at the position of the photoresist corresponding to the connecting pad.
Specifically, referring to fig. 5a, fig. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 4, in which a non-functional surface of a
Step S202: and forming a conductive member in the first opening.
Specifically, referring to fig. 5b, fig. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 4, where the photoresist 16 protects the functional surface of the
In this application, the
Step S203: and removing the photoresist.
Specifically, referring to fig. 5c, fig. 5c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 4, and the photoresist 16 in fig. 5b is removed to expose the functional surface and the side surface of the
Step S204: and forming a plastic package layer on the side surface of the main chip and the side surface of the conductive piece, wherein one end of the conductive piece is exposed out of the plastic package layer.
In a specific application scenario, please refer to fig. 6, fig. 6 is a flowchart illustrating an embodiment corresponding to step S204 in fig. 4, where step S204 specifically includes:
step S301: and forming plastic packaging layers on the side surface and the functional surface of the main chip, wherein the plastic packaging layers cover the conductive parts.
Specifically, referring to fig. 7a, fig. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in fig. 6, a
Step S302: and grinding one side of the plastic packaging layer, which is far away from the functional surface of the main chip, so that the plastic packaging layer is flush with the conductive piece, and the conductive piece is exposed out of the plastic packaging layer.
Specifically, referring to fig. 7b, fig. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in fig. 6, a side of the
Step S102: one end of the conductive piece is electrically connected with the first packaging module by a routing mode.
Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 2, in which a
In the semiconductor package device 300 provided in this embodiment, the
Further, in the semiconductor package device 300, the
Referring to fig. 9, fig. 9 is a schematic structural diagram of another embodiment of a semiconductor package device 300a of the present application, which has a structure similar to that of the semiconductor package device 300 of fig. 1, and also includes a substrate 20, a
Referring to fig. 10, fig. 10 is a schematic flow chart illustrating one embodiment of forming the semiconductor package device of fig. 9, including:
step S401: and forming a plastic packaging layer on the side surface and the functional surface of the main chip, and forming a second opening at the position of the plastic packaging layer corresponding to the connecting pad.
Specifically, referring to fig. 11, fig. 11 is a schematic structural view of an embodiment corresponding to step S401 in fig. 10, in which a non-functional surface of the
Step S402: and forming a conductive member in the second opening.
Specifically, referring to fig. 12, fig. 12 is a flowchart illustrating an embodiment corresponding to step S402 in fig. 10, where step S402 specifically includes:
step S501: and forming a sputtering metal layer in the second opening and on the surface of the plastic packaging layer adjacent to the second opening.
Specifically, referring to fig. 13a, fig. 13a is a schematic structural view of an embodiment corresponding to step S501 in fig. 12, wherein a sputtered
Step S502: and forming the conductive columns on the sputtered metal layer at the positions corresponding to the second openings.
Specifically, referring to fig. 13b, fig. 13b is a schematic structural view of an embodiment corresponding to step S502 in fig. 12, electroplating is performed on the sputtered
Step S503: and etching to remove the sputtered metal layer on the surface of the plastic package layer.
Specifically, referring to fig. 9 again, the conductive element 12a includes a
Further, a wire bonding process is performed between the conductive member 12a and the
In the semiconductor package device 300a, the
Referring to fig. 14, fig. 14 is a schematic structural diagram of a semiconductor package device according to still another embodiment of the present application, and a semiconductor package device 300b in fig. 14 has a structure similar to that of the semiconductor package device 300 in fig. 1, and also includes a substrate 20, a
Specifically, one end surface of the
Specifically, the soft plating layer 24 includes a nickel layer 26 and a gold layer 28, which are sequentially stacked, wherein the nickel layer 26 is located between the
In other embodiments, the surface of the end of the
Referring to fig. 15, fig. 15 is a schematic structural diagram of a semiconductor package device 300c in fig. 15 according to still another embodiment of the present invention, which is similar to the semiconductor package device 300 in fig. 1 in structure and includes a substrate 20b, a
Specifically, referring to fig. 16, fig. 16 is a schematic flow chart of an embodiment of forming the semiconductor package device of fig. 15, including:
step S601: and pasting the non-functional surface of at least one main chip on the carrier plate.
Specifically, referring to fig. 17a, fig. 17a is a schematic structural diagram of an embodiment corresponding to step S601 in fig. 16, the
Step S602: and forming conductive parts on the connecting bonding pads on the functional surface of the main chip and forming a plastic package layer on the side surface and the functional surface of the main chip.
Specifically, please refer to fig. 17b, fig. 17b is a schematic structural diagram of an embodiment corresponding to step S602 in fig. 16, and this step corresponds to step S101 in fig. 2, a
Step S603: removing the carrier plate; and cutting off a part of the plastic packaging layer between the adjacent main chips to obtain a first packaging body containing the single main chip, the conductive piece and the plastic packaging layer.
Specifically, referring to fig. 17c, fig. 17c is a schematic structural diagram of an embodiment corresponding to step S603 in fig. 16, the
Step S604: the first packaging body and the first packaging module are pasted on the substrate, and one end of the conductive piece is electrically connected with the first packaging module in a routing mode.
Specifically, referring to fig. 17d, fig. 17d is a schematic structural view of an embodiment corresponding to step S604 in fig. 16, in which the
Further, referring to fig. 17e, fig. 17e is a structural schematic diagram of an embodiment corresponding to the step S604 in fig. 16, where a protective shell 40 is disposed on the periphery of the
In a specific Application scenario, the
In other embodiments, the first package module 200b may include any one of active devices, passive devices, optoelectronic chips, and biochips, and the
In the semiconductor package device 300c provided by this embodiment, the
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
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