阅读说明：本技术 半导体装置和用于制造半导体装置的方法 (Semiconductor device and method for manufacturing semiconductor device ) 是由 M·施塔德勒 于 2020-02-18 设计创作，主要内容包括：一种半导体装置,该半导体装置包括下半导体芯片、布置在下半导体芯片的上主侧的上方的上半导体芯片、布置在下半导体芯片的上主侧上的金属化层、将上半导体芯片固定在下半导体芯片上的粘合材料,其中,该金属化层具有如下结构：该结构与该金属化层的其余部分相比具有增大的粗糙度,其中,该结构沿着上半导体芯片的轮廓布置。(A semiconductor device comprising a lower semiconductor chip, an upper semiconductor chip arranged above an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, an adhesive material fixing the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has the following structure: the structure has an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along the contour of the upper semiconductor chip.)

1. A semiconductor device, comprising:

a lower semiconductor chip;

an upper semiconductor chip disposed over an upper main side of the lower semiconductor chip;

a metallization layer disposed on an upper primary side of the lower semiconductor chip;

an adhesive material fixing the upper semiconductor chip on the lower semiconductor chip;

wherein the metallization layer has the following structure: the structure has an increased roughness as compared to a remainder of the metallization layer, wherein the structure is disposed along a contour of the upper semiconductor chip.

2. The semiconductor device of claim 1, wherein the structure has a plurality of recesses.

3. The semiconductor device of claim 2, wherein the recess is a hole extending completely through the metallization layer.

4. A semiconductor device according to claim 2 or 3, wherein the recess has an edge length or diameter in the range of 0.05mm to 0.5 mm.

5. The semiconductor device according to any one of the preceding claims, wherein said structure completely surrounds said upper semiconductor chip.

6. The semiconductor device according to any one of the preceding claims, wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material is limited by the structure to a region below the upper semiconductor chip.

7. A semiconductor device according to any one of the preceding claims, wherein the adhesive material is an adhesive.

8. A semiconductor device according to any preceding claim, wherein the metallisation layer is a metallisation of an electrode of the lower semiconductor chip.

9. A semiconductor device according to any one of the preceding claims, wherein the metallisation layer comprises or consists of Cu or Al.

10. The semiconductor device according to any of the preceding claims, wherein the structure is configured such that there is a current path through the structure in the metallization layer between a region of the metallization layer under the upper semiconductor chip and a region of the metallization layer outside the outline of the upper semiconductor chip.

11. A semiconductor device, comprising:

a lower semiconductor chip;

an upper semiconductor chip disposed over an upper main side of the lower semiconductor chip;

a metallization layer disposed on an upper primary side of the lower semiconductor chip;

an adhesive material fixing the upper semiconductor chip on the lower semiconductor chip;

wherein the metallization layer has a surface-structured portion having a plurality of recesses, wherein the surface-structured portion is arranged along a contour of the upper semiconductor chip.

12. The semiconductor device according to claim 11, wherein the recesses are arranged relative to one another such that they are at a distance from one another of not more than twice the diameter or edge length of the recesses.

13. The semiconductor device of claim 11 or 12, wherein the recess is a hole extending completely through the metallization layer.

14. A method for manufacturing a semiconductor device, the method comprising:

providing a lower semiconductor chip;

applying a metallization layer on an upper main side of the lower semiconductor chip;

structuring the metallization layer;

fixing an upper semiconductor chip on the upper main side of the lower semiconductor chip by means of an adhesive material;

wherein the metallization layer is structured such that it has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer,

wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material is limited by the structure to a region below the upper semiconductor chip.

15. The method of claim 14, wherein the applying of the metallization layer comprises sputtering.

16. The method according to claim 14 or 15, wherein the structuring of the metallization layer comprises applying a photo mask and etching the metallization layer.

17. The process as set forth in any one of claims 14 to 16 wherein the securing of the upper semiconductor chip comprises applying the adhesive material on the upper main side by droplet dispensing such that the spreading of the one or more droplets of the adhesive material is limited by the structures in the metallization layer.

18. The process as set forth in any one of claims 14 to 17, wherein the fixing of the upper semiconductor chip comprises disposing the upper semiconductor chip on the adhesive material such that the upper semiconductor chip floats on the adhesive material.

19. The process as set forth in any one of claims 14 to 18, wherein the fixing of the upper semiconductor chip comprises hardening the adhesive material, wherein during the hardening, the upper semiconductor chip is fixed by surface tension applied to the adhesive material by the structures in the metallization layer.

Technical Field

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background

The semiconductor device may be, for example, a semiconductor package including more than one semiconductor chip (e.g., two semiconductor chips arranged on top of each other). The stacked semiconductor chips can be, for example, power semiconductor chips and associated control chips. Here, the upper semiconductor chip may be fixed on the upper main side of the lower semiconductor chip by means of an adhesive material such as an adhesive. Depending on parameters such as the viscosity of the respective adhesive material, the deposition amount of the adhesive material, etc., the upper semiconductor chip may "float" (over) on the adhesive material and thus leave the position where it is disposed. This may lead to the following: the upper semiconductor chip causes a short circuit or cannot be properly electrically connected in the semiconductor device (for example, because the wire automated bonding device cannot reach the contact portion of the upper semiconductor chip if the upper semiconductor chip is not properly positioned). These and other problems may be facilitated to be overcome by an improved semiconductor device or an improved method for manufacturing a semiconductor device.

The object on which the invention is based is solved by the features of the independent claims.

Advantageous embodiments and further developments of the invention are specified in the dependent claims.

Disclosure of Invention

A specific example relates to a semiconductor device including: a lower semiconductor chip; an upper semiconductor chip disposed over the upper main side of the lower semiconductor chip; a metallization layer disposed on the upper primary side of the lower semiconductor chip; an adhesive material that fixes the upper semiconductor chip on the lower semiconductor chip, wherein the metallization layer has a structure of: the structure has an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along the contour of the upper semiconductor chip.

A specific example relates to a semiconductor device including: a lower semiconductor chip; an upper semiconductor chip disposed over the upper main side of the lower semiconductor chip; a metallization layer disposed on the upper primary side of the lower semiconductor chip; an adhesive material which fixes the upper semiconductor chip on the lower semiconductor chip, wherein the metallization layer has a surface-structured portion which has a plurality of recesses, wherein the surface-structured portion is arranged along the contour of the upper semiconductor chip.

A specific example relates to a method for manufacturing a semiconductor device, the method including: providing a lower semiconductor chip; applying a metallization layer on the upper main side of the lower semiconductor chip; structuring the metallization layer; the upper semiconductor chip is fixed to the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured in such a way that it has an increased roughness along the contour of the upper semiconductor chip compared to the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material (Benetzung) is limited by this structure to the region below the upper semiconductor chip.

Drawings

The drawings illustrate examples and together with the description serve to explain the principles of the invention. The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals may denote corresponding, similar or identical parts to each other.

Fig. 1A and 1B show a top view (fig. 1A) and a cross-sectional view (fig. 1B) of a semiconductor arrangement with two semiconductor chips stacked one above the other and a structured metallization layer;

FIG. 2 illustrates a top view of another semiconductor device in which the structure includes a dedicated current carrying path;

fig. 3A to 3C respectively show perspective views of a semiconductor device at different stages of manufacture. In fig. 3A, an adhesive material is deposited, and in fig. 3B, an upper semiconductor chip is placed on the adhesive material. Fig. 3C shows the following case: the adhesive material that flows away over the metallization layer due to its low viscosity is constrained by the structure;

fig. 4A to 4D show different possible shapes of the recess of the structure;

fig. 5 shows a flow chart of a method for manufacturing a semiconductor device.

Detailed Description

In this specification, the terms "coupled" and/or "electrically coupled" do not imply that elements must be directly coupled; intermediate elements may be provided between "coupled" or "electrically coupled" elements.

A semiconductor device including a plurality of semiconductor chips is described below. The semiconductor chips may be of different types, manufactured by different technologies and comprise, for example, integrated circuits, electro-optical or electromechanical circuits and/or passive elements. The semiconductor chip can be designed, for example, as a power semiconductor chip, for example as a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (bipolar transistor with insulated gate), a JFET (junction field effect transistor), a power bipolar transistor or a power diode. Furthermore, the semiconductor chip may comprise control circuitry, a microprocessor or a microelectromechanical component. In one example, a semiconductor chip having a vertical structure may be present, i.e., the semiconductor chip may be fabricated such that current may flow in a direction perpendicular to a main surface of the semiconductor chip. In one example, a semiconductor chip having a vertical structure may have a turn-on element on both of its main surfaces, i.e., on its upper and lower sides. The semiconductor chip may be made of a specific semiconductor material such as Si, SiC, SiGe, GaAs, or GaN.

The semiconductor chip may have electrodes (or vias) that allow electrical contact to be established with an integrated circuit included in the semiconductor chip. One or more metal layers may be applied to the electrodes of the semiconductor chip. The metal layer may be fabricated in any desired geometry and any desired material composition. The metal layer may for example be present in the form of a layer covering an area. Any desired metal or metal alloy (e.g., aluminum, titanium, gold, silver, copper, palladium, platinum, nickel, chromium, or nickel vanadium) may be used as the material. The metal layer need not be homogenous or made of only one material, that is, the materials contained in the metal layer may have different compositions and different concentrations. The electrodes may be located on the active major surface of the semiconductor chip.

The lower semiconductor chip described below may be placed on a system carrier (lead frame). The system carrier may be of any shape, size and any material. The system carrier may include a carrier (die pad) and connection lines (leads). During the manufacture of the semiconductor device, the carrier and the connection lines may be connected to each other. The carrier and the connecting lines can also be made of one piece.

Fig. 1A shows a top view of a schematic example of a semiconductor device 100. The semiconductor device 100 has a lower semiconductor chip 101 and an upper semiconductor chip 102. The upper semiconductor chip 102 is disposed over the upper main side 101_1 of the lower semiconductor chip 101. The metallization layer 103 is arranged on the upper main side 101_1 of the lower semiconductor chip 101, for example between the lower semiconductor chip 101 and the upper semiconductor chip 102. The upper semiconductor chip 102 is fixed on the lower semiconductor chip 101 by an adhesive material 104. The metallization layer 103 has a structure 105 with increased roughness (in other words, has a surface structure with a plurality of recesses) which is arranged along the contour 102_1 of the upper semiconductor chip 102.

Here, the term "roughness" particularly denotes a structured surface in the metallization layer 103 having a predefined pattern. Such roughness or surface structuring affects the wetting characteristics of the liquid (e.g., the bonding material 104) deposited onto the metallization layer (e.g., by increasing the contact angle). This makes it possible in particular to prevent the liquid from spreading over areas with increased roughness.

The lower semiconductor chip 101 may be, for example, a power semiconductor chip designed for operation at high voltages and/or high currents. The lower semiconductor chip 101 may be, for example, a FET or an IGBT. The lower semiconductor chip 101 may have a vertical transistor structure with a first power electrode on the upper main side 101_1 and a second power electrode on the opposite lower main side. The first power electrode may be, for example, a source or an emitter. The second power electrode may be, for example, a drain or a collector. However, according to one example, the mentioned electrodes may also be arranged on the opposite main sides of the lower semiconductor chip 101, respectively. The lower semiconductor chip 101 may have other electrodes, such as a gate or a measurement electrode. The gate or measuring electrode may be arranged on the upper main side 101_1, for example.

The upper semiconductor chip 102 may be, for example, a driver chip designed to control the lower semiconductor chip 101. The upper semiconductor chip 102 may be connected with the lower semiconductor chip 101 through, for example, a conductive connection such as a bonding wire (not shown in fig. 1A). The upper semiconductor chip 102 may have the following lateral dimensions: the lateral dimension is significantly smaller than (e.g., about half as large as or even smaller than) the lateral dimension of the lower semiconductor chip 101. According to one example, the upper semiconductor chip 102 has electrical connection terminals only on the upper main side facing away from the lower semiconductor chip 101. The lower main side of the upper semiconductor chip 102 facing the lower semiconductor chip 101 may have no electrical connection terminals.

The bonding material 104 may be an adhesive, such as a non-conductive adhesive. The adhesive material 104 may completely or at least partially cover the lower main side of the upper semiconductor chip 102, and the adhesive material may electrically isolate the two semiconductor chips 101, 102 from each other. As shown in fig. 1A, the adhesive material 104 may protrude beyond the outline 102_1 of the upper semiconductor chip 102. The adhesive material 104 may be deposited on the upper main side 101_1 of the lower semiconductor chip 101 by means of a suitable deposition method. For example, one or more droplets of adhesive material 104 may be deposited on the upper main side 101_1 by a dispenser.

The adhesive material 104 may have a high viscosity or may also have a low viscosity. Here, "high viscosity" may mean that droplets of the adhesive material 104 deposited on the upper main side 101_1 do not or only to a low extent run off after deposition (i.e. the shape of the adhesive material is substantially maintained). Here, "low viscosity" may mean that droplets of the adhesive material 104 deposited on the upper main side 101_1 tend to run off after deposition (i.e., the shape of the adhesive material is not substantially maintained).

After the deposition of the adhesive material 104, the upper semiconductor chip 102 is placed on the adhesive material. Next, the bonding material 104 may be hardened, for example, by heating in an oven. The upper semiconductor chip 102 is held in place just by viscosity or surface tension applied by the adhesive material 104 before hardening. For the case where the adhesive material 104 having low viscosity is used in the semiconductor device 100, if the adhesive material 104 having low viscosity has flowed over the upper main side 101_1, the upper semiconductor chip 102 may "float out" from a desired position.

After the hardening of the adhesive material 104, if the actual position of the upper semiconductor chip 102 is greatly deviated from its intended position, the connection terminals on the upper semiconductor chip 102 may not be reached by the wire bonding device. In addition, an electrical short may be caused by the upper semiconductor chip 102 moving in position. As described in more detail below, the structure 105 may help avoid these problems.

The metallization layer 103 may be a metallization of an electrode, in particular a power electrode, of the lower semiconductor chip 101. The metallization layer 103 may comprise one or more of any suitable metals or metal alloys, or may consist of Al, Ag, Cu or Ti, for example. The metallization layer 103 may be manufactured using a sputtering process. The metallization layer 103 may also be arranged below the lower main side of the upper semiconductor chip 102. The adhesive material 104 may electrically isolate the upper semiconductor chip 102 from the metallization layer 103. The metallization layer 103 may also have one or more additional connection regions 103_1, which are designed, for example, to provide gate connections or measurement connections of the lower semiconductor chip 101.

The structure 105 in the metallization layer 103 may completely surround the upper semiconductor chip 102 (as shown in fig. 1A), or the structure may be arranged along only one side or only two sides (e.g., L-shaped) or three sides (e.g., U-shaped) of the upper semiconductor chip 102. The structure 105 may protrude into a region inside the outline 102_1 of the upper semiconductor chip 102, or the structure may be arranged completely outside the outline 102_ 1.

The structure 105 may have a plurality of recesses 106, which are configured in the metallization layer 103. The recess 106 may be arranged in the base body. The recess 106 may be created in the metallization layer 103 by an etching process, for example. The recess 106 may be a hole extending completely through the metallization layer 103.

According to an example, the metallization layer may have a thickness in the range of 1 μm to 100 μm, in particular 2 μm to 30 μm or 5 μm to 20 μm. The metallization layer may in particular have a thickness of about 10 μm. All recesses 106 may have the same dimensions. However, the recess 106 may also have a different size, for example, the recess 106 disposed closer to the upper semiconductor chip 102 may have a different size from the other recesses 106 disposed farther from the upper semiconductor chip 102. The recess 106 may have an edge length or diameter in the range of 0.05mm to 0.5mm (e.g., about 0.1 mm).

As shown in fig. 1A, the structures 105 may have a substantially checkerboard pattern (in other words, the recesses 106 may be arranged in a checkerboard pattern). However, the structure 105 may also have another suitable pattern, such as a pattern with circular recesses, triangular recesses, etc.

Fig. 1B shows a cross section through the semiconductor device 100 along the line a-a in fig. 1A. As shown in fig. 1B, the metallization layer 103 may extend under a region under the upper semiconductor chip 102. The adhesive material 104 may completely fill a region under the upper semiconductor chip 102, and the adhesive material may laterally protrude beyond the outline of the upper semiconductor chip 102. As can be seen in fig. 1A and 1B, structure 105 represents the following region: the region has an increased roughness compared to the rest of the metallization layer 103. This increased roughness (e.g., by increasing the contact angle) prevents the bonding material 104 from flowing out of the area within the structure 105 after being applied.

The semiconductor device 100 may comprise a carrier, for example a lead frame (lead frame), on which the lower semiconductor chip 101 is arranged and possibly also electrically connected to the carrier. The power connection terminal of the semiconductor device 100 may be disposed beside the upper semiconductor chip 102 on the metallization layer 103 and may be electrically connected thereto. The semiconductor device 100 may also have a molded body (english "molded body") that encapsulates the lower semiconductor chip 101 and the upper semiconductor chip 102.

Fig. 2 shows another semiconductor arrangement 200, which may be identical to the semiconductor arrangement 100, except for the differences mentioned below.

A structure 105 having a checkerboard pattern as shown in fig. 1A would result in: the region of the metallization layer 103 directly below the upper semiconductor chip 102 (i.e. within the structure 105) and the region outside the structure 105 are not electrically connected to one another or are only poorly electrically connected. However, it may be desirable for regions of metallization layer 103 that are inside and outside structure 105 to be electrically connected to each other. Thus, the structure 105 may be configured such that a current path leads through the structure 105 and connects these regions to each other.

In the example of fig. 2, structure 105 has a dedicated current path 201. The current path 201 may have any suitable shape and arrangement. However, the current path 201 should be configured such that the intended effect of the structure 105 is not cancelled by the current path (i.e., the upper semiconductor chip 102 is prevented from floating out of its desired position).

Fig. 3A and 3B show the semiconductor device 100 or 200 at different stages of production according to one example of a method for manufacturing a semiconductor device.

Fig. 3A shows a stage where an adhesive material 104 has been deposited on the lower semiconductor chip 101, in particular the metallization layer 103. The individual droplets 301 of the bonding material 104 may in particular be deposited adjacent to each other. Fig. 3B shows a stage after the upper semiconductor chip 102 has been placed on the adhesive material 104. The adhesive material 104 may be pressed out laterally under the upper semiconductor chip 102 by the weight of the upper semiconductor chip 102 or by pressure applied by a placing apparatus. However, as already explained above, the structure 105 prevents the adhesive material 104 from being distributed over a larger area. This can be achieved, for example, by: the contact angle between the adhesion material 104 and the metallization layer 103 is increased by the structure 105, which reduces the wettability of the metallization layer 103 in the region of the structure 105.

In the example of fig. 3A, the bonding material 104 is shown to be present in the form of a single droplet 301 after deposition. However, depending on the viscosity or hydrophilicity of the respectively used adhesive material 104, the following may also occur: the droplets 301 are spread out after deposition and for example wet the metallization layer 103 over the entire area within the structure 105. Fig. 3C shows an example of this case. However, even in this case, the adhesive material 104 cannot pass over the area having the structure 105.

Fig. 4A to 4D illustrate examples of alternative patterns of the section B in fig. 3A in a top view, which may be used in the structure 105 instead of a checkerboard pattern. As shown in fig. 4A or 4B, the structure 105 may have a pattern of circular recesses or holes 106, for example. As shown in fig. 4A, the recesses 106 may be arranged spaced apart from each other. In this manner, a current path may be constructed between a region within structure 105 and a region outside structure 105. However, the recesses 106 may also be arranged such that the recesses 106 adjacent to each other are in contact (see fig. 4B).

Other possible shapes of the recesses are, for example, triangular recesses 106 as shown in fig. 4C or diamond-shaped recesses 106 as shown in fig. 4D. The tip of the triangular recess 106 may be directed away from the upper semiconductor chip 102, or the tip may also be directed toward the upper semiconductor chip.

Fig. 5 shows a flow chart of a method for manufacturing a semiconductor device. The method 500 may be used, for example, to manufacture the semiconductor device 100 or 200.

The method 500 includes: in 501, a lower semiconductor chip is provided; in 502, a metallization layer is applied on an upper main side of a lower semiconductor chip; in 503, the metallization layer is structured; in 504, the upper semiconductor chip is fixed on the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured in such a way that it has an increased roughness along the contour of the upper semiconductor chip compared to the remaining part of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material is limited by the structure to a region below the upper semiconductor chip.

The method 500 may further include sputtering (sputtern) to apply the metallization layer 103. After applying the metallization layer 103, a photoresist may be applied to photolithographically structure the metallization layer 103. In this case, the metallization layer 103 covered by the structured photoresist can be etched (in particular wet etched). Thus, the structure 105 and any other structures may be produced in common in the metallization layer 103.

According to the method 500, the fixing of the upper semiconductor chip 102 may include: the adhesive material 104 is applied on the upper main side 101_1 by means of drop dispensing (tropifanausgabe). One or more drops of adhesive material 104 may be applied such that spreading of the one or more drops of adhesive material 104 is limited by the structures 105 in the metallization layer 103, as already explained above.

According to the method 500, the adhesive material 104 may be hardened after the upper semiconductor chip 102 is fixed, for example, by heating in an oven. During hardening, the upper semiconductor chip 102 can be fixed in its position by surface tension applied to the adhesive material 104 by the structure 105.

Examples of the invention

The semiconductor device and the method for manufacturing the semiconductor device are further explained below according to specific examples.

Example 1 is a semiconductor device including: a lower semiconductor chip; an upper semiconductor chip disposed over the upper main side of the lower semiconductor chip; a metallization layer disposed on the upper primary side of the lower semiconductor chip; an adhesive material that fixes the upper semiconductor chip to the lower semiconductor chip, wherein the metallization layer has the following structure: the structure has an increased roughness compared to the rest of the metallization layer, wherein the structure is arranged along the contour of the upper semiconductor chip.

Example 2 is the semiconductor device according to example 1, wherein the structure has a plurality of concave portions.

Example 3 is the semiconductor device of example 2, wherein the recess is a hole extending completely through the metallization layer.

Example 4 is the semiconductor device of example 2 or 3, wherein the recess has an edge length or diameter in a range of 0.05mm to 0.5 mm.

Example 5 is the semiconductor device according to any one of the above examples, wherein the structure completely surrounds the upper semiconductor chip.

Example 6 is the semiconductor device of any of the above examples, wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material is limited by the structure to a region under the upper semiconductor chip.

Example 7 is the semiconductor device of any one of the above examples, wherein the adhesive material is an adhesive.

Example 8 is the semiconductor device of any one of the above examples, wherein the metallization layer is a metallization of an electrode of the lower semiconductor chip.

Example 9 is the semiconductor device of any of the above examples, wherein the metallization layer comprises or consists of Cu or Al.

Example 10 is the semiconductor device of any of the above examples, wherein the structure is configured such that there is a current path through the structure in the metallization layer between a region of the metal layer under the upper semiconductor chip and a region of the metallization layer outside of a contour of the upper semiconductor chip.

Example 11 is a semiconductor device, including: a lower semiconductor chip; an upper semiconductor chip disposed over the upper main side of the lower semiconductor chip; a metallization layer disposed on the upper primary side of the lower semiconductor chip; an adhesive material which fixes the upper semiconductor chip on the lower semiconductor chip, wherein the metallization layer has a surface-structured portion which has a plurality of recesses, wherein the surface-structured portion is arranged along the contour of the upper semiconductor chip.

Example 12 is the semiconductor device of example 11, wherein the recesses are arranged relative to each other such that a distance between each other is no greater than twice a diameter or edge length of the recesses.

Example 13 is the semiconductor device of example 11 or 12, wherein the recess is a hole extending completely through the metallization layer.

Example 14 is a method for manufacturing a semiconductor device, the method comprising: providing a lower semiconductor chip; applying a metallization layer at an upper main side of the lower semiconductor chip; structuring the metallization layer; the upper semiconductor chip is fixed to the upper main side of the lower semiconductor chip by means of an adhesive material, wherein the metallization layer is structured in such a way that it has an increased roughness along the contour of the upper semiconductor chip compared to the remaining part of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the adhesive material is limited by the structure to a region below the upper semiconductor chip.

Example 15 is the method of example 14, wherein the applying of the metallization layer comprises sputtering.

Example 16 is the method of example 14 or 15, wherein the structuring of the metallization layer comprises applying a photomask and etching the metallization layer.

Example 17 is the method of any one of examples 14 to 16, wherein the securing of the upper semiconductor chip includes applying the adhesive material on the upper main side by droplet dispensing such that spreading of one or more droplets of the adhesive material is limited by structures in the metallization layer.

Example 18 is the method according to any one of examples 14 to 17, wherein the fixing of the upper semiconductor chip includes arranging the upper semiconductor chip on the adhesive material such that the upper semiconductor chip floats on the adhesive material.

Example 19 is the method of any one of examples 14 to 18, wherein the fixing of the upper semiconductor chip includes hardening the adhesive material, wherein during the hardening, the upper semiconductor chip is fixed by surface tension applied to the adhesive material by the structures in the metallization layer.

Example 20 is an apparatus having means for performing a method according to any of examples 14-19.

Although specific examples have been shown and described herein, it will be apparent to those skilled in the art that: numerous alternative and/or equivalent configurations of the specific examples shown and described may be considered without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. It is therefore intended that this invention be limited only by the claims and the equivalents thereof.