阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 叶国梁 占迪 宋胜金 于 2020-05-25 设计创作，主要内容包括：本发明提供了一种半导体器件及其制造方法,半导体器件包括至少一层辅助金属层,辅助金属层位于待互连的第一金属层与待互连的第二金属层之间；开孔暴露出辅助金属层的侧面；增大了露出的金属层的面积,从而增大互连层从开孔底部往上的填充速率,使开孔底部尽快填充形成互连层,避免填充互连层过程中顶部提前封口导致互连失败。互连层的顶面低于靠近互连层一侧的第一衬底的表面；互连层不形成在贯穿的第一衬底之间,确保了互连层与第一衬底之间的绝缘,且减小了待互连的第一金属层和待互连的第二金属层之间的配线距离,同时还减小了配线电容。(The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises at least one auxiliary metal layer, and the auxiliary metal layer is positioned between a first metal layer to be interconnected and a second metal layer to be interconnected; opening the hole to expose the side surface of the auxiliary metal layer; the area of the exposed metal layer is increased, so that the filling rate of the interconnection layer from the bottom of the opening to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer, and interconnection failure caused by sealing the top in advance in the process of filling the interconnection layer is avoided. The top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer; the interconnection layer is not formed between the penetrating first substrates, insulation between the interconnection layer and the first substrates is ensured, and a wiring distance between the first metal layer to be interconnected and the second metal layer to be interconnected is reduced, while wiring capacitance is also reduced.)

1. A semiconductor device, comprising:

the wafer comprises a first wafer and a second wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer; the first dielectric layer is bonded facing the second dielectric layer;

at least one auxiliary metal layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer and/or the second dielectric layer;

the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the side face of the first metal layer to be interconnected, the side face of the auxiliary metal layer and the surface of the second metal layer to be interconnected are exposed out of the opening;

the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

2. The semiconductor device according to claim 1, wherein a vertical distance between adjacent metal layers in a metal layer group consisting of the second metal layer to be interconnected, the auxiliary metal layer and the first metal layer to be interconnected is gradually increased from a side of the second metal layer to be interconnected to a side of the first metal layer to be interconnected in a wafer thickness direction.

3. The semiconductor device according to claim 1, wherein in a wafer thickness direction, an opening size of the opening in a layer in which each metal layer in a group of metal layers consisting of the second metal layer to be interconnected and the auxiliary metal layer is located is gradually increased from a side of the second metal layer to be interconnected to a side of the first metal layer to be interconnected.

4. The semiconductor device according to claim 1, wherein the auxiliary metal layer has a cross-sectional shape of any one of a circular ring, a square ring, or a square array spaced apart in a cross-section parallel to the first substrate.

5. The semiconductor device according to claim 1, wherein in a wafer thickness direction, a plurality of first metal layers are distributed in the first dielectric layer, and the first metal layer to be interconnected is located in one of the layers; a plurality of second metal layers are distributed in the second dielectric layer, and the second metal layers to be interconnected are positioned in one layer; the auxiliary metal layer and the first metal layer or the second metal layer between the first metal layer to be interconnected and the second metal layer to be interconnected are positioned on the same layer, and the material of the auxiliary metal layer is the same as that of the first metal layer or the second metal layer.

6. The semiconductor device according to claim 1, further comprising: an insulating layer located over the interconnect layer and filling the opening.

7. A method of manufacturing a semiconductor device, comprising:

providing a first wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

providing a second wafer, wherein the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer;

forming at least one auxiliary metal layer in the first dielectric layer and/or the second dielectric layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected;

bonding the first dielectric layer facing the second dielectric layer;

forming an opening, wherein the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the opening exposes the side surface of the first metal layer to be interconnected, the side surface of the auxiliary metal layer and the surface of the second metal layer to be interconnected;

and forming an interconnection layer, wherein the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein a vertical pitch of adjacent metal layers in a metal layer group consisting of the second metal layer to be interconnected, the auxiliary metal layer, and the first metal layer to be interconnected is gradually increased from a side of the second metal layer to be interconnected toward a side of the first metal layer to be interconnected in a wafer thickness direction.

9. The method for manufacturing a semiconductor device according to claim 7, wherein in a wafer thickness direction, an opening size of the opening in a layer in which each metal layer in a group of metal layers consisting of the second metal layer to be interconnected and the auxiliary metal layer is located is gradually increased from a side of the second metal layer to be interconnected to a side of the first metal layer to be interconnected.

10. The method for manufacturing a semiconductor device according to claim 7, wherein a plurality of first metal layers are formed in the first dielectric layer in a wafer thickness direction, the first metal layer to be interconnected being located in one of the layers; forming a plurality of second metal layers in the second dielectric layer, wherein the second metal layers to be interconnected are positioned in one layer; the auxiliary metal layer and the first metal layer or the second metal layer between the first metal layer to be interconnected and the second metal layer to be interconnected are formed in the same metal layer.

11. The method for manufacturing a semiconductor device according to claim 7, further comprising, after forming the interconnect layer: and forming an insulating layer which is positioned above the interconnection layer and fills the opening.

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device and a manufacturing method thereof.

Background

With the trend of highly integrated semiconductor development, the integration of chips with different functions is the main development direction of semiconductor packaging technology, and wafer level stacking based on 3D-IC technology can achieve the goals of lower cost, faster speed and higher density. After wafer bonding, how to realize metal interconnection between wafers is an important process in semiconductor processing.

Fig. 1 is a diagram of a metal interconnection structure between stacked wafers, in which an upper wafer 11 and a lower wafer 12 are stacked and bonded, the upper wafer 11 includes an upper wafer substrate 111, an upper wafer dielectric layer 112, and an upper wafer metal layer 113, and the lower wafer 12 includes a lower wafer substrate 121, a lower wafer dielectric layer 122, and a lower wafer metal layer 123; through silicon Through vias (TSV) B communicated in the longitudinal direction₁Middle filling interconnection layer A₁The upper wafer metal layer 113 and the lower wafer metal layer 123 are electrically connected. Through silicon via B₁Through the upper wafer substrate 111, the interconnect layer A₁Formed on the through silicon via B₁In (A), it is difficult to secure the interconnection layer A₁And the upper wafer substrate 111 (within the dotted oval line in the figure).

Fig. 2 is a diagram of another metal interconnection structure between stacked wafers, in which an upper wafer 21 and a lower wafer 22 are stacked and bonded, the upper wafer 21 includes an upper wafer substrate 211, an upper wafer dielectric layer 212, and an upper wafer metal layer 213, and the lower wafer 22 includes a lower wafer substrate 221, a lower wafer dielectric layer 222, and a lower wafer metal layer 223; through the silicon through hole B separated in the longitudinal direction₂Middle filling interconnection layer A₂The upper wafer metal layer 213 and the lower wafer metal layer 223 are electrically connected. Through silicon via B₂Through the upper wafer substrate 211, interconnect layer A₂Formed on the through silicon via B₂In (A), it is difficult to secure the interconnection layer A₂And the upper wafer substrate 211 (within the dotted oval line in the figure).

The insulation between the interconnection layer and the upper wafer substrate is difficult to ensure by the metal interconnection mode between the two stacked wafers; moreover, the height (length) of the interconnection layer is long, and the interconnection layer extends to at least the top surface of the wafer substrate besides reaching the distance between two metal layers to be interconnected, so that the length of the interconnection layer is long, and the wiring capacitance is increased.

In another metal interconnection method between stacked wafers, an upper wafer and a lower wafer are stacked and bonded, a projection of an upper wafer metal layer in a longitudinal direction (a wafer thickness direction) falls on a lower wafer metal layer, a TSV hole connects the upper wafer metal layer and the lower wafer metal layer, and an interconnection layer is filled in the TSV hole to realize electrical connection between the upper wafer metal layer and the lower wafer metal layer. In the actual process of the method, the height difference of two metal layers to be connected is large, the filling rate of a top interconnection layer is difficult to control, and the top is easy to seal in advance, namely, the interconnection layer grows from the periphery of an upper wafer metal layer to the middle of the upper wafer metal layer, and the interconnection layer grows from bottom to top of a lower wafer metal layer; the interconnection layer growing from bottom to top at the position of the lower wafer metal layer does not grow to be communicated with the interconnection layer growing at the position of the upper wafer metal layer, and the interconnection layer growing at the position of the upper wafer metal layer grows from the periphery to the middle and is sealed, so that the growth of the interconnection layer is interrupted, and the metal interconnection between the stacked wafers fails.

Disclosure of Invention

The invention aims to ensure the insulation between an interconnection layer and a wafer substrate and reduce the wiring capacitance between metal layers of two wafers.

It is another object of the present invention to avoid premature capping of the interconnect layer fill process.

The present invention provides a semiconductor device including:

the wafer comprises a first wafer and a second wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer; the first dielectric layer is bonded facing the second dielectric layer;

at least one auxiliary metal layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer and/or the second dielectric layer;

the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the side face of the first metal layer to be interconnected, the side face of the auxiliary metal layer and the surface of the second metal layer to be interconnected are exposed out of the opening;

the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

Furthermore, in the thickness direction of the wafer, from one side of the second metal layer to be interconnected to one side of the first metal layer to be interconnected, the vertical distance between adjacent metal layers in a metal layer group formed by the second metal layer to be interconnected, the auxiliary metal layer and the first metal layer to be interconnected is gradually increased.

Furthermore, in the thickness direction of the wafer, from one side of the second metal layer to be interconnected to one side of the first metal layer to be interconnected, the size of the opening of each metal layer in the metal layer group consisting of the second metal layer to be interconnected and the auxiliary metal layer is gradually increased. Further, the auxiliary metal layer has a cross section parallel to the first substrate, and the cross section is in the shape of any one of a circular ring, a square ring or a square array distributed at intervals.

Furthermore, in the thickness direction of the wafer, a plurality of first metal layers are distributed in the first dielectric layer, and the first metal layers to be interconnected are positioned in one of the layers; a plurality of second metal layers are distributed in the second dielectric layer, and the second metal layers to be interconnected are positioned in one layer; the auxiliary metal layer and the first metal layer or the second metal layer between the first metal layer to be interconnected and the second metal layer to be interconnected are positioned on the same layer, and the material of the auxiliary metal layer is the same as that of the first metal layer or the second metal layer.

Further, the method also comprises the following steps: an insulating layer located over the interconnect layer and filling the opening.

The present invention also provides a method of manufacturing a semiconductor device, comprising:

providing a first wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

providing a second wafer, wherein the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer;

forming at least one auxiliary metal layer in the first dielectric layer and/or the second dielectric layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected;

bonding the first dielectric layer facing the second dielectric layer;

forming an opening, wherein the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the opening exposes the side surface of the first metal layer to be interconnected, the side surface of the auxiliary metal layer and the surface of the second metal layer to be interconnected;

and forming an interconnection layer, wherein the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

Furthermore, in the thickness direction of the wafer, from one side of the second metal layer to be interconnected to one side of the first metal layer to be interconnected, the vertical distance between adjacent metal layers in a metal layer group formed by the second metal layer to be interconnected, the auxiliary metal layer and the first metal layer to be interconnected is gradually increased.

Furthermore, in the thickness direction of the wafer, from one side of the second metal layer to be interconnected to one side of the first metal layer to be interconnected, the size of the opening of each metal layer in the metal layer group consisting of the second metal layer to be interconnected and the auxiliary metal layer is gradually increased.

Furthermore, in the thickness direction of the wafer, a plurality of first metal layers are formed in the first dielectric layer, and the first metal layers to be interconnected are positioned in one of the layers; forming a plurality of second metal layers in the second dielectric layer, wherein the second metal layers to be interconnected are positioned in one layer; the auxiliary metal layer and the first metal layer or the second metal layer between the first metal layer to be interconnected and the second metal layer to be interconnected are formed in the same metal layer.

Further, after the forming the interconnection layer, the method further includes: and forming an insulating layer which is positioned above the interconnection layer and fills the opening.

Compared with the prior art, the invention has the following beneficial effects:

the semiconductor device comprises at least one auxiliary metal layer, wherein the auxiliary metal layer is positioned between a first metal layer to be interconnected and a second metal layer to be interconnected, and is formed in a first dielectric layer and/or a second dielectric layer; the opening exposes the side surface of the auxiliary metal layer; the area of the exposed metal layer is increased, so that the filling rate of the interconnection layer from the bottom of the opening to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer, and the interconnection failure caused by the fact that the top is sealed in advance in the process of filling the interconnection layer is avoided. The top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer; the interconnection layer is not formed between the penetrating first substrates, insulation between the interconnection layer and the first substrates is ensured, and a wiring distance between the first metal layers to be interconnected and the second metal layers to be interconnected is reduced, while wiring capacitance is also reduced.

Further, the insulating layer is located above the interconnection layer and fills the opening. The insulating layer is filled between the first substrates penetrating through the first substrate, so that the first substrate and the interconnection layer are better insulated.

Further, under the condition of a certain filling rate of the interconnection layer, the smaller the filling volume is, the shorter the filling time is. In the thickness direction of the wafer, from one side of the second metal layers to be interconnected to one side of the first metal layers to be interconnected, the vertical distance between adjacent metal layers in a metal layer group formed by the second metal layers to be interconnected, the auxiliary metal layers and the first metal layers to be interconnected is gradually increased, and the size of the openings in the layer where each metal layer is located in the metal layer group formed by the second metal layers to be interconnected and the auxiliary metal layers is gradually increased. Thus, the filling volume of the opening close to the second metal layer to be interconnected is smaller, the required filling time is shorter, the filling from the bottom to the top is completed faster, the top is prevented from being sealed in advance, and the opening is prevented from being sealed before the first metal layer and the second metal layer are electrically connected with each other.

Drawings

Fig. 1 is a diagram of a metal interconnection structure between stacked wafers.

Fig. 2 is a structural diagram of another metal interconnection structure between stacked wafers.

Fig. 3 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 4 to 10 are schematic views of steps of a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

11-upper wafer; 111-upper wafer substrate; 112-upper wafer dielectric layer; 113-upper wafer metal layer; 12-lower wafer; 121-lower wafer substrate; 122-lower wafer dielectric layer; 123-lower wafer metal layer;

21-upper wafer; 211-upper wafer substrate; 212-upper wafer dielectric layer; 213-upper wafer metal layer; 22-lower wafer; 221-a lower wafer substrate; 222-lower wafer dielectric layer; 223-lower wafer metal layer;

31-a first wafer; 311-a first substrate; 312-a first dielectric layer; 313 — first metal layers to be interconnected; 314-etch stop layer; 315-first passivation layer; 316-auxiliary metal layer; 316 a-first auxiliary metal layer; 316 b-a second auxiliary metal layer; 316 c-a third auxiliary metal layer; 317-an interconnection layer; 318-an insulating layer;

32-a second wafer; 321-a second substrate; 322-a second dielectric layer; 323-second round metal layers to be interconnected; 324-etch stop layer.

Detailed Description

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.

An embodiment of the present invention provides a semiconductor device, including:

the wafer comprises a first wafer and a second wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer; the first dielectric layer is bonded facing the second dielectric layer;

at least one auxiliary metal layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer and/or the second dielectric layer;

the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the side face of the first metal layer to be interconnected, the side face of the auxiliary metal layer and the surface of the second metal layer to be interconnected are exposed out of the opening;

the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

The semiconductor device of the present embodiment is described in detail below with reference to fig. 7 to 10, and includes:

the wafer comprises a first wafer, a second wafer and a third wafer, wherein the first wafer comprises a first substrate 311, a first dielectric layer 312 positioned on the first substrate 311, and a first metal layer 313 embedded in the first dielectric layer 312 and to be interconnected; specifically, a plurality of first metal layers may be distributed in the first dielectric layer 312 at intervals in the wafer thickness direction, and the first metal layers of different layers may be electrically connected according to actual needs, for example, electrically connected through plugs. The first metal layer 313 to be interconnected is located in one of the first metal layers and is interconnected with the second wafer. The material of the first metal layer comprises copper or aluminum.

The second wafer comprises a second substrate 321, a second dielectric layer 322 located on the second substrate 321, and a second metal layer 323 embedded in the second dielectric layer 322 and to be interconnected, wherein the first dielectric layer 312 is bonded facing the second dielectric layer 322. Specifically, a plurality of second metal layers may be distributed in the second dielectric layer 322 at intervals in the wafer thickness direction, and the second metal layers of different layers may be electrically connected according to actual needs, for example, electrically connected through plugs. The second metal layer 323 to be interconnected is located in one of the several second metal layers and is interconnected with the first wafer. The material of the second metal layer comprises copper or aluminum.

At least one auxiliary metal layer 316, the auxiliary metal layer being located between the first metal layer 313 to be interconnected and the second metal layer 323 to be interconnected, the auxiliary metal layer 323 being formed in the first dielectric layer 312 and/or the second dielectric layer 322. The auxiliary metal layer is made of copper or aluminum.

A hole V penetrates through the first wafer and the second dielectric layer 322 with partial thickness and exposes the second metal layer 323 to be interconnected; the opening V exposes a side surface of the first metal layer 313 to be interconnected, a side surface of the auxiliary metal layer 316, and an upper surface of the second metal layer 323 to be interconnected.

An interconnect layer 317, the interconnect layer 317 being formed in the opening V, the first metal layer 313 to be interconnected, the auxiliary metal layer 316, and the second metal layer 323 to be interconnected all being electrically connected to the interconnect layer 317, a top surface of the interconnect layer 317 being lower than a surface of the first substrate 311 near a side of the interconnect layer. The material of the interconnect layer 317 may include copper or nickel. Compared with the prior art shown in fig. 1 and 2, the interconnection layer 317 is not formed between the penetrating first substrates 311, reducing the wiring distance between the first metal layer 313 to be interconnected and the second metal layer 323 to be interconnected, while also reducing the wiring capacitance.

The auxiliary metal layer is positioned between the first metal layer 313 to be interconnected and the second metal layer 323 to be interconnected in the thickness direction of the wafer; the auxiliary metal layer may be one layer, two layers or more. For convenience of working procedures, the auxiliary metal layer and the first metal layer can be manufactured on the same layer and formed in the same metal layer process, and the auxiliary metal layer and the first metal layer are made of the same material. The first metal layer is used for electrical connection inside the wafer, for example, and the auxiliary metal layer is used for increasing the metal layer area exposed by the opening V and increasing the filling rate of the interconnection layer 317 from the bottom of the opening V to the top.

Fig. 7 shows, for example, three auxiliary metal layers, namely a first auxiliary metal layer 316a, a second auxiliary metal layer 316b and a third auxiliary metal layer 316c, distributed in the first dielectric layer 312. Fig. 8a is a perspective view of the opening in fig. 7 looking down (for clarity of view, only the second auxiliary metal layer 316b and the third auxiliary metal layer 316c are shown).

The side surface of the first metal layer 313 to be interconnected and the side surface of the auxiliary metal layer 316 exposed by the opening V may be axisymmetrically distributed on both sides of the opening V; or the two sides of the opening V are distributed in a non-axisymmetric way and are arranged according to the specific process requirement.

As shown in fig. 7 and 8a, the side of the first metal layer 313 to be interconnected exposed by the opening V and the side of the auxiliary metal layer 316 are axisymmetrically distributed on both sides of the opening V. The X direction and the Y direction which are perpendicular to each other are arranged in a plane parallel to the first substrate 311, and the direction perpendicular to the first substrate 311 is set as the Z direction.

The auxiliary metal layer 316 has a cross-sectional shape of any one of a circular ring or a square ring or an array of spaced squares in a cross-section (lateral direction) parallel to the first substrate 311, where the squares include rectangles and squares. The shape of the opening V corresponds to the shape of the auxiliary metal layer. Example one: the auxiliary metal layer is circular, the opening is circular in transverse cross section, the annular inner wall of the auxiliary metal layer is exposed out of the opening, the height of the auxiliary metal layer in the Z direction is h, the transverse cross section of the layer where the auxiliary metal layer is located is circular (for example, the radius is a), and the area S of the side face, exposed out of the opening, of the auxiliary metal layer is 2 pi ah. Example two: the auxiliary metal layer has a square ring shape in transverse cross section, the opening has a square shape in transverse cross section (for example, as shown in fig. 8 a), and the area of the side surface of the auxiliary metal layer (for example, 316b and 316c) exposed by the opening V is equal to the product of the perimeter of the square obtained by the cross section and the height of the auxiliary metal layer in the Z direction. Example three: as shown in fig. 8b, the auxiliary metal layer 316d has a square array with a spacing in the transverse cross-sectional shape. Fig. 8c is a perspective view corresponding to fig. 8b looking down the opening V.

As shown in fig. 7 to 9, the semiconductor device may have one interconnect layer 317, or two or more interconnect layers 317. The material of the interconnect layer 317 is, for example, copper or nickel. Copper has higher electrical conductivity, higher thermal conductivity, lower melting point, lower coefficient of thermal expansion, and is more ductile. The interconnect layer is formed using an electroless deposition process. Specifically, the electroless pretreatment is performed on the metal layer surfaces exposed by the opening V (the side surfaces of the auxiliary metal layer 316, the upper surface of the second metal layer 323 to be interconnected, the side surfaces of the first metal layer 313 to be interconnected). The electroless plating pretreatment is to form a displacement coating on the surface of the metal layer exposed by the opening V, such as a palladium displacement coating for displacement treatment of electroless copper plating, a zinc displacement coating for displacement treatment of electroless nickel plating, and deposit a plated copper film or nickel film in the via hole V by electroless copper plating or nickel to form the interconnect layer 317, thereby electrically connecting the first metal layer 313 to be interconnected and the second metal layer 323. Electroless deposition has the advantages of no shadowing, low cost processing steps, short time, good uniformity and good gap filling capability.

In the process of forming the interconnect layer 317 by electroless plating, a displacement coating is formed on the exposed metal layer surfaces (the side surfaces of the auxiliary metal layer 316, the upper surface of the second metal layer 323 to be interconnected, and the side surfaces of the first metal layer 313 to be interconnected) of the opening V from which the interconnect layer 317 (plating film) is deposited (filled), and the filling rate of the interconnect layer in the opening V is proportional to the metal layer exposed area S. The embodiment of the present invention aims to complete the filling (growing) of the interconnect layer 317 from the bottom of the opening V to the top of the second metal layer 323 to be interconnected before the seal of the interconnect layer is grown from the periphery to the middle of the side position of the first metal layer 313 to be interconnected. The opening V exposes the area of a part of the second metal layer 323 to be interconnected, and through the design of the auxiliary metal layer 316, the opening also exposes the area of the auxiliary metal layer 316, so that the area of the exposed metal layer is increased, the filling rate of the interconnection layer 317 from the bottom of the opening V to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer 317, and the top is prevented from being sealed in advance in the process of filling the interconnection layer 317, so that interconnection failure is avoided.

The opening V is arranged on a cross section (transverse direction) parallel to the substrate, the length of the cross section along the X direction is L, the width of the cross section of the opening along the Y direction is W, the vertical distance between the adjacent auxiliary metal layers in the Z direction (thickness direction of the wafer) is H (distance between the top surface of the lower auxiliary metal layer and the bottom surface of the upper auxiliary metal layer), and the vertical distance H between the second metal layer to be interconnected, the auxiliary metal layer and the adjacent metal layers in a metal layer group formed by the first metal layer to be interconnected is gradually increased from one side of the second metal layer to be interconnected to one side of the first metal layer to be interconnected in the thickness direction of the wafer; and the size of the opening is gradually increased in the layer where each metal layer is located in the metal layer group consisting of the second metal layer to be interconnected and the auxiliary metal layer.

When the auxiliary metal layer is a layer, the second metal layer to be interconnected, the auxiliary metal layer and the first metal layer to be interconnected form a metal layer group, and the vertical distance between the second metal layer 323 to be interconnected and the auxiliary metal layer in the metal layer group is smaller than the vertical distance between the auxiliary metal layer and the first metal layer 313 to be interconnected.

When the auxiliary metal layers are two layers, for example, the auxiliary metal layers include a lower auxiliary metal layer and an upper auxiliary metal layer, the second metal layer to be interconnected, the lower auxiliary metal layer, the upper auxiliary metal layer and the first metal layer to be interconnected form a metal layer group, and a vertical distance between the second metal layer 323 to be interconnected and the lower auxiliary metal layer, a vertical distance between the lower auxiliary metal layer and the upper auxiliary metal layer, and a vertical distance between the upper auxiliary metal layer and the first metal layer 313 to be interconnected are gradually increased from bottom to top in the metal layer group.

When the auxiliary metal layers are multiple, the second metal layers to be interconnected, the multiple auxiliary metal layers and the first metal layers to be interconnected form a metal layer group, and the vertical distance between the second metal layer 323 to be interconnected and the bottommost auxiliary metal layer, the vertical distance between the adjacent auxiliary metal layers and the vertical distance between the topmost auxiliary metal layer and the first metal layer 313 to be interconnected in the metal layer group are gradually increased from bottom to top. It should be understood that, in the present embodiment, from bottom to top, the side where the second metal layer 323 to be interconnected is located to the side where the first metal layer 313 to be interconnected is located. The vertical pitch in this embodiment refers to a vertical distance between a top surface of a lower metal layer (the second metal layer 323 to be interconnected or any one of the auxiliary metal layers) and a bottom surface of an upper metal layer (the auxiliary metal layer or the first metal layer 313 to be interconnected) adjacent thereto.

With multiple auxiliary metal layers, the vertical spacing H between adjacent auxiliary metal layers is gradually increased from bottom to top. For example, three auxiliary metal layers, a first auxiliary metal layer 316a, a second auxiliary metal layer 316b, and a third auxiliary metal layer 316c are shown in fig. 7. The vertical distance between the first auxiliary metal layer 316a and the second auxiliary metal layer 316b is H₁The vertical distance between the second auxiliary metal layer 316b and the third auxiliary metal layer 316c is H₂Is provided with H₁＜H₂In this way, the filling time at the second auxiliary metal layer 316b is shorter than that at the third auxiliary metal layer 316c, so that the lower portion is earlier than the upper portion to complete the deposition (filling) of the interconnect layer, thereby avoiding the premature top sealing. The opening is formed in the second metal layer to be interconnected,The size of the opening of each metal layer in the metal layer group formed by the auxiliary metal layers is gradually increased, that is, the section length L of the opening along the X direction is gradually increased from bottom to top, the section width of the opening along the Y direction is gradually increased from bottom to top, for example, the size of the opening at the layer where the first metal layers 313 to be interconnected are located (for example, the section area parallel to the substrate section) is larger than the size of the opening at the layer where the second metal layers 323 to be interconnected are located (for example, the section area parallel to the substrate section). Since the filling volume is smaller and the required filling time is shorter under the condition of a certain filling rate of the interconnection layer, the filling volume of the opening close to the second metal layer 323 to be interconnected is smaller, the required filling time is shorter, the filling from the bottom to the top is completed faster, the top is prevented from being sealed in advance, and the opening is prevented from being sealed before the first metal layer and the second metal layer are electrically connected with each other.

As shown in fig. 10, the semiconductor device of the present embodiment further includes: an insulating layer 318, the insulating layer 318 being located over the interconnect layer 317 and filling the opening. The insulating layer is filled between the first substrates 311 penetrating through, so that the first substrates 311 and the interconnection layer 317 are better insulated.

The semiconductor device of this embodiment includes at least one auxiliary metal layer, where the auxiliary metal layer is located between the first metal layer to be interconnected and the second metal layer to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer and/or the second dielectric layer; the opening exposes the side surface of the auxiliary metal layer; the area of the exposed metal layer is increased, so that the filling rate of the interconnection layer from the bottom of the opening to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer, and the interconnection failure caused by the fact that the top is sealed in advance in the process of filling the interconnection layer is avoided. The top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer; the interconnection layer is not formed between the penetrating first substrates, insulation between the interconnection layer and the first substrates is ensured, and a wiring distance between the first metal layers to be interconnected and the second metal layers to be interconnected is reduced, while wiring capacitance is also reduced.

It should be noted that the present invention does not limit which wafer the first wafer and the second wafer must be placed on top/bottom, but the positions of the upper wafer and the lower wafer can be interchanged. Herein, for simplicity and convenience of description, only one positional relationship of the two wafers is shown, and those skilled in the art can understand that all the technical contents described herein are also equally applicable to the case where the positions of the "first wafer" and the "second wafer" are reversed upside down, and the positional relationship of the layers of the stacked semiconductor device is also correspondingly reversed upside down.

Note that, in this document, the numbers "first", "second", and the like are only for distinguishing between various components or processes having the same name, and do not mean an order or positional relationship, and the like. In addition, for respective different components having the same name, for example, "first substrate" and "second substrate", "first passivation layer" and "second passivation layer", etc., it is not intended that they all have the same structure or component. For example, although not shown in the drawings, in most cases, components formed in the "first substrate" and the "second substrate" are different, and the structures of the substrates may also be different. In some embodiments, the substrate may be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate may be a composite substrate such as a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (sige-on-insulator substrate). It will be understood by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application. Various device structures (not limited to semiconductor device structures) such as gate structures and the like may be formed in the substrate.

An embodiment of the present invention further provides a method for manufacturing a semiconductor device, as shown in fig. 3, including:

providing a first wafer, wherein the first wafer comprises a first substrate, a first dielectric layer positioned on the first substrate, and a first metal layer to be interconnected embedded in the first dielectric layer;

providing a second wafer, wherein the second wafer comprises a second substrate, a second dielectric layer positioned on the second substrate and a second metal layer to be interconnected embedded in the second dielectric layer;

forming at least one auxiliary metal layer in the first dielectric layer and/or the second dielectric layer, wherein the auxiliary metal layer is positioned between the first metal layer to be interconnected and the second metal layer to be interconnected;

bonding the first dielectric layer facing the second dielectric layer;

forming an opening, wherein the opening penetrates through the first wafer and the second dielectric layer with partial thickness, and the opening exposes the side surface of the first metal layer to be interconnected, the side surface of the auxiliary metal layer and the surface of the second metal layer to be interconnected;

and forming an interconnection layer, wherein the interconnection layer is formed in the opening, the first metal layer to be interconnected, the auxiliary metal layer and the second metal layer to be interconnected are all electrically connected with the interconnection layer, and the top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer.

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to fig. 4 to 10.

As shown in fig. 4, a first wafer 31 is provided, where the first wafer 31 includes a first substrate 311, a first dielectric layer 312 located on the first substrate 311, and a first metal layer 313 embedded in the first dielectric layer 312 and to be interconnected; a plurality of first metal layers may be distributed in the first dielectric layer 312 at intervals in the wafer thickness direction, and the first metal layers of different layers may be electrically connected according to actual needs. The first metal layer to be interconnected 313 is located in one of the layers; at least one auxiliary metal layer 316 is formed in the first dielectric layer 312. The auxiliary metal layer and the first metal layer may be formed in the same metal layer. An etching stop layer 314 can be further formed between the first metal layer 313 to be interconnected and the first dielectric layer 312; a first passivation layer 315 is formed on a surface of the first substrate 311 facing away from the first dielectric layer 312 to protect the first substrate 311.

As shown in fig. 5, providing a second wafer 32, where the second wafer 32 includes a second substrate 321, a second dielectric layer 322 located on the second substrate 321, and a second metal layer 323 embedded in the second dielectric layer 322 and to be interconnected; a plurality of second metal layers may be distributed in the second dielectric layer 322 at intervals in the wafer thickness direction, and the second metal layers of different layers may be electrically connected according to actual needs. A second metal layer 323 to be interconnected is located in one of the layers.

As shown in fig. 6, the first wafer 31 and the second wafer 32 are bonded, and specifically, the first dielectric layer 312 is bonded facing the second dielectric layer 322.

The auxiliary metal layer 316 is located between the first metal layer 313 to be interconnected and the second metal layer 323 to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer 312 and/or the second dielectric layer 322. The auxiliary metal layer 316 is shown in fig. 6 as being formed in the first dielectric layer 312. If the second metal layer 323 to be interconnected is located at a lower position in the second wafer (near the first substrate 321), an auxiliary metal layer may also be formed in the second dielectric layer 322. And a plurality of auxiliary metal layers can be distributed in the first dielectric layer and/or the second dielectric layer at intervals in the thickness direction of the wafer.

As shown in fig. 7, an opening V may be formed through a photolithography and etching process, where the opening V penetrates through the first wafer 31 and the second dielectric layer 322 with a partial thickness, and the opening V exposes a side surface of the first metal layer 313, a side surface of the auxiliary metal layer 316, and an upper surface of the second metal layer 323 to be connected. Fig. 7 shows, for example, three auxiliary metal layers, namely a first auxiliary metal layer 316a, a second auxiliary metal layer 316b and a third auxiliary metal layer 316c, distributed in the first dielectric layer 312. Fig. 8a is a perspective view of the opening in fig. 7 looking down (for clarity of view, only the second auxiliary metal layer 316b and the third auxiliary metal layer 316c are shown).

As shown in fig. 9, an interconnect layer 317 is formed, for example, by an electroless deposition process. A pretreatment of electroless plating is performed on the exposed metal layer surfaces of the opening V (the side surfaces of the auxiliary metal layer 316, the upper surface of the second metal layer 323 to be interconnected, the side surfaces of the first metal layer 313 to be interconnected). The electroless pretreatment forms a displacement coating on the exposed metal layer surface of the opening V. For example, a palladium displacement coating is used for displacement treatment of electroless copper plating, a zinc displacement coating is used for displacement treatment of electroless nickel plating, and a plated copper film or nickel film is deposited in the via hole V by electroless copper plating or nickel plating to form the interconnect layer 317. The first metal layer to be interconnected 313, the auxiliary metal layer 316 and the second metal layer to be interconnected 323 are all electrically connected with the interconnection layer 317.

For electroless copper plating processes, a plating solution is used to electrolessly deposit copper onto the palladium coating, the plating solution including, for example, copper sulfate or copper sulfanilate, the copper ions in which react with the palladium to deposit copper. For electroless nickel plating processes, a plating solution is used to electrolessly deposit nickel onto a zinc coating, the plating solution including, for example, nickel chloride or nickel sulfate, with the nickel ions in the nickel chloride or nickel sulfate reacting with the zinc to deposit nickel.

The top surface of the interconnect layer 317 is lower than the surface of the first substrate 311 near the side of the interconnect layer 317, and compared with the prior art shown in fig. 1 and 2, the interconnect layer 317 is not formed between the penetrating first substrates 311, which reduces the wiring distance between the first metal layer 313 to be interconnected and the second metal layer 323 to be interconnected, and also reduces the wiring capacitance.

In the process of forming the interconnect layer 317 by electroless plating, a displacement coating is formed on the exposed metal layer surfaces (the side surfaces of the auxiliary metal layer 316, the upper surface of the second metal layer 323 to be interconnected, and the side surfaces of the first metal layer 313 to be interconnected) of the opening V from which the interconnect layer 317 (plating film) is deposited (filled), and the filling rate of the interconnect layer in the opening V is proportional to the metal layer exposed area S. The embodiment of the present invention aims to complete the filling (growing) of the interconnect layer 317 from the bottom of the opening V to the top of the second metal layer 323 to be interconnected before the seal of the interconnect layer is grown from the periphery to the middle of the side position of the first metal layer 313 to be interconnected. The opening V exposes the area of a part of the second metal layer 323 to be interconnected, and through the design of the auxiliary metal layer 316, the opening also exposes the area of the auxiliary metal layer 316, so that the area of the exposed metal layer is increased, the filling rate of the interconnection layer 317 from the bottom of the opening V to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer 317, and the top is prevented from being sealed in advance in the process of filling the interconnection layer 317, so that interconnection failure is avoided.

Under the condition of a certain filling rate of the interconnection layer, the smaller the filling volume is, the shorter the filling time is. In the thickness direction of the wafer, from one side of the second metal layers to be interconnected to one side of the first metal layers to be interconnected, the vertical distance between the adjacent auxiliary metal layers is gradually increased, and the size of the openings formed in the layer where each metal layer is located in the metal layer group consisting of the second metal layers to be interconnected and the auxiliary metal layers is gradually increased. Thus, the filling volume of the opening close to the second metal layer to be interconnected is smaller, the required filling time is shorter, the filling from the bottom to the top is completed faster, the top is prevented from being sealed in advance, and the opening is prevented from being sealed before the first metal layer and the second metal layer are electrically connected with each other.

As shown in fig. 10, an insulating layer 318 is formed, the insulating layer 318 is formed over the interconnect layer 317 to fill the opening V and cover the surface of the first passivation layer 315, and the insulating layer over the first passivation layer 315 is polished by a Chemical Mechanical Polishing (CMP) process to form a planarized insulating layer 318. The insulating layer 318 is filled between the penetrating first substrates 311, ensuring insulation between the first substrates 311 and the interconnect layer 317.

In summary, the present invention provides a semiconductor device and a method for manufacturing the same, where the semiconductor device includes at least one auxiliary metal layer, the auxiliary metal layer is located between the first metal layer to be interconnected and the second metal layer to be interconnected, and the auxiliary metal layer is formed in the first dielectric layer and/or the second dielectric layer; the opening exposes the side surface of the auxiliary metal layer; the area of the exposed metal layer is increased, so that the filling rate of the interconnection layer from the bottom of the opening to the top is increased, the bottom of the opening is filled as soon as possible to form the interconnection layer, and the interconnection failure caused by the fact that the top is sealed in advance in the process of filling the interconnection layer is avoided. The top surface of the interconnection layer is lower than the surface of the first substrate close to one side of the interconnection layer; the interconnection layer is not formed between the penetrating first substrates, insulation between the interconnection layer and the first substrates is ensured, and a wiring distance between the first metal layers to be interconnected and the second metal layers to be interconnected is reduced, while wiring capacitance is also reduced.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.