阅读说明：本技术 半导体设备封装及其制造方法 (Semiconductor device package and method of manufacturing the same ) 是由 吕文隆 于 2019-04-23 设计创作，主要内容包括：本公开的至少一些实施例涉及一种半导体设备封装。所述半导体设备封装包含衬底、半导体设备和底部填充胶。所述半导体设备安置在所述衬底上。所述半导体设备包含第一侧面。所述底部填充胶安置在所述衬底与所述半导体设备之间。所述底部填充胶包含第一侧面。所述底部填充胶的所述第一侧面与所述半导体设备的所述第一侧面基本上共面。(At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor apparatus is disposed on the substrate. The semiconductor device includes a first side. The underfill is disposed between the substrate and the semiconductor device. The underfill comprises a first side. The first side of the underfill is substantially coplanar with the first side of the semiconductor device.)

1. A semiconductor device package, comprising:

a substrate;

a semiconductor apparatus disposed on the substrate, the semiconductor apparatus including a first side; and

an underfill disposed between the substrate and the semiconductor apparatus, the underfill comprising a first side,

wherein the first side of the underfill is substantially coplanar with the first side of the semiconductor device.

2. The semiconductor device package of claim 1, wherein the semiconductor device is a flip-chip type semiconductor device.

3. The semiconductor device package of claim 1, wherein

The semiconductor apparatus further includes a second side opposite the first side; and is

A first distance between a first end of the underfill on the substrate and the first side of the semiconductor device is less than a second distance between a second end of the underfill on the substrate and the second side of the semiconductor device.

4. The semiconductor device package of claim 1, wherein a portion of the first side of the underfill tapers inward in a direction from the semiconductor device to the substrate.

5. The semiconductor device package of claim 3 or 4, wherein

The underfill further comprises a second side opposite the first side; and is

The second side of the underfill partially covers the second side of the semiconductor device.

6. The semiconductor device package of claim 1, wherein a distance between a side of the substrate and the first side of the semiconductor device is less than 0.5 mm.

7. The semiconductor device package of claim 1, further comprising an encapsulant encapsulating the semiconductor device and the underfill.

8. A semiconductor device package, comprising:

a substrate comprising a conductive layer;

a first semiconductor apparatus disposed on the substrate, the first semiconductor apparatus including a first side substantially perpendicular to the substrate;

a first underfill disposed between the substrate and the first semiconductor device, the first underfill including a first side that is substantially coplanar with the first side of the first semiconductor device;

a second semiconductor apparatus disposed on the substrate, the second semiconductor apparatus including a first surface substantially perpendicular to the substrate; and

a second underfill disposed between the substrate and the second semiconductor device, the second underfill comprising a first side that is substantially coplanar with the first side of the second semiconductor device,

wherein the first side of the first semiconductor device faces the first side of the second semiconductor device.

9. The semiconductor device package of claim 8, wherein the first and second semiconductor devices are electrically connected via the conductive layer of the substrate.

10. The semiconductor apparatus package of claim 8, further comprising an alignment structure disposed on the substrate and between the first semiconductor apparatus and the second semiconductor apparatus.

11. The semiconductor device package of claim 8, wherein

A second side of the first underfill opposite the first side partially covers a second side of the first semiconductor device opposite the first side, or a second side of the second underfill opposite the first side partially covers a second side of the second semiconductor device opposite the first side.

12. The semiconductor device package of claim 8, wherein a distance between the first side of the first semiconductor device and the first side of the second semiconductor device is less than 1 mm.

13. The semiconductor device package of claim 8, further comprising an encapsulant encapsulating the first and second semiconductor devices and the first and second underfill.

14. A method of manufacturing a semiconductor device package, comprising:

arranging a substrate with an electric connection structure;

forming an alignment structure on the substrate;

injecting a fluid on the substrate;

bonding a semiconductor device to the substrate, the semiconductor device including an electrical connection structure; and

disposing an underfill between the substrate and the semiconductor device, wherein at least one side of the underfill is formed against the alignment structure.

15. The method of claim 14, further comprising providing the semiconductor device on the fluid, wherein the semiconductor device on the fluid drifts toward and against the alignment structure and the electrical connection structure of the semiconductor device is aligned with the electrical connection structure of the substrate.

16. The method of claim 14, further comprising removing the alignment structure.

17. The method of claim 14, wherein the alignment structure is formed by a photolithographic operation.

18. The method of claim 15, further comprising:

tilting the substrate; and

the substrate is oscillated.

19. The method of claim 18, further comprising removing the fluid by a heating operation.

20. The method of claim 18, further comprising pressing the semiconductor apparatus to the substrate to electrically connect the electrical connection structure of the semiconductor apparatus to the electrical connection structure of the substrate.

Technical Field

The present disclosure relates to a semiconductor device package including an underfill adhesive and a semiconductor device and a method of manufacturing the same.

Background

As miniaturization of semiconductor device packages progresses, the density of internal wires in the semiconductor device packages increases (or the pitch of the internal wires decreases). However, the underfill may ooze due to process limitations of manufacturing the underfill, and the oozed underfill requires a relatively large area of the substrate, which may hinder miniaturization of the semiconductor device package. In addition, the singulated paths may be occupied by oozed underfill, which may reduce the reliability of the semiconductor device package.

Disclosure of Invention

In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor apparatus is disposed on the substrate. The semiconductor device includes a first side. The underfill is disposed between the substrate and the semiconductor device. The underfill comprises a first side. The first side of the underfill is substantially coplanar with the first side of the semiconductor device.

In some embodiments, according to one aspect, a semiconductor device package includes a substrate, a first semiconductor device, a first underfill, a second semiconductor device, and a second underfill. The first semiconductor device is disposed on the substrate. The first semiconductor device includes a first side substantially perpendicular to the substrate. The first underfill is disposed between the substrate and the first semiconductor device. The first underfill comprises a first side substantially coplanar with the first side of the first semiconductor device. The second semiconductor device is disposed on the substrate. The second semiconductor device includes a first surface substantially perpendicular to the substrate. The second underfill is disposed between the substrate and the second semiconductor device. The second underfill comprises a first side that is substantially coplanar with the first side of the second semiconductor device. The first side of the first semiconductor device faces the first side of the second semiconductor device.

In some embodiments, according to another aspect, a method for manufacturing a semiconductor device package is disclosed. The method comprises the following steps: arranging a substrate with an electric connection structure; forming an alignment structure on the substrate; injecting a fluid on the substrate; bonding a semiconductor device to the substrate, the semiconductor device including an electrical connection structure; and disposing an underfill between the substrate and the semiconductor device, wherein at least one side of the underfill is formed against the alignment structure.

Drawings

Fig. 1A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1C illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 1D illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2A illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2B illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 2C illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 3 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 4 illustrates a cross-sectional view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5A illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5B illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5C illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 5D illustrates a top view of a semiconductor device package, according to some embodiments of the present disclosure.

Fig. 6A illustrates one type of carrier for a semiconductor package structure according to some embodiments of the present disclosure.

Fig. 6B illustrates one type of carrier for a semiconductor package structure according to some embodiments of the present disclosure.

Fig. 7A-7P illustrate methods of fabricating semiconductor device packages according to some embodiments of the present disclosure.

Detailed Description

Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions, such as "above," "below," "up," "left," "right," "down," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," "upper," "above," "below," and the like, are specified with respect to a component or group of components or a plane of a component or group of components for orienting one or more components as shown in the associated figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure are not necessarily offset by such arrangements.

Fig. 1A is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a substrate 10, a semiconductor device 12, an underfill 13, an encapsulant 14, and a conductive element 15.

The substrate 10 has an upper surface 101 and a lower surface 102 opposite the upper surface 101. the substrate 10 has sides 103 between the upper surface 101 and the lower surface 102. the substrate 10 has conductive pads 104 disposed on the upper surface 101 and conductive pads 106 disposed on the lower surface 102. the substrate 10 has interconnect elements 105 (e.g., vias) disposed between the conductive pads 104 and 106 to provide an electrical connection therebetween. for example, the conductive pads 104 are electrically connected to the conductive pads 106 via the interconnect elements 105. the substrate 10 may include one or more conductive layers. the substrate 10 may include a solder mask layer. the substrate 10 may be, for example, a Printed Circuit Board (PCB), such as a paper copper foil laminate, a composite copper foil laminate, a polymer impregnated fiberglass based copper foil laminate, or a combination of two or more thereof. the substrate 10 may include an interconnect structure, such as a redistribution layer (RD L).

The conductive elements 15 are disposed on the lower surface 102 of the substrate 10 the conductive elements 15 are disposed on the conductive pads 106 in some embodiments, the conductive elements 15 may be controlled collapse chip connection (C4) bumps, solder bumps, Ball Grid Arrays (BGAs), planar grid arrays (L GA), posts, or a combination of two or more thereof.

Semiconductor device 12 is disposed on an upper surface 101 of substrate 10. Semiconductor device 12 has a side 121 and a side 122 opposite side 121. The sides 121 and 122 of the semiconductor device 12 are substantially perpendicular to the upper surface 101 of the substrate 10. The semiconductor device 12 includes a conductive pad 123. The conductive pad 123 is electrically connected to the conductive pad 104. The semiconductor device 12 is a flip-chip type semiconductor device. Semiconductor device 12 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic component or semiconductor device.

An underfill 13 is disposed between the semiconductor device 12 and the substrate 10. The underfill 13 surrounds or covers the conductive pad 123 of the semiconductor device 12. Underfill 13 has a side 131 and a side 132 opposite side 131. The side 131 of the underfill 13 is substantially perpendicular to the upper surface 101 of the substrate 10. Side 131 of underfill 13 is substantially coplanar with side 121 of semiconductor device 12. Side 132 of underfill 13 partially covers side 122 of semiconductor device 12. Side 132 and side 122 are non-continuous. For example, side 132 is not coplanar with side 122. For example, side 132 is inclined relative to surface 122. For example, the side 132 and the upper surface 101 of the substrate 10 define an angle of less than 90 degrees.

In some embodiments, the horizontal distance D1 between side 103 of substrate 10 and side 121 of semiconductor device 12 is less than 0.5 mm. For example, the distance D1 may be 0.4mm, 0.3mm, 0.2mm, 0.1mm, or near zero. With this arrangement, the distance D1 can be precisely adjusted, and the area of the substrate 10 occupied by the underfill 13 can be reduced. The total area of the substrate 10 can be effectively utilized, which will contribute to miniaturization of the semiconductor device package 1. The underfill 13 has a thickness T1 extending from the active surface of the semiconductor device 12 to the upper surface 101 of the substrate 10. The thickness T1 is in the range of approximately 20 μm to 50 μm. The volume of underfill 13 used can be precisely controlled to a minimum volume, which will reduce manufacturing costs.

The encapsulant 14 is disposed on the upper surface 101 of the substrate 10. The encapsulant 14 encapsulates the semiconductor device 12 and the underfill 13. In some embodiments, the back side of the semiconductor device 12 may be completely covered by the encapsulant 14. In other embodiments, the backside of the semiconductor device 12 may be substantially coplanar with the upper surface of the encapsulant 14. For example, a backside of the semiconductor device 12 may be exposed from the encapsulant 14. The thickness of the enclosure 14 can be flexibly designed.

Fig. 1B is a cross-sectional view of a semiconductor device package 1' according to some embodiments of the present disclosure. The semiconductor device package 1' is similar to the semiconductor device package 1 in fig. 1A, except that the side 131' of the underfill 13' includes a vertical portion and an inclined portion. The vertical portion of side 131 'of underfill 13' is coplanar with side 121 of semiconductor device 12 and in contact with semiconductor device 12. The inclined portion of the side face 131 'of the underfill 13' is inclined outward in the direction from the semiconductor device 12 to the substrate 10.

The horizontal distance D2 between the left end of the underfill 13 'and the side 121 of the semiconductor device 12 is smaller than the horizontal distance D3 between the right end of the underfill 13' and the side 122 of the semiconductor device 12.

The appearance of the underfill 13' may be affected by alignment structures (not shown in fig. 1B). In some embodiments, the alignment structure may comprise a photosensitive material or other suitable material. The alignment structure may be a photoresist.

Fig. 1C is a cross-sectional view of a semiconductor device package 1 "according to some embodiments of the present disclosure. The semiconductor device package 1 "is similar to the semiconductor device package 1 in fig. 1A, except that the side 131" of the underfill 13 "includes a vertical portion and an inclined portion. The vertical portion of side 131 "of underfill 13" is coplanar with side 121 of semiconductor device 12 and in contact with semiconductor device 12. The inclined portions of the side faces 131 "of the underfill 13" are shrunk inwardly in the direction from the semiconductor device 12 to the substrate 10.

The appearance of the underfill 13 "may be affected by alignment structures (not shown in fig. 1C). In some embodiments, the alignment structure may comprise a photosensitive material or other suitable material. The alignment structure may be a photoresist.

Fig. 1D is a cross-sectional view of a semiconductor device package 1 "' according to some embodiments of the present disclosure. Semiconductor device package 1 "' is similar to semiconductor device package 1 of fig. 1A except that side 131" ' of underfill 13 "' is a sloped side. Side 131 "'of underfill 13"' is retracted inwardly in the direction from semiconductor device 12 to substrate 10.

The appearance of underfill 13' "may be affected by alignment structures (not shown in fig. 1D). In some embodiments, the alignment structure may comprise a photosensitive material or other suitable material. The alignment structure may be a photoresist.

Fig. 2A is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 includes a substrate 10, semiconductor devices 12 and 16, underfills 13 and 17, an encapsulant 14, and conductive elements 15.

The arrangement of the semiconductor device 12 and the underfill 13 is similar to that illustrated in fig. 1A. The arrangement of the semiconductor device 16 and the underfill 17 is similar to the arrangement of the semiconductor device 12 and the underfill 13.

The semiconductor device 16 is disposed on the upper surface 101 of the substrate 10. Semiconductor device 16 has a side 161 and a side 162 opposite side 161. The sides 161 and 162 of the semiconductor device 16 are substantially perpendicular to the upper surface 101 of the substrate 10. The semiconductor device 16 includes a conductive pad 163. The conductive pad 163 is electrically connected to the conductive pad 104. The semiconductor device 16 is a flip-chip type semiconductor device. The semiconductor device 16 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic components or semiconductor devices. Semiconductor device 16 may be different from or the same as semiconductor device 12.

An underfill 17 is disposed between the semiconductor device 16 and the substrate 10. The underfill 17 surrounds or covers the conductive pads 163 of the semiconductor device 16. Underfill 17 has a side 171 and a side 172 opposite side 171. The side 171 of the underfill 17 is substantially perpendicular to the upper surface 101 of the substrate 10. Side 171 of underfill 17 is substantially coplanar with side 161 of semiconductor device 16. Side 172 of underfill 17 partially covers side 162 of semiconductor device 16. Semiconductor device 16 may be disposed proximate to semiconductor device 12. Side 172 and side 162 are discontinuous. For example, side 172 is not coplanar with side 162. For example, side 172 is inclined relative to surface 162. For example, the side 172 and the upper surface 101 of the substrate 10 define an angle of less than 90 degrees.

The encapsulant 14 encapsulates the semiconductor device 12 and the underfill 13. The encapsulant 14 encapsulates the semiconductor device 16 and the underfill 17. In some embodiments, the backside of the semiconductor device 12 or 16 may be completely covered by the encapsulant 14. In other embodiments, the backside of the semiconductor device 12 and the backside of the semiconductor device 16 may be substantially coplanar with the upper surface of the enclosure 14. For example, the backside of semiconductor device 12 and the backside of semiconductor device 16 may be exposed from encapsulant 14. The thickness of the enclosure 14 can be flexibly designed. In some embodiments, the encapsulant 14 may be omitted.

Fig. 2B is a cross-sectional view of a semiconductor device package 2' according to some embodiments of the present disclosure. The semiconductor device package 2 'is similar to the semiconductor device package 2 in fig. 2A, except that the encapsulant 14' has a curved upper surface.

The enclosure 14' is formed by a potting operation. The encapsulant 14' encapsulates the semiconductor device 12 and the underfill 13. The encapsulant 14' encapsulates the semiconductor device 16 and underfill 17. In some embodiments, the material of the encapsulant 14' may be the same as the material of the underfill 13 and 17. The material of the encapsulant 14' may be different from the material of the underfills 13 and 17.

Fig. 2C is a cross-sectional view of a semiconductor device package 2 "according to some embodiments of the present disclosure. The semiconductor device package 2 "is similar to the semiconductor device package 2 in fig. 2A, except that the semiconductor device package 2" further includes a semiconductor device 18 and an underfill 19 disposed on the lower surface 102 of the substrate 10. The semiconductor device package 2 "is a double-sided package.

Semiconductor device 18 has a side 181 and a side 182 opposite side 181. Sides 181 and 182 of semiconductor device 18 are substantially perpendicular to lower surface 102 of substrate 10. Semiconductor device 18 includes conductive pads 183. The conductive pad 183 is electrically connected to the conductive pad 106. The semiconductor device 18 is a flip-chip type semiconductor device. Semiconductor device 18 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic component or semiconductor device. In some embodiments, semiconductor device 18 may be the same as semiconductor device 12 or 16. Semiconductor device 18 may be different from semiconductor devices 12 or 16.

An underfill 19 is disposed between the semiconductor device 18 and the substrate 10. The underfill 19 surrounds or covers the conductive pads 183 of the semiconductor device 18. The underfill 19 has a side 191 and a side 192 opposite the side 191. The sides 191 of the underfill 19 are substantially perpendicular to the lower surface 102 of the substrate 10. Side 191 of underfill 19 is substantially coplanar with side 181 of semiconductor device 18. Side 192 of underfill 19 partially covers side 182 of semiconductor device 18. Side 192 and side 182 are non-continuous. For example, side 192 is not coplanar with side 182. For example, side 192 is inclined relative to surface 182. For example, the side 192 and the lower surface 102 of the substrate 10 define an angle of less than 90 degrees.

Fig. 3 is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 contains the semiconductor device package 2' ″, the semiconductor devices 32 and 36, and the underfills 33 and 37. Semiconductor device package 2' ″ is similar to semiconductor device package 2 of fig. 2A, except that interconnect element 21 electrically connects conductive pads 104 to semiconductor devices 32 and 36. The semiconductor device package 3 is a multilayer package.

A semiconductor device 32 is disposed on the backside of the enclosure 14. The semiconductor device 32 has a side 321 and a side 322 opposite the side 321. The sides 321 and 322 of the semiconductor device 32 are substantially perpendicular to the backside of the encapsulant 14. The semiconductor device 32 includes a conductive pad 323. The conductive pad 323 is electrically connected to the conductive pad 104 via the interconnection element 21. The semiconductor device 32 is a flip-chip type semiconductor device. The semiconductor device 32 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic components or semiconductor devices.

An underfill 33 is disposed between the semiconductor device 32 and the encapsulant 14. The underfill 33 covers or surrounds the conductive pads 323 of the semiconductor device 32. The underfill 33 has a side 331 and a side 332 opposite the side 331. The side 331 of the underfill 33 is substantially perpendicular to the backside of the enclosure 14. The side 331 of the underfill 33 is substantially coplanar with the side 321 of the semiconductor device 32. Side 332 of underfill 33 partially covers side 322 of semiconductor device 32. Side 332 and side 322 are non-continuous. For example, side 332 is not coplanar with side 322. For example, side 332 is inclined relative to surface 322. For example, the side 332 and the upper surface of the enclosure 14 define an angle of less than 90 degrees.

Semiconductor device 36 has a side 361 and a side 362 opposite side 361. The underfill 37 has a side 371 and a side 372 opposite the side 371. The arrangement of the semiconductor device 36 and the underfill 37 is similar to that of the semiconductor device 32 and the underfill 33.

The encapsulant 34 is disposed on the backside of the encapsulant 14. The encapsulant 34 encapsulates the semiconductor device 32 and the underfill 33. The encapsulant 34 encapsulates the semiconductor device 36 and underfill 37. In some embodiments, the backside of the semiconductor devices 32 and 36 may be completely covered by the encapsulant 14. In other embodiments, the backside of the semiconductor devices 32 and 36 may be substantially coplanar with the upper surface of the encapsulant 34. For example, the backside of semiconductor devices 32 and 36 may be exposed from encapsulant 34. The thickness of the envelope 34 can be flexibly designed.

Fig. 4 is a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. Semiconductor device package 4 includes substrate 40, alignment structure 41, semiconductor devices 42 and 46, underfills 43 and 47, and encapsulant 44.

Substrate 40 has a conductive layer 407 adjacent to an upper surface of substrate 40. conductive layer 407 may be a patterned conductive layer. substrate 40 may have a conductive pad disposed on an upper surface of substrate 40. the conductive pad is electrically connected to conductive layer 407. substrate 40 may include a solder mask layer. substrate 40 may be, for example, a Printed Circuit Board (PCB), such as a paper copper foil laminate, a composite copper foil laminate, a polymer impregnated fiberglass-based copper foil laminate, or a combination of two or more thereof.

Semiconductor devices 42 are disposed on an upper surface of substrate 40. Semiconductor device 42 has a side 421 and a side 422 opposite side 421. Sides 421 and 422 of semiconductor device 42 are substantially perpendicular to the upper surface of substrate 40. Semiconductor device 42 includes conductive pad 423. Conductive pad 423 is electrically connected to conductive layer 407 via a conductive pad of substrate 40. The semiconductor device 42 is a flip-chip type semiconductor device. Semiconductor device 42 may include an Application Specific Integrated Circuit (ASIC), a controller, a processor, or other electronic component or semiconductor device.

An underfill 43 is disposed between the semiconductor device 42 and the substrate 40. The underfill 43 surrounds or covers the conductive pad 423 of the semiconductor device 42. The underfill 43 has a side 431 and a side 432 opposite the side 431. The side 431 of the underfill 43 is substantially perpendicular to the upper surface of the substrate 40. Side 431 of underfill 43 is substantially coplanar with side 421 of semiconductor device 42. Side 432 of underfill 43 partially covers side 422 of semiconductor device 42. Side 432 and side 422 are non-continuous. For example, side 432 is not coplanar with side 422. For example, side 432 is inclined relative to surface 422. For example, side 432 and upper surface 101 of substrate 10 define an angle of less than 90 degrees.

Semiconductor device 46 has a side 461 and a side 462 opposite side 461. The underfill 47 has a side 471 and a side 472 opposite the side 471. The arrangement of the semiconductor device 46 and the underfill 47 is similar to that of the semiconductor device 42 and the underfill 43. Side 421 of semiconductor device 42 faces side 461 of semiconductor device 46. Semiconductor device 42 and semiconductor device 46 are electrically connected to each other via conductive layer 407. The side 431 of the underfill 43 faces the side 471 of the underfill 47. In some embodiments, semiconductor device 42 may be the same as or different from semiconductor device 46.

An alignment structure 41 is disposed on an upper surface of the substrate 40. Alignment structure 41 is disposed between semiconductor device 42 and semiconductor device 46. The alignment structure 41 is in contact with the semiconductor device 42 and the underfill 43. The alignment structure 41 is in contact with the semiconductor device 46 and the underfill 47. In some embodiments, alignment structure 41 may comprise a photosensitive material or other suitable material. The alignment structure 41 may be a photoresist.

Alignment structure 41 has a width W1. The width W1 of the alignment structure 41 may be flexibly adjusted. Accordingly, semiconductor devices 42 and 46 may be disposed as close as possible to facilitate signal communication between semiconductor devices 42 and 46.

The encapsulant 44 encapsulates the semiconductor device 42 and the underfill 43. The encapsulant 44 encapsulates the semiconductor device 46 and the underfill 47. In some embodiments, the backside of semiconductor devices 42 and 46 may be completely covered by encapsulant 44. In other embodiments, the upper surface of alignment structure 41 may be substantially coplanar with the upper surface of encapsulant 44. In another embodiment, the upper surface of alignment structure 41 and the backside of semiconductor devices 42 and 46 may be substantially coplanar with the upper surface of encapsulant 44. With this arrangement of alignment structures 41, there will be no voids in the encapsulant 44.

In some embodiments, the structure of fig. 4 may be applied to a chip on fan-out substrate (FOCoS) structure. The structure of fig. 4 may be applied to a chip-last operation to avoid underfill bleed. Therefore, the distance between the two semiconductor devices can be shortened.

Fig. 5A is a top view of a semiconductor device package 5A according to some embodiments of the present disclosure. The semiconductor device package 5a has four units. Each cell includes a substrate 10, semiconductor devices 12 and 16, and underfills 13 and 17. Semiconductor devices 12 and 16 are symmetrical inward. The underfill 13 does not ooze out to the left and bottom sides of the semiconductor device 12. The underfill 17 does not ooze out to the right and bottom sides of the semiconductor device 16.

Fig. 5B is a top view of a semiconductor device package 5B according to some embodiments of the present disclosure. The semiconductor device package 5b is similar to the semiconductor device package 5A in fig. 5A except that the underfill 13 does not ooze to the right and bottom sides of the semiconductor device 12 and the underfill 17 does not ooze to the right and bottom sides of the semiconductor device 16.

Fig. 5C is a top view of a semiconductor device package 5C according to some embodiments of the present disclosure. The semiconductor device package 5c is similar to the semiconductor device package 5A in fig. 5A except that the underfill 13 does not ooze to the right and bottom sides of the semiconductor device 12 and the underfill 17 does not ooze to the left and bottom sides of the semiconductor device 16. The semiconductor devices 12 and 16 are outwardly symmetrical.

Fig. 5D is a top view of a semiconductor device package 5D according to some embodiments of the present disclosure. The semiconductor device package 5d has two units. Each cell includes a substrate 10, semiconductor devices 12 and 16, and underfills 13 and 17. The underfill 13 does not ooze out to the left and right sides of the semiconductor device 12. The underfill 17 does not ooze out to the left and right sides of the semiconductor device 16.

The two units may be separated from the predefined singulation path. The predefined singulation path has a width W2. The width W2 is in a range of approximately 60 μm to approximately 100 μm. The semiconductor device 12 is spaced apart from the predefined singulation path by a distance D1. The semiconductor device 16 is spaced apart from the predefined singulation path by a distance D1. The distance D1 is less than 0.5 mm.

Fig. 6A and 6B illustrate different types of semiconductor device packages according to some embodiments of the present disclosure.

As shown in fig. 6A, a plurality of chips 60 and/or dies are placed on a square carrier 61. In some embodiments, at least one of the chips 60 may include a semiconductor apparatus package 1, 1', 1 "', 2', 2", 3, 4, 5A, 5b, 5C, and/or 5D as shown in fig. 1A-1D, 2A-2C, 3, 4, and/or 5A-5D. In some embodiments, carrier 61 may comprise an organic material (e.g., molding compound, BT, PI, PBO, solder resist, ABF, PP, epoxy-based material, or a combination of two or more thereof) or an inorganic material (e.g., silicon, glass, ceramic, quartz, or a combination of two or more thereof).

As shown in fig. 6B, a plurality of chips 60 and/or dies are placed on a circular carrier 62. In some embodiments, at least one of the chips 60 may include a semiconductor apparatus package 1, 1', 1 "', 2', 2", 3, 4, 5A, 5b, 5C, and/or 5D as shown in fig. 1A-1D, 2A-2C, 3, 4, and/or 5A-5D. In some embodiments, the carrier 62 may comprise an organic material (e.g., molding compound, BT, PI, PBO, solder resist, ABF, PP, epoxy-based material, or a combination of two or more thereof) or an inorganic material (e.g., silicon, glass, ceramic, quartz, or a combination of two or more thereof).

Fig. 7A-7P illustrate some embodiments of methods of manufacturing a semiconductor device package 1 according to some embodiments of the present disclosure. The figures have been simplified to more clearly present aspects of the disclosure. The operations of the method of manufacturing the semiconductor device package 1 can be applied to the semiconductor device packages of fig. 1B, 1C, 1D, 2A, 2B, 2C, 3, and 4 in a similar manner.

Referring to fig. 7A, a method for manufacturing a semiconductor device package 1 includes providing a substrate 10. The conductive film 104' is formed on the upper surface of the substrate 10. The substrate 10 includes interconnect elements 105 and conductive pads 106 disposed on a lower surface of the substrate 10.

Referring to fig. 7B, a photoresist 71 is applied to the upper surface of the substrate 10. The photoresist 71 is patterned by a photolithography operation to form openings 71'. A conductive film 104 "is formed in the opening 71' by a plating operation. The conductive film 104 "is formed over the conductive film 104'.

Referring to fig. 7C, the photoresist 71 is removed. Subsequently, an etching operation is performed to form the conductive pad 104.

Referring to fig. 7D, a photoresist 71 is further applied to the upper surface of the substrate 10.

Referring to fig. 7E, a photoresist 71 is patterned by a photolithography operation to form an alignment structure 72. The alignment structure 72 comprises a photosensitive material. The sidewalls of the alignment structures 72 are substantially perpendicular to the upper surface of the substrate 10. In some embodiments, the appearance (e.g., sidewalls) of the alignment structures 72 may be affected by the lithography operation. For example, the appearance of the alignment structures 72 may be affected by different settings of the pre-cure or development of the lithography operation. The sidewalls of the alignment structure 72 may be sloped or partially sloped.

The alignment structure 72 may be located on or adjacent to the predefined singulation path to prevent the underfill from bleeding into the predefined singulation path. The design of the alignment structure 72 may shorten the distance between the two semiconductor devices, so that the area of the substrate 10 is effectively utilized. In some embodiments, the alignment structure 72 may be located at any desired location on the substrate 10.

Referring to fig. 7F, a fluid 73 is injected or potted onto the upper surface of the substrate 10. Fluid 73 is confined by alignment structure 72. The density of the fluid 73 is greater than the density of the die. Fluid 73 may comprise dibromomethane, diiodomethane, dichloroethane, thallium formate, or other suitable material.

Referring to fig. 7G, the substrate 10 is placed on the holder 70. Semiconductor device 12 is picked up and placed on fluid 73. The semiconductor device 12 has a conductive pad 123. The conductive pad 123 may serve as an electrical connection structure. The density of semiconductor device 12 is less than the density of fluid 73. Semiconductor device 12 floats on fluid 73. The semiconductor device 12 does not contact the conductive pad 104 of the substrate 10.

Referring to FIG. 7H, an enlarged view of the region bounded by the dashed lines in FIG. 7G is shown. The substrate 10 on the holder 70 is tilted. The semiconductor device 12 on the fluid 73 drifts toward and against the alignment structure 72 due to gravity. The conductive pads 123 (i.e., electrical connection structures) of the semiconductor device 12 are aligned with the conductive pads 104 of the substrate 10. The alignment structures 72 act as alignment elements to facilitate alignment of the conductive pads 123 of the semiconductor device 12 with the conductive pads 104 of the substrate 10.

The substrate 10 is further ultrasonically oscillated to ensure that the semiconductor device 12 drifts toward and against the alignment structure 72. The conductive pads 123 of the semiconductor device 12 are not in contact with the conductive pads 104 of the substrate 10.

Referring to fig. 7I, fluid 73 is removed. The conductive pads 123 of the semiconductor device 12 are in contact with the conductive pads 104 of the substrate 10. Subsequently, the pressing member 74 is provided on the semiconductor device 12. The semiconductor device 12 is bonded to the substrate 10 via pressure applied to the pressing member 74. The conductive pads 123 of the semiconductor device 12 are bonded to the conductive pads 104 of the substrate 10. While performing a thermal operation. In some embodiments, the thermal operation may be performed after the pressing operation described above.

The alignment structure 72 acts as a stop to support the semiconductor device 12 to prevent cracking of the conductive pads 123 of the semiconductor device 12 or the conductive pads 104 of the substrate 10.

Referring to fig. 7J, an underfill 13 is applied between the semiconductor device 12 and the substrate 10. The right sidewall of the underfill 13 is coplanar with the right sidewall of the semiconductor device 12. Since the substrate 10 is inclined, the underfill 13 is easily filled between the semiconductor device 12 and the substrate 10, and the volume of the left portion of the underfill 13 can be controlled to be as small as possible due to gravity.

Referring to fig. 7K, fluid 73 is further injected or potted onto the upper surface of substrate 10. Semiconductor device 16 is picked up and placed on fluid 73. The semiconductor device 16 has a conductive pad 163. The conductive pad 163 may serve as an electrical connection structure. The density of semiconductor device 16 is less than the density of fluid 73. Semiconductor device 16 floats on fluid 73. The semiconductor device 16 does not contact the conductive pad 104 of the substrate 10.

Referring to fig. 7L, which shows an enlarged view of the region bounded by the dashed lines in fig. 7K, the substrate 10 on the holder 70 is tilted, the semiconductor device 16 on the fluid 73 drifts toward and against the alignment structure 72 due to gravity, the conductive pads 163 (i.e., electrical connection structures) of the semiconductor device 16 align with the conductive pads 104 of the substrate 10, the alignment structure 72 acts as an alignment element to facilitate alignment of the conductive pads 163 of the semiconductor device 16 with the conductive pads 104 of the substrate 10.

The substrate 10 is further ultrasonically oscillated to ensure that the semiconductor device 16 drifts toward and against the alignment structure 72. The conductive pads 163 of the semiconductor device 16 are not in contact with the conductive pads 104 of the substrate 10.

Referring to fig. 7M, fluid 73 is removed. The pressing operation and the heating operation are performed in a manner similar to the performed operation of fig. 7I.

Referring to fig. 7N, an underfill 17 is applied between the semiconductor device 16 and the substrate 10. The left sidewall of the underfill 17 is coplanar with the left sidewall of the semiconductor device 16.

Referring to fig. 7O, the alignment structure 72 is removed. Subsequently, the encapsulant 14 is applied over the substrate 10. The encapsulant 14 encapsulates the semiconductor devices 12 and 16 and the underfills 13 and 17. Then, a singulation operation is performed via the predefined singulation path.

Referring to fig. 7P, the conductive elements 15 are formed on conductive pads 106 disposed on the lower surface of the substrate 10.

As used herein, and without further definition, the terms "substantially," "approximately," and "about" are used to describe and contemplate minor variations. When used in conjunction with an event or circumstance, the terms can encompass the occurrence of the event or circumstance specifically and the close approximation of the event or circumstance. For example, when used in conjunction with numerical values, the term can encompass a range of variation of less than or equal to ± 10% of the stated value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. The term "substantially coplanar" may mean that the two surfaces lie along the same plane within a few microns, for example within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to be limiting. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be a distinction between artistic renditions in this disclosure and actual devices. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation.