阅读说明：本技术 包括锚固结构的半导体封装 (Semiconductor package including anchor structure ) 是由 朴玟秀 于 2019-10-16 设计创作，主要内容包括：包括锚固结构的半导体封装。一种半导体封装包括封装基板以及安装在封装基板上的半导体芯片。封装基板包括信号凸块焊盘和锚固凸块焊盘,并且半导体芯片包括信号凸块和锚固凸块。信号凸块接合到信号凸块焊盘,锚固凸块被设置为与锚固凸块焊盘相邻,并且锚固凸块的底表面相对于封装基板的表面位于比锚固凸块焊盘的顶表面低的水平处。(A semiconductor package including an anchor structure. A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes signal bump pads and anchor bump pads, and the semiconductor chip includes signal bumps and anchor bumps. The signal bump is bonded to the signal bump pad, the anchor bump is disposed adjacent to the anchor bump pad, and a bottom surface of the anchor bump is located at a lower level than a top surface of the anchor bump pad with respect to a surface of the package substrate.)

1. A semiconductor package, comprising:

a package substrate including a signal bump pad and an anchor bump pad; and

a semiconductor chip mounted on the package substrate and including signal bumps and anchor bumps,

wherein the signal bump is bonded to the signal bump pad,

wherein the anchor bump is disposed adjacent to the anchor bump pad, and

wherein a bottom surface of the anchor bump is located at a lower level than a top surface of the anchor bump pad with respect to a surface of the package substrate.

2. The semiconductor package of claim 1, wherein the anchor bumps are disposed laterally offset with respect to the anchor bump pads.

3. The semiconductor package of claim 2, wherein a side surface of the anchor bump is in contact with a side surface of the anchor bump pad.

4. The semiconductor package of claim 2, wherein side surfaces of the anchor bumps are spaced apart from side surfaces of the anchor bump pads.

5. The semiconductor package of claim 1, wherein a side surface of the anchor bump overlaps 40% to 70% of a height of a side surface of the anchor bump pad.

6. The semiconductor package of claim 1, wherein a height of the anchor bumps is greater than a height of the signal bumps.

7. The semiconductor package of claim 1, wherein the semiconductor package,

wherein the signal bump includes a solder pattern bonded to the signal bump pad; and is

Wherein the anchor bump is not bonded to the anchor bump pad.

8. The semiconductor package of claim 7, wherein the semiconductor package,

wherein the anchor bump does not include a solder pattern bonded to the anchor bump pad.

9. The semiconductor package of claim 1, wherein the semiconductor package,

wherein the package substrate includes a substrate main body having a surface extending in a major axis direction and a minor axis direction; and is

Wherein the anchor bump pads are disposed on corner regions of a surface of the package substrate.

10. The semiconductor package of claim 9, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the semiconductor chip includes a chip body having a surface extending in the major axis direction and the minor axis direction;

wherein the anchor bump is provided on the chip body of the semiconductor chip, and the anchor bump is provided closer to an edge region of the surface of the chip body than the anchor bump pad in the long axis direction, and

wherein the anchor bump is disposed closer to an edge region of the surface of the substrate body than the anchor bump pad in the long axis direction.

11. The semiconductor package of claim 9, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the anchor bump pad has a width in the minor axis direction and a length in the major axis direction; and is

Wherein the width is greater than the length.

12. The semiconductor package of claim 9, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the package substrate further includes a solder resist layer disposed on the substrate body to selectively expose the signal bump pad and the anchor bump pad; and is

Wherein the anchor bump is configured to be inserted into a void space between the anchor bump pad and the solder resist layer.

13. The semiconductor package according to claim 12, wherein the empty space in which the anchor bump is provided is located above a region of the surface of the substrate body exposed through an opening of the solder resist layer.

14. The semiconductor package of claim 9, wherein the package substrate has a coefficient of thermal expansion that is greater than a coefficient of thermal expansion of the semiconductor die.

15. The semiconductor package according to claim 14, wherein the anchor bump pads are arranged to exert a pushing force on the anchor bumps in the long axis direction when the package substrate and the semiconductor chip thermally expand while the semiconductor chip is stacked on the package substrate.

16. A semiconductor package, comprising:

a package substrate configured to include a surface extending in a major axis direction and a minor axis direction, and configured to include signal bump pads and anchor bump pads disposed on the surface; and

a semiconductor chip mounted on the package substrate and including a signal bump adjacent to the signal bump pad and an anchor bump adjacent to the anchor bump pad,

wherein the anchor bump pad is disposed on a corner region of the surface, and

wherein the anchor bump is disposed closer to an edge region of the surface than the anchor bump pad in the long axis direction.

17. The semiconductor package of claim 16, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the signal bump is arranged to be bonded to the signal bump pad; and is

Wherein a portion of a side surface of the anchor bump overlaps at least a portion of a side surface of the anchor bump pad.

18. The semiconductor package of claim 17, wherein the anchor bumps are not bonded to the anchor bump pads.

19. The semiconductor package of claim 17, wherein a side surface of the anchor bump overlaps 40% to 70% of a height of a side surface of the anchor bump pad.

20. The semiconductor package of claim 17, wherein the semiconductor package,

wherein the thermal expansion coefficient of the packaging substrate is larger than that of the semiconductor chip; and is

Wherein the anchor bump pads are arranged to apply a pushing force to the anchor bumps in the long axis direction when the package substrate and the semiconductor chip thermally expand while the semiconductor chip is stacked on the package substrate.

21. The semiconductor package of claim 16, wherein a bottom surface of the anchor bump is located above the surface of the package substrate without contacting the package substrate.

22. The semiconductor package of claim 16, wherein a bottom surface of the anchor bump is in contact with the surface of the package substrate.

23. The semiconductor package of claim 16, wherein the height of the anchor bumps is greater than the height of the signal bumps.

24. The semiconductor package of claim 16, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the signal bump includes a solder pattern bonded to the signal bump pad; and is

Wherein the anchor bump does not include a solder pattern bonded to the anchor bump pad.

25. The semiconductor package of claim 16, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the anchor bump pad has a width in the minor axis direction and a length in the major axis direction; and is

Wherein the width is greater than the length.

26. The semiconductor package of claim 16, wherein the first and second semiconductor chips are mounted on the substrate,

wherein the package substrate further comprises a solder resist layer disposed on the surface of the package substrate to selectively expose the signal bump pads and the anchor bump pads; and is

Wherein the anchor bump is configured to be inserted into a void space between the anchor bump pad and the solder resist layer.

27. The semiconductor package of claim 26, wherein the empty space in which the anchor bump is disposed is located above a region of the surface exposed through an opening of the solder resist layer.

Technical Field

The present disclosure relates generally to semiconductor packages, and more particularly, to semiconductor packages including anchor structures.

Background

Generally, each semiconductor package may be configured to include a Printed Circuit Board (PCB) and a chip mounted on the PCB. The chip may be electrically connected to the PCB by connection members such as bumps or wires.

In the case of employing bumps as the connection members in the semiconductor package, the bumps may be formed on the chip and bump pads may be formed on the PCB. The bump and bump pad may then be bonded to each other using solder. Recently, the number of connection members employed in each semiconductor package has increased to provide a high-performance semiconductor package. Accordingly, much effort has been focused on developing and securing techniques for bonding bumps to bump pads.

Disclosure of Invention

According to an embodiment, a semiconductor package may include a package substrate and a semiconductor chip mounted on the package substrate. The package substrate may include signal bump pads and anchor bump pads, and the semiconductor chip includes signal bumps and anchor bumps. The signal bump is bonded to the signal bump pad, the anchor bump is disposed adjacent to the anchor bump pad, and a bottom surface of the anchor bump may be located at a lower level than a top surface of the anchor bump pad with respect to a surface of the package substrate.

According to another embodiment, a semiconductor package may include a package substrate and a semiconductor chip mounted on the package substrate. The package substrate may be configured to include a surface extending in a major axis direction and a minor axis direction, and to include signal bump pads and anchor bump pads disposed on the surface. The semiconductor chip may include a signal bump adjacent to the signal bump pad and an anchor bump adjacent to the anchor bump pad. The anchor bump pads may be disposed on corner regions of the surface, and the anchor bumps are disposed closer to edge regions of the surface than the anchor bump pads in the long axis direction.

Drawings

Fig. 1 is a plan view illustrating a package substrate of a semiconductor package according to an embodiment of the present disclosure.

FIG. 2 is a cross-sectional view taken along lines I-I ', II-II ', and III-III ' of FIG. 1.

Fig. 3 is a plan view illustrating a semiconductor chip of a semiconductor package according to an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view taken along lines IV-IV ', V-V ', and VI-VI ' of FIG. 3.

Fig. 5 is a plan view illustrating a semiconductor package according to an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view taken along lines VII-VII ', VIII-VIII ', and IX-IX ' of FIG. 5.

Fig. 7 is a schematic diagram illustrating a step of bonding a semiconductor chip to a package substrate in a manufacturing process of a semiconductor package according to an embodiment of the present disclosure.

Fig. 8 to 10 are cross-sectional views illustrating a bonding process of a package substrate and a semiconductor chip employed in a semiconductor package according to an embodiment of the present disclosure.

Fig. 11 is a block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment of the present disclosure; and

fig. 12 is a block diagram illustrating another electronic system including a semiconductor package according to an embodiment of the present disclosure.

Detailed Description

Terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to those of ordinary skill in the art to which the embodiments belong. If defined in detail, the terms may be construed according to the definition. Unless defined otherwise, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments belong.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to limit the elements themselves or to imply a particular order.

It will also be understood that when an element or layer is referred to as being "on," "over," "under," or "outside" another element or layer, it can be directly in contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between" or "adjacent" and "directly adjacent").

Spatially relative terms, such as "under", "lower", "above", "upper", "top", "bottom", and the like, may be used to describe a relationship of an element and/or feature to another element and/or feature (e.g., as shown in the figures). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Semiconductor packages may include electronic devices such as semiconductor chips. The semiconductor package may include one or more anchor structures. The semiconductor chips can be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a dicing process. The semiconductor chip may correspond to a memory chip, a logic chip (including an Application Specific Integrated Circuit (ASIC) chip), or a system on a chip (SoC). The memory chip may include a Dynamic Random Access Memory (DRAM) circuit, a Static Random Access Memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a Magnetic Random Access Memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include logic circuitry integrated on a semiconductor substrate. The semiconductor chip may be referred to as a semiconductor die according to its shape after the dicing process.

The semiconductor package may include a Printed Circuit Board (PCB) mounted with a semiconductor chip. The PCB may include at least one layer of an integrated circuit pattern and may be referred to as a package substrate in this specification. The package substrate may include connection means for communicating with the semiconductor chip. The connection means may be formed using a wire bonding technique or a flip chip bonding technique to bond the semiconductor chip to the package substrate.

The semiconductor package may be used in various communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems.

Like reference numerals refer to like elements throughout the specification. Even if a reference number is not mentioned or described with reference to one figure, the reference number may also be mentioned or described with reference to another figure. In addition, even if a reference numeral is not shown in one drawing, it may be mentioned or described with reference to another drawing.

In the present specification, the term "joined" may be used to describe a state in which an element is physically or chemically attached and fixed to another element by a material having adhesive strength. As an example, the signal bump being bonded to the signal bump pad may mean that the signal bump and the signal bump pad are attached to each other using a solder layer such that the signal bump is fixed to the signal bump pad.

In this specification, the term "contact" or "contact with … …" may be used to describe a state in which an element merely touches another element. As an example, the anchor bump contacting the anchor bump pad may mean that the anchor bump and the anchor bump pad only touch each other without using an adhesive material such as a solder layer. Thus, two elements in contact with each other can be more easily separated or disengaged from each other than two elements engaged with each other. The term "easy" may mean that a state (e.g., a contact state or a bonding state) between two elements is changed to another state by relatively low energy.

Fig. 1 is a plan view illustrating a package substrate 10 of a semiconductor package according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along lines I-I ', II-II ', and III-III ' of FIG. 1.

Referring to fig. 1 and 2, the package substrate 10 may include a substrate body 110, signal bump pads 122 disposed on the package substrate 10, and anchor bump pads 124 disposed on the package substrate 10. In addition, the package substrate 10 may further include a solder resist layer 130 disposed on the package substrate 10 to selectively expose the signal bump pads 122 and the anchor bump pads 124. For example, the package substrate 10 may be a Printed Circuit Board (PCB), an interposer, or a flexible PCB.

In an embodiment, the substrate body 110 may have a surface 110s extending in a direction parallel to a long axis (i.e., y-axis) and a direction parallel to a short axis (i.e., x-axis) the substrate body 110 may have a first length L1 in the long axis direction and a second length L2 in the short axis direction, furthermore, the substrate body 110 may have a central axis C10-y parallel to the long axis direction and may have a rectangular planar shape symmetrical with respect to the central axis C10-y the substrate body 110 may serve as an interconnection structure for electrically and signal-connecting a semiconductor chip (20 of fig. 3) to an external device, and thus, although not shown in fig. 1 and 2, circuit patterns of a plurality of layers and an insulating layer for electrically insulating the circuit patterns of the plurality of layers from each other may be provided in the substrate body 110.

The signal bump pads 122 and the anchor bump pads 124 may be disposed on the surface 110S of the substrate body 110. One of the signal bump pads 122 may be electrically connected to at least one of the circuit patterns of the plurality of layers. The signal bump pads 122 may be formed of a conductive material. For example, the signal bump pad 122 may include a copper material. The anchor bump pad 124 may be a dummy pad electrically insulated from a circuit pattern transmitting a signal. When the package substrate 10 thermally expands (see fig. 9), the anchor bump pads 124 may be sufficiently rigid to exert a force on the anchor bumps (224 of fig. 9). In an embodiment, the anchor bump pad 124 may be formed to include a metal material such as a copper material.

Referring to fig. 1, the signal bump pads 122 may be arranged in a direction parallel to the long axis on the area a1 of the surface 110S. The signal bump pads 122 may be arranged in at least two columns. The signal bump pads 122 may be arranged to be symmetrical with respect to the central axis C10-y. Each signal bump pad 122 may have a width "a 1" in a direction parallel to the short axis and may have a length "b 1" in a direction parallel to the long axis. In an embodiment, the width "a 1" in the minor axis direction may be greater than the length "b 1" in the major axis direction. For example, each of the signal bump pads 122 may be provided to have a stripe shape or a bar shape extending in the short axis direction.

As can be seen from the description of fig. 3, the width "a 1" of the signal bump pad 122 may be greater than the diameter "r 1" of the signal bump 222. Referring to fig. 2, the signal bump pad 122 may have a height "h 1" in a direction parallel to a z-axis corresponding to a normal of the surface 110S.

The anchor bump pads 124 may be disposed in corner regions a2, A3, a4, and a5, respectively, of the surface 110S. Accordingly, the anchor bump pads 124 may be disposed on an edge region of the surface 110S of the substrate body 110 to be farther from the central axis C10-y than the signal bump pads 122. The anchor bump pads 124 may be disposed symmetrically with respect to the central axis C10-y. Each of the anchor bump pads 124 may have a width "a 2" in the short axis direction and may have a length "b 2" in the long axis direction. In an embodiment, the width "a 2" in the minor axis direction may be greater than the length "b 2" in the major axis direction. For example, each anchor bump pad 124 may be provided to have a strip shape or a bar shape extending in the short axis direction. Referring to fig. 2, the anchor bump pad 124 may have a height "h 2" in a direction parallel to a z-axis corresponding to a normal of the surface 110S.

As can be seen from the description of fig. 3, the width "a 2" of the anchor bump pad 124 may be greater than the diameter "r 2" of the anchor bump 224. Therefore, even if misalignment between the anchor bump pad 124 and the anchor bump 224 occurs within a predetermined range, the possibility that the anchor bump pad 124 is placed in contact with the side surface of the anchor bump 224 may increase, as can be seen from the description of fig. 5 and 6. As a result, the anchor bump pads 124 may sufficiently exert force on the anchor bumps 224 when manufacturing the semiconductor package 30 shown in fig. 7 to 10. The word "predetermined" (e.g., predetermined range) as used herein with respect to a parameter means that the value of the parameter is determined prior to using the parameter in a process or algorithm. For some embodiments, the values of the parameters are determined before the process or algorithm begins. In other embodiments, the values of the parameters are determined during the process or algorithm but before the parameters are used in the process or algorithm.

In an embodiment, the width "a 2", length "b 2", and height "h 2" of the anchor bump pad 124 may be substantially equal to the width "a 1", length "b 1", and height "h 1" of the signal bump pad 122, respectively. In another embodiment, at least one of the width "a 2", the length "b 2", and the height "h 2" of the anchor bump pad 124 may be different from a corresponding one of the width "a 1", the length "b 1", and the height "h 1" of the signal bump pad 122.

Referring again to fig. 1 and 2, a solder resist layer 130 may be disposed on the surface 110S of the substrate body 110 to selectively expose the signal bump pads 122 and the anchor bump pads 124. The solder resist layer 130 may be provided to protect the substrate body 110. As shown in fig. 1, the solder resist layer 130 may be disposed to expose the signal bump pads 122 through openings or slits parallel to the long axis direction on the area a1 of the surface 110S. In addition, the solder resist layer 130 may be disposed to expose the anchor bump pads 124 on the corner regions a2, A3, a4, and a5 of the surface 110S.

Fig. 3 is a plan view illustrating a semiconductor chip 20 included in a semiconductor package according to an embodiment of the present disclosure. FIG. 4 is a cross-sectional view taken along lines IV-IV ', V-V ', and VI-VI ' of FIG. 3.

Referring to fig. 3 and 4, the semiconductor chip 20 may include a chip body 210, signal bumps 222 disposed on the chip body 210, and anchor bumps 224 disposed on the chip body 210.

In an embodiment, the chip body 210 may have a surface 210s extending in a major axis direction and a minor axis direction the chip body 210 may have a first length L3 in the major axis direction and a second length L4 in the minor axis direction furthermore, the chip body 210 may have a central axis C20-y parallel to the major axis direction and may have a rectangular planar shape symmetrical with respect to the central axis C20-y.

Although not shown in fig. 3 and 4, circuit patterns of a plurality of layers and an insulating layer for electrically insulating the circuit patterns of the plurality of layers from each other may be disposed in the chip body 210. The circuit patterns and the insulating layers of the plurality of layers may be various circuit patterns constituting the electronic device.

The signal bumps 222 and the anchor bumps 224 may be disposed on the surface 210S of the chip body 210. One of the signal bumps 222 may be electrically connected to at least one of the circuit patterns of the plurality of layers. The signal bumps 222 may be formed of a conductive material. Each signal bump 222 may include a bump body 222a and a solder pattern 222 b. In this case, the bump body 222a may include a copper material. The anchor bumps 224 may be dummy bumps electrically insulated from a circuit pattern transmitting a signal. When the package substrate 10 thermally expands, the anchor bumps 224 may be sufficiently rigid to accept the force from the anchor bump pads 124 and to exert sufficient force on the chip body 210 such that the semiconductor chip 20 is warped, as can be seen from the description of fig. 9. In an embodiment, the anchor bump 224 may be formed to include a metal material such as a copper material.

Referring to fig. 3, the signal bumps 222 may be arranged in a direction parallel to the long axis on the region B1 of the surface 210S. The signal bumps 222 may be arranged in at least two rows. The signal bumps 222 may be arranged at positions corresponding to the signal bump pads 122 (see fig. 5 and 6).

Referring to fig. 4, each signal bump 222 may include: a bump main body 222a provided to protrude from the surface 210S of the chip main body 210; and a solder pattern 222b disposed at an end of the bump main body 222a opposite to the chip main body 210. For example, the bump body 222a may have a pillar shape or a rod shape. In embodiments, the bump body 222a may have a circular shape, an elliptical shape, or a polygonal shape when viewed in a plan view. The solder pattern 222b may include a tin material, a silver material, a nickel material, or a combination including at least two thereof. The solder pattern 222b may have a hemispherical shape. In an embodiment, the solder pattern 222b may be formed by plating the bump body 222a with solder having a fixed form or a non-fixed form and by heating the solder to deform the solder. As shown in fig. 3, each signal bump 222 may be provided in a circular shape having a first diameter "r 1" in a plan view. As shown in fig. 4, the signal bump 222 may have a first height "h 3" from the surface 210S of the chip body 210.

The anchor tabs 224 may be disposed in corner regions B2, B3, B4, and B5, respectively, of the surface 210S. Accordingly, the anchor bumps 224 may be disposed on the edge regions of the surface 210S of the chip body 210 to be farther from the central axis C20-y than the signal bumps 222. The anchor tab 224 may be disposed symmetrically with respect to the central axis C20-y. In an embodiment, the anchor bumps 224 may be disposed to protrude from the surface 210S of the chip body 210. Each of the anchor lugs 224 may have a post shape or a rod shape. In embodiments, the anchor tab 224 may have a circular shape, an elliptical shape, or a polygonal shape when viewed in plan view. The anchor bumps 224 may be provided without any solder pattern.

As shown in fig. 3, each anchor tab 224 may be provided in a circular shape having a second diameter "r 2" in plan view. As shown in fig. 4, the anchor bumps 224 may have a second height "h 4" from the surface 210S of the chip body 210. In an embodiment, the second diameter "r 2" of the anchor bump 224 may be greater than the first diameter "r 1" of the signal bump 222. The second height "h 4" of the anchor bump 224 may be greater than the first height "h 3" of the signal bump 222. In some other embodiments, the second diameter "r 2" of the anchor bump 224 may be equal to or less than the first diameter "r 1" of the signal bump 222. In some other embodiments, the anchor tab 224 may be a post having an elliptical shape or a polygonal shape in plan view. In this case, the length of the anchor bump 224 in the major axis direction may be greater than the length of the signal bump 222 in the major axis direction, and the length of the anchor bump 224 in the minor axis direction may be greater than the length of the signal bump 222 in the minor axis direction.

Fig. 5 is a plan view illustrating a semiconductor package 30 according to an embodiment of the present disclosure. FIG. 6 is a cross-sectional view taken along lines VII-VII ', VIII-VIII ', and IX-IX ' of FIG. 5. The semiconductor package 30 of fig. 5 includes the package substrate 10 described with reference to fig. 1 and 2 and the semiconductor chip 20 described with reference to fig. 3 and 4 and mounted on the package substrate 10. Fig. 6 is a schematic cross-sectional view illustrating the semiconductor package 30 shown in fig. 5. As shown in fig. 5 and 6, in the semiconductor package 30, the semiconductor chip 20 may be bonded to the package substrate 10 using a flip chip bonding technique. The semiconductor package 30 shown in fig. 5 and 6 may be manufactured using the bonding process shown in fig. 7 to 10.

Referring to fig. 5 and 6, the signal bump 222 may be bonded to the signal bump pad 122 through a solder pattern 222 b. For example, the signal bumps 222 may at least partially overlap the respective signal bump pads 122 in the z-axis direction such that the signal bumps 222 are easily bonded to the signal bump pads 122 by the solder patterns 222 b.

The anchor bumps 224 may be disposed laterally adjacent to the anchor bump pads 124. As shown in fig. 5, the anchor bumps 224 may be disposed closer to an edge region of the surface 210S of the chip body 210 than the anchor bump pads 124 in the long axis direction. In an embodiment, the anchor bumps 224 may be disposed on the chip body 210 of the semiconductor chip 20, and the anchor bumps 224 may be disposed closer to an edge region of the surface 110S of the substrate body 110 of the package substrate 10. That is, the anchor bumps 224 may be disposed between the anchor bump pads 124 and the side surfaces of the chip body 210 in the long axis direction when viewed from a plan view. In an embodiment, the anchor bumps 224 may be disposed between the anchor bump pads 124 and the side surfaces of the substrate body 110 in the long axis direction when viewed from a plan view. The anchor bumps 224 may not include solder. Accordingly, the anchor bumps 224 may not bond to the anchor bump pads 124. As a result, the anchor bumps 224 may not be bonded to the anchor bump pads 124, but only contact or no contact with the anchor bump pads 124.

In an embodiment, the anchor bumps 224 may not overlap the anchor bump pads 124 in the vertical direction (i.e., in the z-axis direction), as shown in fig. 6. That is, the anchor bumps 224 may be inserted into the empty spaces between the solder resist layer 130 and the anchor bump pads 124. The empty space in which the anchor bump 224 is disposed may be located on a portion of the surface 110S exposed through the opening of the solder resist layer 130. As a result, the anchor bump 224 may be disposed laterally adjacent to the anchor bump pad 124, and when the surface 110S of the substrate body 110 is regarded as a reference level, the bottom surface 224S of the anchor bump 224 may be located at a lower level than the top surface 124S of the anchor bump pad 124. That is, the bottom surface 224S of the anchor bump 224 may be disposed closer to the surface 110S of the substrate body 110 than the top surface 124S of the anchor bump pad 124. In an embodiment, the bottom surface 224S of the anchor bump 224 may be located at a lower level relative to the surface 110S of the package substrate 10 than the top surface 124S of the anchor bump pad 124. The anchor bumps 224 may be disposed laterally offset from the anchor bump pads 124 in plan view. In an embodiment, the bottom surface 224S of the anchor bump 224 may be located above the surface 110S of the substrate body 110 without contacting the surface 110S of the substrate body 110. However, in some other embodiments, at least one of the plurality of bottom surfaces 224S of the anchor bump 224 may be in contact with the surface 110S of the substrate body 110.

In an embodiment, a portion of a side surface of any one of the anchor bumps 224 and a portion of a side surface of any one of the anchor bump pads 124 may overlap each other in a lateral direction (i.e., a y-axis direction) to provide an overlapping portion Hc. As shown in fig. 6, although the side surfaces of the anchor bumps 224 are in contact with the corresponding side surfaces of the anchor bump pads 124, the present disclosure is not limited thereto. For example, in some other implementations, at least one side surface of the anchor bump 224 may be spaced apart from a corresponding one of the side surfaces of the anchor bump pad 124. Even in the case where the side surfaces of the anchor bumps 224 are spaced apart from the corresponding side surfaces of the anchor bump pads 124, since the anchor bump pads 124 have to move and push the anchor bumps 224 to apply force to the anchor bumps 224 when the package substrate 10 thermally expands, the anchor bumps 224 may be disposed to be spaced apart from the anchor bump pads 124 by a predetermined distance less than a certain distance (see fig. 7 to 10).

In order for the anchor bump pads 124 to sufficiently apply force to the anchor bumps 224 through the overlapping portions Hc of the anchor bump pads 124, the side surfaces of each anchor bump 224 may be designed to cover or overlap 40% to 70% of the height of the side surface of the corresponding anchor bump pad 124. For example, if the height "h 2" of the anchor bump pad 124 is 10 microns, the overlap Hc may have a height of 4 to 7 microns.

As described above, according to the embodiment of the present disclosure, the signal bump pad 122 may maintain a state of contacting the signal bump 222. In contrast, the anchor bump pads 124 of the package substrate 10 may not be bonded to the anchor bumps 224 of the semiconductor chip 20. Thus, although each signal bump 222 includes a solder pattern, the anchor bumps 224 may not include any solder pattern. The anchor bump pads 124 may be disposed laterally offset with respect to the anchor bumps 224 such that the top surfaces 124S of the anchor bump pads 124 do not contact the bottom surfaces 224S of the anchor bumps 224. The anchor bumps 224 may be disposed closer to the side surfaces of the substrate body 110 than the anchor bump pads 124 in the long axis direction, and each anchor bump 224 may be disposed to cover or overlap at least a portion of the side surface of any one of the anchor bump pads 124. Accordingly, when a solder bonding process is performed to bond the signal bump 222 to the signal bump pad 122, the bonding reliability between the signal bump 222 and the signal bump pad 122 may be improved (see fig. 7 to 10).

Fig. 7 is a schematic diagram illustrating a step of bonding the semiconductor chip 20 to the package substrate 10 in a manufacturing process of the semiconductor package 30 according to an embodiment of the present disclosure. Fig. 8 to 10 are cross-sectional views illustrating a bonding process of the package substrate 10 and the semiconductor chip 20 employed in the semiconductor package 30 according to an embodiment of the present disclosure. In fig. 8 to 10, for ease and convenience of explanation, the signal bump pads 122 and the anchor bump pads 124 are shown adjacent to each other on the surface 110S of the substrate body 110 and the signal bumps 222 and the anchor bumps 224 are shown adjacent to each other on the surface 210S of the chip body 210.

Referring to fig. 7, a bonding process of the package substrate 10 and the semiconductor chip 20 may be performed in a reflow oven using the reflow chamber 400 and the transfer apparatus 500. The transfer device 500 may drive a pair of drive shafts 510 and 520 to move the transfer plate 530 in the direction M1. The bonding process may be performed by driving the transfer apparatus 500 such that the stacked structure 30i including the semiconductor chips 20 mounted on the package substrate 10 sequentially passes through the first to fourth sections T1, T2, T3 and T4, which are individually divided, in the reflow chamber 400.

Referring to fig. 8, the package substrate 10 described with reference to fig. 1 and 2 and the semiconductor chip 20 described with reference to fig. 3 and 4 may be provided. For example, the semiconductor chip 20 formed with the signal bump 222 including the solder pattern 222b may be provided. In an embodiment, the solder pattern 222b may be formed by plating the bump main body 222a with solder having a fixed form or a non-fixed form and by heating the solder and deforming the solder into a spherical shape. Subsequently, the semiconductor chip 20 may be stacked on the package substrate 10 such that the surface 210S of the semiconductor chip 20 faces the surface 110S of the package substrate 10, thereby providing a stacked structure 30 i. In the stacked structure 30i, the signal bumps 222 may be disposed to vertically overlap the respective signal bump pads 122, and the anchor bumps 224 may be disposed to be laterally offset with respect to the anchor bump pads 124 without vertically overlapping the anchor bump pads 124. As shown in fig. 8, the solder patterns 222b of the signal bumps 222 may be disposed to be in contact with the signal bump pads 122, respectively. The side surfaces of the anchor bumps 224 may be disposed to at least partially overlap the surfaces of the anchor bump pads 124 in the lateral direction (i.e., the y-axis direction). In this case, the semiconductor chip 20 may be stacked on the package substrate 10 such that the side surfaces of the anchor bumps 224 are physically spaced apart from the surfaces of the anchor bump pads 124 in the lateral direction (i.e., the y-axis direction), as shown in fig. 8. Even in this case, the anchor bumps 224 may be disposed to be spaced apart from the anchor bump pads 124 by a predetermined distance less than a certain distance in the lateral direction because the anchor bump pads 124 have to move and push the anchor bumps 224 to apply force to the anchor bumps 224 when the package substrate 10 is thermally expanded. In an embodiment, the bottom surface 224S of the anchor bump 224 may be spaced apart from the surface 110S of the substrate body 110.

Referring again to fig. 7, after the laminated structure 30i is loaded on the transfer plate 530 of the transfer apparatus 500, the laminated structure 30i may be moved in the direction M1 to pass through the first section T1. In the first section T1, the laminated structure 30i may be heated for performing the preheating step and the soaking step. For example, the laminated structure 30i may be heated from room temperature to an elevated temperature of 150 to 180 degrees celsius in the first section T1.

Subsequently, the laminated structure 30i may pass through the second section T2 of the reflow chamber 400. The second section T2 may be a first high temperature section, and the preheating step and the soaking step may be performed in the second section T2. For example, the laminated structure 30i may maintain a temperature of 150 to 180 degrees celsius in the second section T2. While the laminated structure 30i passes through the second section T2, the volatile components in the solder pattern 222b may be removed. In addition, while the stacked structure 30i passes through the second section T2, the flux of the solder pattern 222b may be activated to reduce the surface of the signal bump pad 122 for later bonding to the signal bump 222. Further, in the second section T2, the laminated structure 30i may be thermally stable at a temperature lower than the reflow temperature before the third section T3.

Referring to fig. 7 and 9, the laminated structure 30i may pass through the third section T3 of the reflow chamber 400. The third section T3 may be a second high temperature section, and the reflow step may be performed in the third section T3. In the third section T3, the laminated structure 30i may be heated to a temperature of 200 to 250 degrees celsius to melt the solder pattern 222 b. Accordingly, while the stacked structure 30i passes through the third section T3, the solder pattern 222b may flow to sufficiently contact the signal bump 222. As shown in fig. 9, the solder pattern 222b may flow from the signal bump 222 to the signal bump pad 122 to substantially form a wetting area on the signal bump 222 and the signal bump pad 122.

Referring to fig. 9, while the stacked structure 30i passes through the third section T3, the package substrate 10 and the semiconductor chip 20 may thermally expand due to heat provided in the reflow chamber 400. Generally, the package substrate 10 may mainly include a polymer material. Accordingly, the thermal expansion coefficient of the package substrate 10 may be greater than that of the semiconductor chip 20 mainly including a silicon material. Therefore, the package substrate 10 may expand more than the semiconductor chip 20 in the lateral directions E1 and E2. As shown in fig. 9, if the package substrate 10 is expanded, the anchor bump pads 124 may move in the lateral directions E1 and E2, compared to the anchor bump pads 124 shown in fig. 8. As a result of the expansion of the package substrate 10, the anchor bump pads 124 may sufficiently contact the anchor bumps 224 and may exert forces F1 and F2 on the anchor bumps 224 in the lateral directions E1 and E2. Since the anchor bump pads 124 are in contact with the anchor bumps 224, the forces F1 and F2 that push the anchor bumps 224 in the lateral directions E1 and E2 may be transmitted to the semiconductor chip 20 through the anchor bumps 224. Since the forces F1 and F2 are applied to the anchor bumps 224 fixed to the surface of the chip body 210 in the lateral directions E1 and E2, the semiconductor chip 20 may be warped by the forces F1 and F2. That is, the anchor bumps 224 receiving the forces F1 and F2 may generate a compressive force F210 in the z-axis direction that is applied to the semiconductor chip 20. Referring again to fig. 3, in the long axis direction, warpage deformation of the package substrate 10 may occur more seriously. Therefore, the force with which the anchor bump pad 124 presses against the anchor bump 224 can be strongly generated in the long axis direction.

Referring again to fig. 7, the laminated structure 30i may pass through a fourth section T4. In the fourth section T4, the laminated structure 30i may be cooled from the reflow temperature to room temperature. Referring again to fig. 9, while the laminated structure 30i passes through the fourth section T4, the solder pattern 222b melted in the third section T3 may be cured to form a solder joint portion. The compressive force F210 generated in the third section T3 may be maintained while the laminated structure 30i passes through the fourth section T4.

After the laminated structure 30i passes through the fourth section T4, the process of bonding the signal bump 222 to the signal bump pad 122 may be terminated. That is, after the stacked structure 30i is unloaded from the reflow chamber 400, the manufacture of the semiconductor package 30 may be completed, as shown in fig. 10. After the bonding process is terminated, the side surfaces of the anchor bumps 224 may be brought into contact with the corresponding side surfaces of the anchor bump pads 124 to maintain the contact state. However, in some other embodiments, the side surfaces of the anchor bumps 224 may be spaced apart from the side surfaces of the anchor bump pads 124 after the bonding process is terminated.

According to the above embodiments, a semiconductor package 30 may be provided, which includes the anchor bump 224 and the anchor bump pad 124 adjacent to the anchor bump 224. When the semiconductor chip 20 including the anchor bumps 224 is bonded to the package substrate 10 including the anchor bump pads 124, the anchor bump pads 124 may exert a pushing force on the anchor bumps 224 due to a difference between the thermal expansion coefficients of the semiconductor chip 20 and the package substrate 10. The pushing force applied to the anchor bumps 224 may generate a compressive force, thereby improving the bondability between the semiconductor chip 20 and the package substrate 10. Therefore, the reliability of the bonding between the semiconductor chip 20 and the package substrate 10 can be improved.

The anchor bump pads 124 and the anchor bumps 224 may be used to fix the position of the semiconductor chip 20 while a bonding process is performed to bond the semiconductor chip 20 to the package substrate 10. Referring to fig. 7 to 10, in the case where heat is conducted to the laminated structure 30i using the air convection phenomenon in the reflow chamber 400 including the first to fourth sections T1 to T4, the airflow in the reflow chamber 400 may apply various directional forces or various directional pressures to the laminated structure 30 i. In this case, if the anchor bump pads 124 and the anchor bumps 224 are not present, air pressure laterally applied to the stacked structure 30i may cause misalignment between the semiconductor chip 20 and the package substrate 10. However, according to embodiments, the anchor bump pads 124 and the anchor bumps 224 may act as hooks that prevent or mitigate the semiconductor chip 20 from sliding on the package substrate 10. Accordingly, the anchor bump pads 124 and the anchor bumps 224 may improve the bonding reliability between the semiconductor chip 20 and the package substrate 10.

Fig. 11 is a block diagram illustrating an electronic system including a memory card 7800 employing a semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include a semiconductor package according to an embodiment.

The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data is read out or stored data is stored in response to a read/write request from the host 7830.

Fig. 12 is a block diagram illustrating an electronic system 8710 including at least one of semiconductor packages according to an embodiment. The electronic system 8710 may include a controller 8711, an input/output unit 8712, and a memory 8713. The controller 8711, the input/output unit 8712, and the memory 8713 may be coupled to each other by a bus 8715 that provides a path for data movement.

In an embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include a semiconductor package according to an embodiment of the present disclosure. The input/output unit 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands, etc. to be executed by the controller 8711.

The memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 can also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be wired or wireless in type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.

If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 may be used in a communication system using a technology of CDMA (code division multiple access), GSM (global system for mobile communication), NADC (north american digital cellular), E-TDMA (enhanced time division multiple access), WCDAM (wideband code division multiple access), CDMA2000, L TE (long term evolution), or Wibro (wireless broadband internet).

Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims.

Cross Reference to Related Applications

The present application claims priority from korean application No.10-2019-0013107, filed on 31/1/2019, which is incorporated herein by reference in its entirety.