阅读说明：本技术 反熔丝结构的制造方法及反熔丝结构 (Manufacturing method of anti-fuse structure and anti-fuse structure ) 是由 不公告发明人 于 2018-09-10 设计创作，主要内容包括：本发明提供了一种反熔丝结构的制造方法及反熔丝结构,执行第一离子注入工艺,在隔离结构圈起的衬底中形成功能阱及第一底部隔离阱,功能阱自衬底上表面延伸至衬底中,第一底部隔离阱同图形位于功能阱的下方,执行第二离子注入工艺,在与第一离子注入工艺图案互补的衬底中形成侧部隔离阱及第二底部隔离阱,侧部隔离阱自衬底上表面延伸至衬底中并包覆隔离结构,第二底部隔离阱同图形位于侧部隔离阱的下方,第一底部隔离阱、侧部隔离阱和第二底部隔离阱属于相同离子注入类型,和功能阱分属不同离子注入类型,第一底部隔离阱和第二底部隔离阱相连成底部隔离阱组合层,由此能够通过较少的掩膜工艺形成反熔丝结构,从而能够降低反熔丝结构的制造成本。(The invention provides a manufacturing method of an anti-fuse structure and the anti-fuse structure, a first ion implantation process is executed, a functional well and a first bottom isolation well are formed in a substrate encircled by an isolation structure, the functional well extends into the substrate from the upper surface of the substrate, the first bottom isolation well and a pattern are positioned below the functional well, a second ion implantation process is executed, a side isolation well and a second bottom isolation well are formed in the substrate which is complementary to the pattern of the first ion implantation process, the side isolation well extends into the substrate from the upper surface of the substrate and covers the isolation structure, the second bottom isolation well and the pattern are positioned below the side isolation well, the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type and belong to different ion implantation types, the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer, therefore, the anti-fuse structure can be formed by less mask processes, and the manufacturing cost of the anti-fuse structure can be reduced.)

1. A method of fabricating an antifuse structure, comprising:

providing a substrate, wherein a plurality of isolation structures are formed in the substrate, the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are annular and encircle part of the substrate;

executing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure respectively, wherein the functional well extends from the upper surface of the substrate to the substrate, the first bottom isolation well is positioned below the functional well in the same pattern, and the functional well and the first bottom isolation well belong to different ion implantation types respectively;

executing a second ion implantation process, including forming a lateral isolation well and a second bottom isolation well in the substrate which is complementary to the first ion implantation process pattern, respectively, wherein the lateral isolation well extends from the upper surface of the substrate into the substrate and wraps the isolation structure to isolate the adjacent functional wells, the second bottom isolation well and the pattern are located below the lateral isolation well, the first bottom isolation well, the lateral isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

an antifuse is formed over the functional well.

2. The method of claim 1, wherein performing a first ion implantation process comprises:

performing a first step of a first ion implantation process under a first mask to form one of the functional well and the first bottom isolation well in the substrate; and

continuing under the first mask, a second step of a first ion implantation process is performed to form the other of the functional well and the first bottom isolation well in the substrate.

3. The method of claim 2, wherein the functional well is formed with an ion implantation energy of 70 Kev-150 Kev and an ion implantation dose of 1e 12-5 e 13; the ion implantation energy for forming the first bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

4. The method of claim 1, wherein performing a second ion implantation process comprises:

performing a first step of a second ion implantation process under the second mask to form one of the side isolation well and the second bottom isolation well in the substrate; and

continuing under the second mask, a second step of a second ion implantation process is performed to form the other of the side isolation well and the second bottom isolation well in the substrate.

5. The method of claim 4, wherein the side isolation well is formed with an ion implantation energy of 70 Kev-150 Kev and an ion implantation dose of 1e 12-5 e 13; the ion implantation energy for forming the second bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

6. The method of manufacturing an antifuse structure of claim 1, wherein the functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

7. The method for manufacturing an antifuse structure according to any one of claims 1 to 6, wherein a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well;

the method for forming the antifuse on the functional well comprises the following steps:

forming an anti-fuse active region in the functional well, the anti-fuse active region extending from the functional well upper surface into the functional well; and

and forming a conductive layer on the dielectric layer, wherein the conductive layer and the anti-fuse active region are separated by the part of the dielectric layer covered under the conductive layer, so that the anti-fuse is formed by the anti-fuse active region, the separated part of the dielectric layer and the conductive layer.

8. The method of claim 7, wherein the dielectric layer has a thickness of less than 40 angstroms.

9. The method of manufacturing an antifuse structure according to claim 7, wherein the antifuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer and extends over portions of the side isolation wells.

10. The method of fabricating an antifuse structure of claim 7, wherein after forming the antifuse, the method of fabricating the antifuse structure further comprises:

forming a contact in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the conductive layer footprint into the antifuse active region.

11. An antifuse structure, comprising:

a substrate having a plurality of isolation structures formed therein, the isolation structures extending from an upper surface of the substrate into the substrate, the isolation structures being annular and enclosing a portion of the substrate;

a functional well formed in the substrate enclosed by the isolation structure, the functional well extending from the upper surface of the substrate into the substrate;

the first bottom isolation trap is formed in the substrate encircled by the isolation structure, and the first bottom isolation trap is positioned below the functional trap in the same pattern, wherein the functional trap and the first bottom isolation trap are respectively of different ion implantation types;

a lateral isolation well formed in the substrate in a complementary manner to the functional well pattern, the lateral isolation well extending from the upper surface of the substrate into the substrate and encapsulating the isolation structure to isolate adjacent functional wells;

a second bottom isolation well formed in the substrate, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

an antifuse formed over the functional well.

12. The antifuse structure of claim 11, wherein the functional well and the side isolation well are the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well are the same depth in the substrate.

13. The antifuse structure of claim 11, wherein a dielectric layer is formed over the substrate, the dielectric layer overlying the functional well; the antifuse includes:

an anti-fuse active region formed in the functional well, the anti-fuse active region extending into the functional well from the functional well upper surface;

a conductive layer formed on the dielectric layer and covering a portion under the conductive layer to space the conductive layer and the antifuse active region; and

the dielectric layer is spaced at a spacing portion between the conductive layer and the antifuse active region.

14. The antifuse structure of claim 13, wherein the dielectric layer is less than 40 angstroms thick.

15. The antifuse structure of claim 13, wherein the conductive layer extends over a portion of the side isolation well.

16. The antifuse structure of any one of claims 13 to 15, further comprising a contact formed in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the footprint of the conductive layer into the antifuse active region.

17. A method of fabricating an antifuse structure, comprising:

providing a substrate, wherein a plurality of isolation structures are formed in the substrate, the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are annular and encircle part of the substrate;

executing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure respectively, wherein the functional well extends from the upper surface of the substrate to the substrate, the first bottom isolation well is positioned below the functional well in the same pattern, and the functional well and the first bottom isolation well belong to different ion implantation types respectively;

performing a second ion implantation process, including forming a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer for isolating the functional wells; and

an antifuse is formed over the functional well.

18. The method of fabricating an antifuse structure of claim 17, wherein the second bottom isolation well covers an inner sidewall of the isolation structure.

19. The method of fabricating an antifuse structure of claim 17, wherein the first bottom isolation well and the second bottom isolation well are the same depth in the substrate.

20. The method of claim 17, wherein performing a first ion implantation process comprises:

performing a first step of a first ion implantation process under a first mask to form one of the functional well and the first bottom isolation well in the substrate; and

continuing under the first mask, a second step of a first ion implantation process is performed to form the other of the functional well and the first bottom isolation well in the substrate.

21. The method of claim 20, wherein the functional well is formed with an ion implantation energy of 70Kev to 150Kev and an ion implantation dose of 1e12 to 5e 13; the ion implantation energy for forming the first bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

22. The method of any of claims 17-21, wherein a dielectric layer is formed over the substrate, the dielectric layer covering the functional well;

the method for forming the antifuse on the functional well comprises the following steps:

forming an anti-fuse active region in the functional well, the anti-fuse active region extending from the functional well upper surface into the functional well; and

and forming a conductive layer on the dielectric layer, wherein the conductive layer and the anti-fuse active region are separated by the part of the dielectric layer covered under the conductive layer, so that the anti-fuse is formed by the anti-fuse active region, the separated part of the dielectric layer and the conductive layer.

23. The method of claim 22, wherein the dielectric layer has a thickness of less than 40 angstroms.

24. The method of manufacturing an antifuse structure of claim 22, wherein the antifuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer and extends over a portion of the second bottom isolation well.

25. The method of fabricating an antifuse structure of claim 22, wherein after forming the antifuse, the method of fabricating the antifuse structure further comprises:

forming a contact in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the conductive layer footprint into the antifuse active region.

26. An antifuse structure, comprising:

a substrate having a plurality of isolation structures formed therein, the isolation structures extending from an upper surface of the substrate into the substrate, the isolation structures being annular and enclosing a portion of the substrate;

a functional well formed in the substrate enclosed by the isolation structure, the functional well extending from the upper surface of the substrate into the substrate;

the first bottom isolation trap is formed in the substrate encircled by the isolation structure, and the first bottom isolation trap is positioned below the functional trap in the same pattern, wherein the functional trap and the first bottom isolation trap are respectively of different ion implantation types;

a second bottom isolation well formed in the substrate in a pattern complementary to the functional well, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer for isolating the functional wells; and

an antifuse formed over the functional well.

27. The antifuse structure of claim 26, wherein the second bottom isolation well covers an inner sidewall of the isolation structure.

28. The antifuse structure of claim 26, wherein the first bottom isolation well and the second bottom isolation well are the same depth in the substrate.

29. The antifuse structure of claim 26, wherein a dielectric layer is formed over the substrate, the dielectric layer overlying the functional well; the antifuse includes:

an anti-fuse active region formed in the functional well, the anti-fuse active region extending into the functional well from the functional well upper surface;

a conductive layer formed on the dielectric layer and covering a portion under the conductive layer to space the conductive layer and the antifuse active region; and

the dielectric layer is spaced at a spacing portion between the conductive layer and the antifuse active region.

30. The antifuse structure of claim 29, wherein the dielectric layer is less than 40 angstroms thick.

31. The antifuse structure of claim 29, wherein the conductive layer extends over a portion of the second bottom isolation well.

32. The antifuse structure of any one of claims 29 to 31, further comprising a contact formed in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the overlying region of the conductive layer into the antifuse active region.

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing an antifuse structure and an antifuse structure.

Background

When at least one unit cell in the semiconductor device is defective or malfunctioning in a manufacturing process, the semiconductor device cannot be used as a memory device. The memory having at least one defective unit cell is classified as a defective product and causes a reduction in production efficiency. Accordingly, techniques have been developed to replace defective cells with redundant cells to repair defective cells in a memory device. For example, one type of memory circuit includes a Dynamic Random Access Memory (DRAM) array of memory cells arranged in rows and columns, each of which is addressable for storing bits of information. If a defective cell is detected in a test operation after the memory device is manufactured, a write operation is performed in an internal circuit of the memory device to replace the defective cell with a redundant cell.

Currently, the selection of the redundancy unit is mainly achieved by designing a fuse structure and/or an antifuse structure in the memory. The method for repairing the semiconductor device by the fuse structure is to perform a writing repair process at a wafer level, and cannot be applied to a packaged semiconductor device, and as the integration degree of the semiconductor gradually increases, the fuse structure is limited by the spot size of a laser beam, so that the existing repair method has more choices for the anti-fuse structure.

The antifuse structure is repaired in such a way that it is normally non-conductive (high resistance) when not written, and becomes conductive when the voltage applied across it exceeds a certain value. The unwritten antifuse is equivalent to a capacitor, and the current is extremely small or zero when the read operation is carried out; the written antifuse is equivalent to a resistor, and the current increases significantly when a read operation is performed. The antifuse structure selectively connects portions of the circuit together so that previously unconnected devices can be used in the circuit to complete a repair process.

In the prior art, the manufacturing cost of the antifuse structure is high, so that how to reduce the manufacturing cost of the antifuse structure is a problem which is always solved by the technical personnel in the field.

Disclosure of Invention

The present invention provides a method for manufacturing an antifuse structure and an antifuse structure, so as to solve the problem of high manufacturing cost of the antifuse structure in the prior art.

In order to solve the above technical problem, the present invention provides a method for manufacturing an antifuse structure, comprising:

providing a substrate, wherein a plurality of isolation structures are formed in the substrate, the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are annular and encircle part of the substrate;

executing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure respectively, wherein the functional well extends from the upper surface of the substrate to the substrate, the first bottom isolation well is positioned below the functional well in the same pattern, and the functional well and the first bottom isolation well belong to different ion implantation types respectively;

executing a second ion implantation process, including forming a lateral isolation well and a second bottom isolation well in the substrate which is complementary to the first ion implantation process pattern, respectively, wherein the lateral isolation well extends from the upper surface of the substrate into the substrate and wraps the isolation structure to isolate the adjacent functional wells, the second bottom isolation well and the pattern are located below the lateral isolation well, the first bottom isolation well, the lateral isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

an antifuse is formed over the functional well.

Optionally, in the manufacturing method of the antifuse structure, the performing of the first ion implantation process includes the following steps:

performing a first step of a first ion implantation process under a first mask to form one of the functional well and the first bottom isolation well in the substrate; and

continuing under the first mask, a second step of a first ion implantation process is performed to form the other of the functional well and the first bottom isolation well in the substrate.

Optionally, in the manufacturing method of the antifuse structure, the ion implantation energy for forming the functional well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e 13; the ion implantation energy for forming the first bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

Optionally, in the manufacturing method of the antifuse structure, the performing of the second ion implantation process includes the following steps:

performing a first step of a second ion implantation process under the second mask to form one of the side isolation well and the second bottom isolation well in the substrate; and

continuing under the second mask, a second step of a second ion implantation process is performed to form the other of the side isolation well and the second bottom isolation well in the substrate.

Optionally, in the manufacturing method of the antifuse structure, the ion implantation energy for forming the side isolation well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e 13; the ion implantation energy for forming the second bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

Optionally, in the manufacturing method of the antifuse structure, the functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

Optionally, in the manufacturing method of the antifuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well;

the method for forming the antifuse on the functional well comprises the following steps:

forming an anti-fuse active region in the functional well, the anti-fuse active region extending from the functional well upper surface into the functional well; and

and forming a conductive layer on the dielectric layer, wherein the conductive layer and the anti-fuse active region are separated by the part of the dielectric layer covered under the conductive layer, so that the anti-fuse is formed by the anti-fuse active region, the separated part of the dielectric layer and the conductive layer.

Optionally, in the manufacturing method of the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

Optionally, in the manufacturing method of the antifuse structure, the antifuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer and extends over portions of the side isolation wells.

Optionally, in the manufacturing method of the antifuse structure, after the antifuse is formed, the manufacturing method of the antifuse structure further includes:

forming a contact in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the conductive layer footprint into the antifuse active region.

The present invention also provides an antifuse structure, comprising:

a substrate having a plurality of isolation structures formed therein, the isolation structures extending from an upper surface of the substrate into the substrate, the isolation structures being annular and enclosing a portion of the substrate;

a functional well formed in the substrate enclosed by the isolation structure, the functional well extending from the upper surface of the substrate into the substrate;

the first bottom isolation trap is formed in the substrate encircled by the isolation structure, and the first bottom isolation trap is positioned below the functional trap in the same pattern, wherein the functional trap and the first bottom isolation trap are respectively of different ion implantation types;

a lateral isolation well formed in the substrate in a complementary manner to the functional well pattern, the lateral isolation well extending from the upper surface of the substrate into the substrate and encapsulating the isolation structure to isolate adjacent functional wells;

a second bottom isolation well formed in the substrate, the second bottom isolation well being located below the side isolation well in the same pattern, wherein the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer; and

an antifuse formed over the functional well.

Optionally, in the antifuse structure, the functional well and the side isolation well have the same depth in the substrate, and the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

Optionally, in the antifuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the antifuse includes:

an anti-fuse active region formed in the functional well, the anti-fuse active region extending into the functional well from the functional well upper surface;

a conductive layer formed on the dielectric layer and covering a portion under the conductive layer to space the conductive layer and the antifuse active region; and

the dielectric layer is spaced at a spacing portion between the conductive layer and the antifuse active region.

Optionally, in the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

Optionally, in the antifuse structure, the conductive layer extends to cover a portion of the side isolation well.

Optionally, in the antifuse structure, the antifuse structure further includes a contact formed in the antifuse active region, and the contact extends from an upper surface portion of the antifuse active region outside the coverage area of the conductive layer into the antifuse active region.

The invention also provides a manufacturing method of the anti-fuse structure, which comprises the following steps:

providing a substrate, wherein a plurality of isolation structures are formed in the substrate, the isolation structures extend from the upper surface of the substrate into the substrate, and the isolation structures are annular and encircle part of the substrate;

executing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure respectively, wherein the functional well extends from the upper surface of the substrate to the substrate, the first bottom isolation well is positioned below the functional well in the same pattern, and the functional well and the first bottom isolation well belong to different ion implantation types respectively;

performing a second ion implantation process, including forming a second bottom isolation well in the substrate complementary to the first ion implantation process pattern, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer for isolating the functional wells; and

an antifuse is formed over the functional well.

Optionally, in the manufacturing method of the antifuse structure, the second bottom isolation well covers an inner sidewall of the isolation structure.

Optionally, in the manufacturing method of the antifuse structure, the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

Optionally, in the manufacturing method of the antifuse structure, the performing of the first ion implantation process includes the following steps:

performing a first step of a first ion implantation process under a first mask to form one of the functional well and the first bottom isolation well in the substrate; and

continuing under the first mask, a second step of a first ion implantation process is performed to form the other of the functional well and the first bottom isolation well in the substrate.

Optionally, in the manufacturing method of the antifuse structure, the ion implantation energy for forming the functional well is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e 13; the ion implantation energy for forming the first bottom isolation trap is between 80Kev and 200Kev, and the ion implantation dosage is between 1e12 and 5e 13.

Optionally, in the manufacturing method of the antifuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well;

the method for forming the antifuse on the functional well comprises the following steps:

forming an anti-fuse active region in the functional well, the anti-fuse active region extending from the functional well upper surface into the functional well; and

and forming a conductive layer on the dielectric layer, wherein the conductive layer and the anti-fuse active region are separated by the part of the dielectric layer covered under the conductive layer, so that the anti-fuse is formed by the anti-fuse active region, the separated part of the dielectric layer and the conductive layer.

Optionally, in the manufacturing method of the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

Optionally, in the manufacturing method of the antifuse structure, the antifuse active region is formed by performing an ion implantation process on the functional well; the conductive layer is formed by depositing polysilicon on the dielectric layer and extends over a portion of the second bottom isolation well.

Optionally, in the manufacturing method of the antifuse structure, after the antifuse is formed, the manufacturing method of the antifuse structure further includes:

forming a contact in the antifuse active region, the contact extending from an upper surface portion of the antifuse active region outside the conductive layer footprint into the antifuse active region.

The present invention also provides an antifuse structure, comprising:

a substrate having a plurality of isolation structures formed therein, the isolation structures extending from an upper surface of the substrate into the substrate, the isolation structures being annular and enclosing a portion of the substrate;

a functional well formed in the substrate enclosed by the isolation structure, the functional well extending from the upper surface of the substrate into the substrate;

the first bottom isolation trap is formed in the substrate encircled by the isolation structure, and the first bottom isolation trap is positioned below the functional trap in the same pattern, wherein the functional trap and the first bottom isolation trap are respectively of different ion implantation types;

a second bottom isolation well formed in the substrate in a pattern complementary to the functional well, the second bottom isolation well extending from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, wherein the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer for isolating the functional wells; and

an antifuse formed over the functional well.

Optionally, in the antifuse structure, the second bottom isolation well covers an inner sidewall of the isolation structure.

Optionally, in the antifuse structure, the first bottom isolation well and the second bottom isolation well have the same depth in the substrate.

Optionally, in the antifuse structure, a dielectric layer is formed on the substrate, and the dielectric layer covers the functional well; the antifuse includes:

an anti-fuse active region formed in the functional well, the anti-fuse active region extending into the functional well from the functional well upper surface;

a conductive layer formed on the dielectric layer and covering a portion under the conductive layer to space the conductive layer and the antifuse active region; and

the dielectric layer is spaced at a spacing portion between the conductive layer and the antifuse active region.

Optionally, in the antifuse structure, the thickness of the dielectric layer is less than 40 angstroms.

Optionally, in the antifuse structure, the conductive layer extends to cover a portion of the second bottom isolation well.

Optionally, in the antifuse structure, the antifuse structure further includes a contact formed in the antifuse active region, and the contact extends from an upper surface portion of the antifuse active region outside the coverage area of the conductive layer into the antifuse active region.

In the manufacturing method of the anti-fuse structure and the anti-fuse structure provided by the invention, by executing a first ion implantation process, a functional well and a first bottom isolation well are respectively formed in the substrate encircled by the isolation structure, the functional well extends from the upper surface of the substrate to the substrate, the first bottom isolation well and a pattern are respectively positioned below the functional well, wherein the functional well and the first bottom isolation well belong to different ion implantation types, and by executing a second ion implantation process, a side isolation well and a second bottom isolation well are respectively formed in the substrate which is complementary to the first ion implantation process pattern, the side isolation well extends from the upper surface of the substrate to the substrate and covers the isolation structure to isolate the adjacent functional wells, and the second bottom isolation well and the pattern are positioned below the side isolation wells, the first bottom isolation well, the side isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer, so that the anti-fuse structure can be formed through less mask processes, and the manufacturing cost of the anti-fuse structure can be reduced.

Drawings

FIG. 1 is a schematic cross-sectional view of a substrate provided in a method of fabricating an antifuse structure.

Fig. 2 is a schematic cross-sectional view of the structure shown in fig. 1 after a first ion implantation process is performed thereon.

Fig. 3 is a schematic cross-sectional view of the structure shown in fig. 2 after a second ion implantation process is performed thereon.

Fig. 4 is a schematic cross-sectional view of the structure shown in fig. 3 after a third ion implantation process is performed thereon.

Fig. 5 is a cross-sectional view of the structure shown in fig. 4 after forming an antifuse thereon.

Fig. 6 is a schematic cross-sectional view of a substrate provided in a method of manufacturing an antifuse structure according to an embodiment of the present invention.

Fig. 7 is a cross-sectional view of the structure shown in fig. 6 after a first ion implantation process is performed thereon.

Fig. 8 is a schematic cross-sectional view of the structure shown in fig. 7 after a second ion implantation process has been performed thereon.

Fig. 9 is a schematic cross-sectional view of the structure shown in fig. 8 after forming an antifuse thereon.

Fig. 10 is a schematic cross-sectional view of a substrate provided in a method of fabricating an antifuse structure according to an embodiment of the present invention.

Fig. 11 is a cross-sectional view of the structure shown in fig. 10 after a first ion implantation process has been performed thereon.

Fig. 12 is a schematic cross-sectional view of the structure shown in fig. 11 after a second ion implantation process has been performed thereon.

Fig. 13 is a cross-sectional view of the structure shown in fig. 12 after forming an antifuse thereon.

In the context of figures 1 to 13,

100-a substrate; 101-a dielectric layer; 110-an isolation structure; 120-bottom isolation well; 130-functional well; 140-side isolation wells; 150-an antifuse; 151-antifuse active region; 152-a conductive layer; 160-contact point; m10 — first mask; m11 — second mask; m12 — third mask;

200-a substrate; 201-a dielectric layer; 210-an isolation structure; 220-functional well; 230-a first bottom isolation well; 240-side isolation wells; 250-a second bottom isolation well; 260-an antifuse; 261-an antifuse active region; 262-a conductive layer; 270-contact points; m20 — first mask; m21 — second mask;

300-a substrate; 301-a dielectric layer; 310-an isolation structure; 320-functional well; 330-first bottom isolation well; 340-a second bottom isolation well; 350-an antifuse; 351-antifuse active region; 352-a conductive layer; 360-contact point; m30 — first mask; m31-second mask.

Detailed Description

The anti-fuse structure and the method for manufacturing the anti-fuse structure according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

In a method for manufacturing an anti-fuse structure, at least three mask processes are required to form the anti-fuse structure, thereby resulting in high manufacturing cost of the anti-fuse structure. Specifically, please refer to fig. 1 to 5, wherein fig. 1 is a schematic cross-sectional view of a substrate provided in a method for manufacturing an antifuse structure; FIG. 2 is a schematic cross-sectional view of the structure shown in FIG. 1 after a first ion implantation process has been performed thereon; FIG. 3 is a schematic cross-sectional view of the structure shown in FIG. 2 after a second ion implantation process has been performed thereon; FIG. 4 is a schematic cross-sectional view of the structure shown in FIG. 3 after a third ion implantation process has been performed thereon; fig. 5 is a cross-sectional view of the structure shown in fig. 4 after forming an antifuse thereon.

First, as shown in fig. 1, a substrate 100 is provided, wherein a plurality of isolation structures 110 are formed in the substrate 100, the isolation structures 110 extend from an upper surface of the substrate 100 into the substrate 100, and the isolation structures 110 are annular and enclose a portion of the substrate 100. Further, a dielectric layer 101 is formed on the substrate 100.

Next, as shown in fig. 2, a first ion implantation process is performed under a first mask M10 to form a bottom isolation well 120 in the substrate 100, wherein the bottom isolation well 120 overlaps with a portion of the isolation structure 110 away from the surface of the substrate 100.

Next, as shown in fig. 3, a second ion implantation process is performed under a second mask M11 to form a functional well 130 in the substrate 100 enclosed by the isolation structure 110, wherein the functional well 130 extends from the surface of the substrate 100 into the bottom isolation well 120.

As shown in fig. 4, under a third mask M12, a third ion implantation process is performed to form a lateral isolation well 140 in the substrate complementary to the pattern of the functional well 130, wherein the lateral isolation well 140 wraps the isolation structure 110 and the lateral isolation well 140 extends from the surface of the substrate 100 into the bottom isolation well 120. Here, the complementary pattern of the side isolation well 140 and the functional well 130 means that the pattern of the side isolation well 140 may be regarded as an extension of the pattern of the functional well 130 in a horizontal direction.

An antifuse 150 is then formed over the functional well 130, as shown in fig. 5. Specifically, an anti-fuse active region 151 is formed in the functional well 130, and the anti-fuse active region 151 extends from the upper surface of the functional well 130 into the functional well 130; and forming a conductive layer 152 on the dielectric layer 101, and the dielectric layer 101 covers a portion under the conductive layer 152 to separate the conductive layer 152 and the antifuse active region 151, so as to form the antifuse 150 by using the antifuse active region 151, the separated portion of the dielectric layer 101, and the conductive layer 152. Further, a contact 160 may also be formed in the antifuse active region 151, the contact 160 extending from an upper surface portion of the antifuse active region 151 outside the coverage area of the conductive layer 152 into the antifuse active region 151.

It can be seen that, in a method for manufacturing an antifuse structure, three mask processes are required, and a first mask M10, a second mask M11 and a third mask M12 are respectively used to form the antifuse structure, thereby resulting in high manufacturing cost of the antifuse structure.

On this basis, the embodiment of the present invention provides a manufacturing method of an antifuse structure and an antifuse structure, by performing a first ion implantation process, including forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure, respectively, the functional well extending into the substrate from the upper surface of the substrate, the first bottom isolation well being located under the functional well in the same pattern, wherein the functional well and the first bottom isolation well are of different ion implantation types, by performing a second ion implantation process, including forming a side isolation well and a second bottom isolation well in the substrate complementary to the first ion implantation pattern, respectively, the side isolation well extending into the substrate from the upper surface of the substrate and wrapping the isolation structure to isolate the adjacent functional wells, the second bottom isolation trap is located below the side isolation trap in the same pattern, wherein the first bottom isolation trap, the side isolation trap and the second bottom isolation trap belong to the same ion implantation type, and the first bottom isolation trap and the second bottom isolation trap are connected to form a bottom isolation trap combination layer, so that the anti-fuse structure can be formed through fewer mask processes, and the manufacturing cost of the anti-fuse structure can be reduced.

Specifically, please refer to fig. 6 to 9, wherein fig. 6 is a schematic cross-sectional view of a substrate provided in a method for manufacturing an antifuse structure according to an embodiment of the present invention; FIG. 7 is a schematic cross-sectional view of the structure shown in FIG. 6 after a first ion implantation process has been performed thereon; FIG. 8 is a schematic cross-sectional view of the structure shown in FIG. 7 after a second ion implantation process has been performed thereon; fig. 9 is a schematic cross-sectional view of the structure shown in fig. 8 after forming an antifuse thereon.

As shown in fig. 6, first, a substrate 200 is provided, a plurality of isolation structures 210 are formed in the substrate 200, the isolation structures 210 extend from the upper surface of the substrate 200 into the substrate 200, and the isolation structures 210 are annular and surround a portion of the substrate 200. The isolation structure 210 may be made of silicon oxide or silicon nitride.

Further, a dielectric layer 201 is formed on the substrate 200. Preferably, the thickness of the dielectric layer 201 is less than 40 angstroms, for example, the thickness of the dielectric layer 201 may be 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 30 angstroms, or the like. The material of the dielectric layer 201 may be selected from one of silicon oxide and silicon nitride.

Next, as shown in fig. 7, a first ion implantation process is performed, including forming a functional well 220 and a first bottom isolation well 230 in the substrate 200 enclosed by the isolation structure 210, respectively, wherein the functional well 220 extends from the upper surface of the substrate 200 into the substrate 200, the first bottom isolation well 230 is patterned below the functional well 220, and the functional well 220 and the first bottom isolation well 230 are of different ion implantation types. Here, the first bottom isolation well 230 is connected to the bottom of the functional well 220, and the first bottom isolation well 230 is patterned under the functional well 220, which means that the pattern of the first bottom isolation well 230 may be regarded as an extension of the pattern of the functional well 220 in the vertical direction. Further, the functional well 220 may be a P-type ion implantation, and correspondingly, the first bottom isolation well 230 may be an N-type ion implantation; alternatively, the functional well 220 may be an N-type ion implantation, and accordingly, the first bottom isolation well 230 may be a P-type ion implantation.

Specifically, the first ion implantation process includes the following steps: performing a first step of a first ion implantation process under a first mask M20 to form one of the functional well 220 and the first bottom isolation well 230 in the substrate 200; and continuing to perform a second step of the first ion implantation process under the first mask M20 to form the other of the functional well 220 and the first bottom isolation well 230 in the substrate 200. Here, the functional well 220 and the first bottom isolation well 230 may be formed by using the first mask M20 together, and further, in the specific formation process of the functional well 220 and the first bottom isolation well 230, the functional well 220 may be formed first and then the first bottom isolation well 230 may be formed, or the functional well 220 may be formed first and then the first bottom isolation well 230 may be formed.

Wherein the ion implantation energy for forming the functional trap 220 is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e 13; the first bottom isolation well 230 is formed with an ion implantation energy of 80Kev to 200Kev and an ion implantation dose of 1e12 to 5e 13.

Next, as shown in fig. 8, a second ion implantation process is performed, including forming a lateral isolation well 240 and a second bottom isolation well 250 in the substrate 200 with a pattern complementary to the first ion implantation process, respectively, wherein the lateral isolation well 240 extends from the upper surface of the substrate 200 into the substrate 200 and wraps the isolation structure 210 to isolate the adjacent functional wells 220, the second bottom isolation well 250 is located below the lateral isolation well 240 with the same pattern, wherein the first bottom isolation well 230, the lateral isolation well 240, and the second bottom isolation well 250 are of the same ion implantation type, and the first bottom isolation well 230 and the second bottom isolation well 250 are connected to form a bottom isolation well combination layer.

Here, the patterns of the lateral isolation well 240 and the functional well 220 are complementary, and particularly, the pattern of the lateral isolation well 240 may be considered as an extension of the pattern of the functional well 220 in a horizontal direction. The pattern of the second bottom isolation well 250 and the first bottom isolation well 230 are complementary, and in particular, in the horizontal direction, the pattern of the second bottom isolation well 250 may be regarded as an extension of the pattern of the first bottom isolation well 230. Further, the second bottom isolation well 250 is patterned below the side isolation well 240, which means that the pattern of the second bottom isolation well 250 may be regarded as an extension of the pattern of the side isolation well 240 in the vertical direction.

That is, in the embodiment of the present application, the functional well 220 and the side isolation well 240 have the same depth in the substrate 200, and the first bottom isolation well 230 and the second bottom isolation well 250 have the same depth in the substrate 200. Here, in particular, the upper surfaces of the functional well 220 and the lateral isolation well 240 are at the same level (here, the surface of the substrate 200), and the lower surfaces of the functional well 220 and the lateral isolation well 240 are at the same level; the upper surfaces of the first bottom isolation well 230 and the second bottom isolation well 250 are at the same level (here, connected to the bottoms of the functional well 220 and the lateral isolation well 240, respectively), and the lower surfaces of the first bottom isolation well 230 and the second bottom isolation well 250 are at the same level.

In the embodiment of the present application, the implanted ions of the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 may all be P-type ions, and at this time, the implanted ions of the functional well 220 are N-type ions; alternatively, the implanted ions of the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 may all be N-type ions, and at this time, the implanted ions of the functional well 220 are P-type ions.

Specifically, the second ion implantation process includes the following steps: performing a first step of a second ion implantation process under a second mask M21 to form one of the side isolation well 240 and the second bottom isolation well 250 in the substrate 200; and continuing to perform a second step of a second ion implantation process under the second mask M21 to form the other of the side isolation well 240 and the second bottom isolation well 250 in the substrate 200. Here, the side isolation well 240 and the second bottom isolation well 250 may be formed by using the second mask M21 together, and further, in the specific formation process of the side isolation well 240 and the second bottom isolation well 250, the side isolation well 240 may be formed first and then the second bottom isolation well 250 may be formed, or the side isolation well 240 may be formed first and then the second bottom isolation well 250 may be formed first.

Wherein the ion implantation energy for forming the side isolation well 240 is between 70Kev and 150Kev, and the ion implantation dose is between 1e12 and 5e 13; the second bottom isolation well 250 is formed with an ion implantation energy of 80Kev to 200Kev and an ion implantation dose of 1e12 to 5e 13.

It can be seen that in the embodiment of the present application, the functional well 220 and the bowl-shaped isolation well (including the side isolation well 240, the first bottom isolation well 230, and the second bottom isolation well 250) isolating the functional well 220 can be formed by only two mask processes, so that the manufacturing cost of the antifuse structure is reduced by using a reduced mask process.

Next, referring to fig. 9, an antifuse 260 is formed over the functional well 220. The method specifically comprises the following steps: forming an antifuse active region 261 in the functional well 220, the antifuse active region 261 extending from an upper surface of the functional well 220 into the functional well 220; and forming a conductive layer 262 on the dielectric layer 201, and the dielectric layer 201 covers a part under the conductive layer 262 to separate the conductive layer 262 from the antifuse active region 261, so as to form the antifuse 260 by using the antifuse active region 261, the separated part of the dielectric layer 201 and the conductive layer 262.

The anti-fuse active region 261 may be formed by performing an ion implantation process on the functional well 220; the conductive layer 262 is formed by depositing polysilicon on the dielectric layer 201, and the conductive layer 262 extends to cover portions of the side isolation wells 240. Specifically, in the embodiment of the present application, the conductive layer 262 is located on the dielectric layer 201, and the conductive layer 262 covers a portion of the antifuse active region 261 and a portion extending to cover the side isolation well 240.

With continued reference to fig. 9, the method for manufacturing the antifuse structure further includes: a contact 270 is formed in the antifuse active region 261, the contact 270 extending from an upper surface portion of the antifuse active region 261 outside the footprint of the conductive layer 262 into the antifuse active region 261. The contact 270 may be formed by performing an ion implantation process on the antifuse active region 261.

Accordingly, an anti-fuse structure formed by the method for manufacturing an anti-fuse structure according to the embodiment of the present invention is further provided, and referring to fig. 9, specifically, the anti-fuse structure includes:

a substrate 200, wherein a plurality of isolation structures 210 are formed in the substrate 200, the isolation structures 210 extend from the upper surface of the substrate 200 into the substrate 200, and the isolation structures 210 are ring-shaped and enclose a portion of the substrate 200;

a functional well 220 formed in the substrate 200 enclosed by the isolation structure 210, the functional well 220 extending from the upper surface of the substrate 200 into the substrate 200;

a first bottom isolation well 230 formed in the substrate 200 enclosed by the isolation structure 210, wherein the first bottom isolation well 230 is patterned below the functional well 220, and the functional well 220 and the first bottom isolation well 230 are of different ion implantation types;

a lateral isolation well 240 formed in the substrate 200 in a pattern complementary to the functional well 220, the lateral isolation well 240 extending from the upper surface of the substrate 200 into the substrate 200 and encapsulating the isolation structure 210 to isolate the adjacent functional wells 220;

a second bottom isolation well 250 formed in the substrate 200, wherein the second bottom isolation well 250 is patterned below the side isolation well 240, the first bottom isolation well 230, the side isolation well 240 and the second bottom isolation well 250 belong to the same ion implantation type, and the first bottom isolation well 230 and the second bottom isolation well 250 are connected to form a bottom isolation well combination layer; and

an antifuse 260, the antifuse 260 formed over the functional well 220.

Specifically, the functional well 220 and the side isolation well 240 have the same depth in the substrate 200, and the first bottom isolation well 230 and the second bottom isolation well 250 have the same depth in the substrate 200.

Further, a dielectric layer 201 is formed on the substrate 200, and the dielectric layer 201 covers the functional well 220; the antifuse 260 includes: an antifuse active region 261, the antifuse active region 261 being formed in the functional well 220, the antifuse active region 261 extending from an upper surface of the functional well 220 into the functional well 220; a conductive layer 262, wherein the conductive layer 262 is formed on the dielectric layer 201, and the dielectric layer 201 covers a portion under the conductive layer 262 to space the conductive layer 262 and the anti-fuse active region 261; and the dielectric layer 201 is spaced apart at a spacing portion between the conductive layer 262 and the antifuse active region 261. Preferably, the thickness of the dielectric layer 201 is less than 40 angstroms. Further, the dielectric layer 201 extends to cover a portion of the side isolation well 240, and the conductive layer 262 extends to cover a portion of the side isolation well 240. Wherein the antifuse structure further comprises a contact 270 formed in the antifuse active region 261, the contact 270 extending from an upper surface portion of the antifuse active region 261 outside the capping region of the conductive layer 262 into the antifuse active region 261.

The embodiment of the invention also provides a manufacturing method of the anti-fuse structure and the anti-fuse structure, and the anti-fuse structure comprises the steps of respectively forming a functional well and a first bottom isolation well in the substrate encircled by the isolation structure by executing a first ion implantation process, wherein the functional well extends into the substrate from the upper surface of the substrate, the first bottom isolation well and a pattern are positioned below the functional well, and the functional well and the first bottom isolation well belong to different ion implantation types; and performing a second ion implantation process, including forming a second bottom isolation well in the substrate complementary to the first ion implantation pattern, wherein the second bottom isolation well extends from the upper surface of the substrate into the substrate to isolate the adjacent functional wells, the first bottom isolation well and the second bottom isolation well belong to the same ion implantation type, and the first bottom isolation well and the second bottom isolation well are connected to form a bottom isolation well combination layer for isolating the functional wells, so that the anti-fuse structure can be formed through fewer mask processes, and the manufacturing cost of the anti-fuse structure can be reduced.

Specifically, please refer to fig. 10 to 13, wherein fig. 10 is a schematic cross-sectional view of a substrate provided in a method for manufacturing an antifuse structure according to an embodiment of the present invention; fig. 11 is a schematic cross-sectional view of the structure shown in fig. 10 after a first ion implantation process has been performed thereon; fig. 12 is a schematic cross-sectional view of the structure shown in fig. 11 after a second ion implantation process has been performed thereon; fig. 13 is a cross-sectional view of the structure shown in fig. 12 after forming an antifuse thereon.

First, as shown in fig. 10, a substrate 300 is provided, wherein a plurality of isolation structures 310 are formed in the substrate 300, the isolation structures 310 extend from the upper surface of the substrate 300 into the substrate 300, and the isolation structures 310 are ring-shaped and enclose a portion of the substrate 300. The isolation structure 310 may be made of silicon oxide or silicon nitride.

Further, a dielectric layer 301 is formed on the substrate 300. Preferably, the thickness of the dielectric layer 301 is less than 40 angstroms, for example, the thickness of the dielectric layer 301 may be 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, 30 angstroms, or the like. The material of the dielectric layer 301 may be selected from one of silicon oxide and silicon nitride.

Next, as shown in fig. 11, a first ion implantation process is performed, including forming a functional well 320 and a first bottom isolation well 330 in the substrate 300 enclosed by the isolation structure 310, respectively, wherein the functional well 320 extends from the upper surface of the substrate 300 into the substrate 300, the first bottom isolation well 330 is patterned below the functional well 320, and the functional well 320 and the first bottom isolation well 330 are of different ion implantation types. Here, the first bottom isolation well 330 is connected to the bottom of the functional well 320, and the first bottom isolation well 330 is patterned under the functional well 320, which means that the pattern of the first bottom isolation well 330 may be regarded as an extension of the pattern of the functional well 320 in the vertical direction. Further, the functional well 320 may be a P-type ion implantation, and correspondingly, the first bottom isolation well 330 may be an N-type ion implantation; alternatively, the functional well 320 may be an N-type ion implantation, and accordingly, the first bottom isolation well 330 may be a P-type ion implantation.

Specifically, the first ion implantation process includes the following steps: performing a first step of a first ion implantation process under a first mask M30 to form one of the functional well 320 and the first bottom isolation well 330 in the substrate 300; and continuing to perform a second step of the first ion implantation process under the first mask M30 to form the other of the functional well 320 and the first bottom isolation well 330 in the substrate 300. Here, the functional well 320 and the first bottom isolation well 330 may be formed by using the first mask M30 together, and further, in the specific formation process of the functional well 320 and the first bottom isolation well 330, the functional well 320 may be formed first and then the first bottom isolation well 330 may be formed, or the functional well 320 may be formed first and then the first bottom isolation well 330 may be formed.

Wherein, the ion implantation energy for forming the functional trap 320 is between 70Kev and 150Kev, and the ion implantation dosage is between 1e12 and 5e 13; the ion implantation energy for forming the first bottom isolation well 330 is between 80Kev and 200Kev, and the ion implantation dose is between 1e12 and 5e 13.

Next, as shown in fig. 12, a second ion implantation process is performed, including forming a second bottom isolation well 340 in the substrate 300 complementary to the first ion implantation process pattern, wherein the second bottom isolation well 340 extends from the upper surface of the substrate 300 into the substrate 300 to isolate the adjacent functional wells 320, wherein the first bottom isolation well 330 and the second bottom isolation well 340 are of the same ion implantation type, and the first bottom isolation well 330 and the second bottom isolation well 340 are connected to form a bottom isolation well combination layer for isolating the functional wells.

Specifically, the second ion implantation process may be performed under a second mask M31 to form the second bottom isolation well 340. The second ion implantation process may have an ion implantation energy of 70Kev to 200Kev and an ion implantation dose of 1e12 to 5e 13.

Further, the second bottom isolation well 340 may cover the inner sidewall of the isolation structure 310, that is, the second bottom isolation well 340 covers the sidewall of the isolation structure 310 near the functional well 320. Here, the pattern of the second bottom isolation well 340 is complementary to (a combination of) the patterns of the functional well 320 and the first bottom isolation well 330. Specifically, in the horizontal direction, the pattern of the portion of the second bottom isolation well 340 near the upper surface of the substrate 300 may be regarded as an extension of the pattern of the functional well 320; the pattern of the portion of the second bottom isolation well 340 away from the upper surface of the substrate 300 may be considered an extension of the pattern of the first bottom isolation well 330.

In the embodiment of the present application, the thickness of the second bottom isolation well 340 in the vertical direction is greater than the thickness of the first bottom isolation well 330 in the vertical direction. Further, the depth of the first bottom isolation well 330 and the second bottom isolation well 340 in the substrate 300 are the same, that is, the lower surface of the first bottom isolation well 330 and the lower surface of the second bottom isolation well 340 are at the same level.

In this embodiment, the implanted ions of the first bottom isolation well 330 and the second bottom isolation well 340 may be both P-type ions, and at this time, the implanted ions of the functional well 320 are N-type ions; alternatively, the implanted ions of the first bottom isolation well 330 and the second bottom isolation well 340 may be both N-type ions, and at this time, the implanted ions of the functional well 320 are P-type ions.

It can be seen that in the embodiment of the present application, the functional well 320 and the bowl-shaped isolation well (including the first bottom isolation well 330 and the second bottom isolation well 340) isolating the functional well 320 can be formed by only two mask processes, so that a reduced mask process is used, and the manufacturing cost of the antifuse structure is reduced.

As shown in fig. 13, an antifuse 350 is formed over the functional well 320. The method specifically comprises the following steps: forming an antifuse active region 351 in the functional well 320, the antifuse active region 351 extending from the upper surface of the functional well 320 into the functional well 320; and forming a conductive layer 352 on the dielectric layer 301, and the dielectric layer 301 covers a portion under the conductive layer 352 to separate the conductive layer 352 and the antifuse active region 351, so as to form the antifuse 350 by using the antifuse active region 351, the separated portion of the dielectric layer 301 and the conductive layer 352.

The anti-fuse active region 351 may be formed by performing an ion implantation process on the functional well 320; the conductive layer 352 is formed by depositing polysilicon on the dielectric layer 301, and the conductive layer 352 extends to cover a portion of the second bottom isolation well 340. Specifically, in the embodiment of the present application, the conductive layer 352 is located on the dielectric layer 301, and the conductive layer 352 covers a portion of the antifuse active region 351 and a portion extending to cover the second bottom isolation well 340.

With continued reference to fig. 13, the method for manufacturing the antifuse structure further includes: a contact 360 is formed in the antifuse active region 351, the contact 360 extending from an upper surface portion of the antifuse active region 351 outside the footprint of the conductive layer 352 into the antifuse active region 351. The contact 360 may be formed by performing an ion implantation process on the antifuse active region 351.

Accordingly, an anti-fuse structure formed by the method for manufacturing an anti-fuse structure according to the embodiment of the present invention can be referred to fig. 13, specifically, the anti-fuse structure includes:

a substrate 300, wherein a plurality of isolation structures 310 are formed in the substrate 300, the isolation structures 310 extend from the upper surface of the substrate 300 into the substrate 300, and the isolation structures 310 are ring-shaped and enclose a portion of the substrate 300;

a functional well 320 formed in the substrate 300 enclosed by the isolation structure 310, the functional well 320 extending from the upper surface of the substrate 300 into the substrate 300;

a first bottom isolation well 330 formed in the substrate 300 enclosed by the isolation structure 310, wherein the first bottom isolation well 330 is patterned below the functional well 320, and the functional well 320 and the first bottom isolation well 330 are of different ion implantation types;

a second bottom isolation well 340 formed in the substrate 300 in a pattern complementary to the functional well 320, the second bottom isolation well 340 extending from the upper surface of the substrate 300 into the substrate 300 to isolate the adjacent functional wells 320, wherein the first bottom isolation well 330 and the second bottom isolation well 340 are of the same ion implantation type, and the first bottom isolation well 330 and the second bottom isolation well 340 are connected to form a bottom isolation well combination layer for isolating the functional wells; and

an antifuse 350, the antifuse 350 formed over the functional well 320.

Wherein the second bottom isolation well 340 covers the inner sidewall of the isolation structure 310. The first bottom isolation well 330 and the second bottom isolation well 340 have the same depth in the substrate 300.

Further, a dielectric layer 301 is formed on the substrate 300, and the dielectric layer 301 covers the functional well 320; the antifuse 350 includes: an antifuse active region 351, the antifuse active region 351 being formed in the functional well 320, the antifuse active region 351 extending from an upper surface of the functional well 320 into the functional well 320; a conductive layer 352, wherein the conductive layer 352 is formed on the dielectric layer 301, and the dielectric layer 301 covers a portion under the conductive layer 352 to space the conductive layer 352 and the anti-fuse active region 351; and the dielectric layer 301 is spaced apart at a spacing portion between the conductive layer 352 and the anti-fuse active region 351. Preferably, the thickness of the dielectric layer 301 is less than 40 angstroms. The conductive layer 352 extends over a portion of the second bottom isolation well 340. In the embodiment, the anti-fuse structure further includes a contact 360 formed in the anti-fuse active region 351, wherein the contact 360 extends from an upper surface portion of the anti-fuse active region 351 outside the coverage area of the conductive layer 352 into the anti-fuse active region 351.

In summary, in the method for manufacturing the antifuse structure and the antifuse structure provided by the invention, the antifuse structure can be formed by a few mask processes, so that the manufacturing cost of the antifuse structure can be reduced.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.