阅读说明：本技术 集成电路存储器及其形成方法 (Integrated circuit memory and forming method thereof ) 是由 江文湧 林仕杰 于 2018-09-10 设计创作，主要内容包括：本发明提供了一种集成电路存储器及其形成方法,通过在对应同一有源区的两条字线之间的沟槽隔离结构中形成绝缘结构,且所述绝缘结构的材料的介电常数小于所述沟槽隔离结构的材料的介电常数,从而减小了对应同一有源区的两条所述字线之间的寄生电容,提高了集成电路存储器的性能和稳定性。(The invention provides an integrated circuit memory and a forming method thereof.A trench isolation structure between two word lines corresponding to the same active region is formed with an insulation structure, and the dielectric constant of the material of the insulation structure is smaller than that of the material of the trench isolation structure, thereby reducing the parasitic capacitance between the two word lines corresponding to the same active region and improving the performance and the stability of the integrated circuit memory.)

1. An integrated circuit memory, comprising:

a substrate having a plurality of trench isolation structures formed therein, the trench isolation structures defining a plurality of active regions,

a plurality of word lines arranged in parallel and formed in the substrate, wherein the word lines intersect the corresponding active regions and extend into the trench isolation structure, and each active region intersects two word lines;

and the insulating structures are formed in the trench isolation structures and positioned between the two word lines corresponding to the same active region, and the dielectric constant of the material of the insulating structures is smaller than that of the material of the trench isolation structures.

2. The integrated circuit memory of claim 1 wherein a plurality of the active regions are arranged in an array, and a plurality of the active regions in a same column intersect with two same word lines, such that two adjacent active regions and two word lines in the same column surround an insulating region in the trench isolation structure, the insulating structure being formed in the insulating region of the trench isolation structure.

3. The integrated circuit memory of claim 2 wherein the insulating structure comprises a layer of insulating material formed in an insulating trench, the layer of insulating material having a dielectric constant of less than 4.

4. The integrated circuit memory of claim 3 wherein the insulating structure further comprises a stress buffer layer covering sidewalls and a bottom wall of the insulating trench, the insulating material layer being formed on the stress buffer layer and filling the insulating trench.

5. The integrated circuit memory of claim 3 wherein the material of the insulating material layer comprises one or more of free silicon oxide material, silicon oxycarbide, fluorosilicone glass, carbon doped glass, and organic polymers.

6. The integrated circuit memory of claim 1, wherein adjacent two of the isolation structures are separated by one of the active regions in a direction in which the word lines extend.

7. The integrated circuit memory of claim 5, wherein the active region is used to form two memory cells of the integrated circuit memory, each of the active regions having a drain region and two source regions formed therein, the two source regions being located on opposite sides of the drain region, each of the memory cells having an access transistor therein, the two access transistors sharing the drain region.

8. A method of forming an integrated circuit memory, comprising:

providing a substrate, wherein a plurality of trench isolation structures are formed in the substrate, and the trench isolation structures define a plurality of active regions extending along a first direction;

forming a plurality of insulation trenches in the trench isolation structure, wherein the insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the insulation trenches arranged on the same straight line intersect with the active region;

filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than that of the material of the trench isolation structure; and the number of the first and second groups,

forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines intersect with the corresponding active regions and extend into the trench isolation structure, each active region intersects with two word lines, and the two word lines corresponding to the same active region are respectively located on two sides of the insulation structure in the trench isolation structure.

9. The method of forming an integrated circuit memory of claim 8, wherein forming a plurality of the isolation structures comprises:

forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulation region and a part of the active region is formed in the first mask layer, and the insulation region is used for forming the insulation structure;

etching the insulation region below the first opening to form a plurality of insulation grooves arranged along the second direction in the groove isolation structure; and the number of the first and second groups,

and filling an insulating material layer in the insulating groove to form the insulating structure.

10. The method of claim 9, wherein the step of filling the insulating material layer in the insulating trench to form the insulating structure comprises:

forming stress buffer layers on the side wall and the bottom wall of the insulation groove; and the number of the first and second groups,

and forming the insulating material layer on the stress buffer layer, wherein the insulating material layer fills the insulating groove, and the stress buffer layer and the insulating material layer jointly form the insulating structure.

11. The method of forming an integrated circuit memory of claim 8, wherein the step of forming the first mask layer comprises:

forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers the word line region;

forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and forms the first mask layer together with the second mask layer;

and after forming the insulating structure, the step of forming the word line in the substrate includes:

filling a fourth mask layer in the first opening, and removing the second mask layer to form a second opening corresponding to the word line region;

etching the word line area below the second opening to form a word line groove in the substrate;

forming a word line in the word line trench.

12. The method of claim 9, wherein the fourth mask layer is formed of a same material as the third mask layer.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to an integrated circuit memory and a method for forming the same.

Background

In order to reduce the area of an integrated circuit memory to achieve the maximum integration, a trench-type transistor structure is usually adopted, and two transistors sharing a drain electrode can be manufactured in one active region to further reduce the area and reduce the production cost. However, the distance between the two transistors is very close, and a large parasitic capacitance is generated between the word lines, which affects the performance and stability of the device.

Disclosure of Invention

The invention aims to provide an integrated circuit memory and a forming method thereof, which can reduce the parasitic capacitance between two word lines corresponding to the same active region by reducing the dielectric constant of a dielectric medium between the two word lines, thereby improving the performance and stability of a device.

In order to achieve the above object, the present invention provides an integrated circuit memory, comprising:

a substrate having a plurality of trench isolation structures formed therein, the trench isolation structures defining a plurality of active regions,

a plurality of word lines arranged in parallel and formed in the substrate, wherein the word lines intersect the corresponding active regions and extend into the trench isolation structure, and each active region intersects two word lines;

and the insulating structures are formed in the trench isolation structures and positioned between the two word lines corresponding to the same active region, and the dielectric constant of the material of the insulating structures is smaller than that of the material of the trench isolation structures.

Optionally, the active regions are arranged in an array, and the active regions in the same column are intersected with the same two word lines, so that an insulating region is surrounded by two adjacent active regions and two adjacent word lines in the same column in the trench isolation structure, and the insulating structure is formed in the insulating region of the trench isolation structure.

Optionally, the insulating structure includes an insulating material layer formed in an insulating trench, and a dielectric constant of a material of the insulating material layer is less than 4.

Optionally, the insulating structure further includes a stress buffer layer, the stress buffer layer covers the sidewall and the bottom wall of the insulating trench, and the insulating material layer is formed on the stress buffer layer and fills the insulating trench.

Optionally, the material of the insulating material layer includes one or more of a free silicon oxide material, silicon oxycarbide, fluorosilicone glass, carbon-doped glass, and an organic polymer.

Optionally, in the extending direction of the word line, two adjacent insulation structures are separated by one active region.

Optionally, the active region is used to form two storage units of the integrated circuit memory, a drain region and two source regions are formed in each active region, the two source regions are respectively located at two sides of the drain region, each storage unit has an access transistor, and the two access transistors share the drain region.

The invention also provides a forming method of the integrated circuit memory, which comprises the following steps:

providing a substrate, wherein a plurality of trench isolation structures are formed in the substrate, and the trench isolation structures define a plurality of active regions extending along a first direction;

forming a plurality of insulation trenches in the trench isolation structure, wherein the insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the insulation trenches arranged on the same straight line intersect with the active region;

filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than that of the material of the trench isolation structure; and the number of the first and second groups,

forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines intersect with the corresponding active regions and extend into the trench isolation structure, each active region intersects with two word lines, and the two word lines corresponding to the same active region are respectively located on two sides of the insulation structure in the trench isolation structure.

Optionally, the step of forming a plurality of the insulation structures includes:

forming a first mask layer extending along a second direction on the substrate, wherein a first opening corresponding to an insulation region and a part of the active region is formed in the first mask layer, and the insulation region is used for forming the insulation structure;

etching the insulation region below the first opening to form a plurality of insulation grooves arranged along the second direction in the groove isolation structure; and the number of the first and second groups,

and filling an insulating material layer in the insulating groove to form the insulating structure.

Optionally, the step of filling the insulating material layer in the insulating trench to form the insulating structure includes:

forming stress buffer layers on the side wall and the bottom wall of the insulation groove; and the number of the first and second groups,

and forming the insulating material layer on the stress buffer layer, wherein the insulating material layer fills the insulating groove, and the stress buffer layer and the insulating material layer jointly form the insulating structure.

Optionally, the step of forming the first mask layer includes:

forming a second mask layer extending along a second direction on the substrate, wherein the second mask layer covers the word line region;

forming a third mask layer on the substrate, wherein the third mask layer is adjacent to the second mask layer and forms the first mask layer together with the second mask layer;

and after forming the insulating structure, the step of forming the word line in the substrate includes:

filling a fourth mask layer in the first opening, and removing the second mask layer to form a second opening corresponding to the word line region;

etching the word line area below the second opening to form a word line groove in the substrate;

forming a word line in the word line trench.

Optionally, the material of the fourth mask layer is the same as the material of the third mask layer.

In the integrated circuit memory and the forming method thereof provided by the invention, the insulating structure is formed in the groove isolation structure between the two word lines corresponding to the active area, and the dielectric constant of the material of the insulating structure is smaller than that of the material of the groove isolation structure, so that the parasitic capacitance between the two word lines corresponding to the same active area is reduced, and the performance and the stability of the integrated circuit memory are improved.

Drawings

FIG. 1 is a top view of an integrated circuit memory according to an embodiment of the present invention;

FIG. 2 is a partial cross-sectional view of the integrated circuit memory of FIG. 1 taken along line D-D' in a vertical direction according to an embodiment of the present invention;

FIG. 3 is a flow chart of a method for forming an integrated circuit memory according to an embodiment of the invention;

FIGS. 4-12 are partial cross-sectional views of semiconductor structures formed by the method of forming the integrated circuit memory according to embodiments of the present invention;

wherein the reference numbers are as follows:

1-a substrate; 11-trench isolation structures; 12-active region, 121-drain region, 122-source region;

2-word line; 21-word line trenches;

3-an insulating structure; 31-an insulation trench; 32-a layer of insulating material;

41-a second mask layer; 42-a fifth mask layer;

43-a third mask layer; 44-a fourth mask layer;

51-a first opening; 52-a second opening;

a-a first direction; b-a second direction.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 and fig. 2 are schematic structural diagrams of an integrated circuit memory provided in this embodiment, as shown in fig. 1 and fig. 2, the integrated circuit memory includes a substrate 1, a plurality of trench isolation structures 11 are formed in the substrate 1, and the trench isolation structures 11 define a plurality of active regions 12; a plurality of word lines 2 arranged in parallel and formed in the substrate 1, wherein the word lines 2 intersect with the corresponding active regions 12 and extend into the trench isolation structure 11, and each active region 12 intersects with two word lines 2; and a plurality of insulating structures 3 formed in the trench isolation structures 11, wherein the dielectric constant of the material of the insulating structures 3 is smaller than the dielectric constant of the material of the trench isolation structures 11.

For convenience of description, two of the word lines 2 corresponding to the same active region 12 are defined herein as two adjacent word lines 2, and none of the word lines 2 corresponding to the same active region 12 are adjacent, for example, there are three pairs of adjacent word lines 2 in fig. 1.

Specifically, referring to fig. 1, a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 separate adjacent active regions 12, so that the active regions form an array distribution with multiple rows and multiple columns, the trench isolation structures 11 generally include a silicon oxide layer formed in the isolation trenches, the active regions 12 are surrounded by the trench isolation structures 11, each active region 12 includes two source regions 121 and a drain region 122, the drain region 122 is located between two source regions 121, a plurality of word lines 2 arranged in parallel are located in the substrate 1, and each active region 12 is penetrated by two adjacent word lines 2, wherein two adjacent word lines 2 respectively penetrate through a portion between the source region 121 and the drain region 122 in the active region 12 to separate each source region 121 from the drain region 122, so as to form two access transistors in each active region, the two access transistors share the drain region 122.

Further, referring to fig. 2, fig. 8 and fig. 9, the insulating structure 3 is located in the trench isolation structure 11 at two sides of each active region 12 and located between two adjacent word lines 2. Specifically, the active regions 12 are arranged in an array, and the active regions 12 in the same column all intersect with the same two word lines 2, so that the two adjacent active regions 12 and the two word lines 2 in the same column surround an insulation region in the trench isolation structure 11, and the insulation structure 3 is formed in the insulation region of the trench isolation structure 11.

The insulating structure 3 includes an insulating material layer 32 formed in an insulating trench 31, wherein the insulating material layer 32 is made of a low-K material having a dielectric constant less than 4, such as one or more of a free silicon oxide material, a silicon carbon oxide, a fluorinated silicon glass, a carbon-doped glass, and an organic polymer. It can be understood that, since the material of the insulating structure 3 is a low-K material and is located between two adjacent word lines 2, the parasitic capacitance between two adjacent word lines 2 can be effectively reduced, thereby improving the performance of the device.

Further, as shown in fig. 2, the insulating structures 3 may be further sunk in the substrate 1 than the word lines 2, and in the extending direction (i.e., the second direction b) of the word lines 2, two adjacent insulating structures 3 are separated by one active region 12 (i.e., all the insulating structures 3 except the drain region 122 between two word lines 2 corresponding to the same active region 12), so that the area of the insulating structures 3 is larger, and the parasitic capacitance between two adjacent word lines 2 can be further reduced.

Optionally, the insulating structure 3 may further include a stress buffer layer (not shown) covering the sidewalls and the bottom wall of the insulating trench 31, and the insulating material layer 32 is formed on the stress buffer layer and fills the insulating trench 31 to buffer and match the stress between the films.

As shown in fig. 3, the present embodiment provides a method for forming an integrated circuit memory, including:

s1: forming a plurality of insulation trenches in the trench isolation structure, wherein the insulation trenches are arranged along a second direction, and virtual connecting lines corresponding to the insulation trenches arranged on the same straight line intersect with the active region;

s2: filling an insulating material layer in the insulating trench to form an insulating structure, wherein the dielectric constant of the material of the insulating material layer is smaller than that of the material of the trench isolation structure;

s3: forming a plurality of word lines extending along the second direction in the substrate, wherein the word lines intersect with the corresponding active regions and extend into the trench isolation structure, each active region intersects with two word lines, and the two word lines corresponding to the same active region are respectively located on two sides of the insulation structure in the trench isolation structure.

Specifically, referring to fig. 1, the substrate 1 is provided, a plurality of trench isolation structures 11 are formed in the substrate 1, the trench isolation structures 11 define a plurality of active regions 12 extending along a first direction a, that is, the periphery of each active region 12 is surrounded by the trench isolation structures 11, so that the plurality of active regions 12 are isolated from each other, a drain region 122 and two source regions 121 are formed in each active region 12, the two source regions 121 are respectively located at two sides of the drain region 122, the active regions are used for forming two memory cells of the integrated circuit memory, each memory cell has an access transistor therein, and the two access transistors share the drain region 122.

Next, as shown in fig. 4 to 8, a first mask layer extending along the second direction b is formed on the substrate 1, and the insulating trench 31 is formed by using the first mask layer as a mask. Specifically, the step of forming the first mask layer includes: first, as shown in fig. 4, forming a second mask layer 41 on the substrate 1, where the second mask layer 41 covers a portion of the substrate 1 corresponding to a word line region, where the word line region is used for forming a word line, it can be understood that the second mask layer 41 is in a strip shape and extends along the second direction b; next, as shown in fig. 5, forming a fifth mask layer 42 extending along the second direction b on the substrate 1, where the fifth mask layer 42 covers the substrate 1 between two adjacent word line regions; next, as shown in fig. 6, forming a third mask layer 43 extending along the second direction b on the substrate 1, where the third mask layer 43 is adjacent to the second mask layer 41 and covers the remaining substrate 1; finally, as shown in fig. 7, etching is performed to remove the fifth mask layer 42, and the second mask layer 41 and the third mask layer 43 are remained to form a first mask layer, it can be understood that, after the fifth mask layer 42 is removed, an area covered by the fifth mask layer 42 is opened to form a first opening 51, which can be regarded as the first opening 51 formed in the first mask layer, and the first opening 51 simultaneously exposes the drain region 122 and an insulating region, which is used for forming the insulating structure.

Next, as shown in fig. 8, the insulation region is etched by using the first mask layer as a mask to form an insulation trench 31 in the trench isolation structure 11, where the insulation trench 31 may or may not penetrate through the entire trench isolation structure 11, and the present invention is not limited thereto. As shown in fig. 9, the insulation trench 31 is filled with a low-K material to form an insulation material layer 32, and the insulation structure 3 is finally formed.

It can be understood that, as shown in fig. 1 and fig. 8, since the first opening 51 further corresponds to the drain region 122, when the insulating region is etched to form the insulating trench 31, an etchant having a high selection ratio to the material of the drain region 122 and the material of the trench isolation structure 11 needs to be selected, so that the insulating trench 31 is generated by etching the trench isolation structure 11 but has little influence on the drain region 122, and the formed insulating trenches 31 are arranged on two sides of the drain region 122.

Preferably, before forming the isolation material layer 32, a stress buffer layer may be formed on the sidewall and the bottom wall of the insulation trench 31; then, the insulating material layer 32 is formed on the stress buffer layer, the insulating material layer 32 fills the insulating trench 31, the stress buffer layer and the insulating material layer 32 together form the insulating structure 3, and the stress buffer layer can perform stress matching and buffering functions, so that stability between the films is better.

Further, as shown in fig. 10, in order to form the word line, the first opening 51 may be filled with a fourth mask layer 44 extending in the second direction b. And then directly removing the second mask layer 41 to form a second opening 52, wherein the second opening 52 corresponds to the word line region.

Finally, as shown in fig. 11 to 12, the third mask layer 43 and the fourth mask layer 44 are used as masks, the word line region is etched to form a word line trench 21, and then a word line 2 is formed in the word line trench 21, optionally, the word line 2 includes a gate dielectric layer and a gate conductive layer, the word line trench 21 is formed in the substrate 1 and passes through a portion between the drain region 122 and the source region 121, the gate dielectric layer covers a sidewall and a bottom wall of the word line trench 21, and the gate conductive layer is formed on the gate dielectric layer and is filled in the word line trench 21. Finally, the third mask layer 43 and the fourth mask layer 44 are removed, so as to form the semiconductor structure shown in fig. 2.

Further, the third mask layer 43 and the fourth mask layer 44 may be made of the same material, so as to remove the second mask layer 41 and retain the third mask layer 43 and the fourth mask layer 44.

It can be understood that, in this embodiment, since the first mask layer is composed of the second mask layer 41 and the third mask layer 43, when the word line 2 is formed after the insulating structure 3 is formed, the word line 2 can be formed by directly stripping the second mask layer 41 without forming a new mask layer, so that the process is simplified, and it can be understood that, when the insulating structure 3 in this embodiment is formed, a new mask does not need to be redesigned in the original process, and the performance of the device can be greatly improved on the basis of a simpler process.

In summary, in the integrated circuit memory and the forming method thereof provided by the embodiments of the invention, the insulating structure is formed in the trench isolation structure between the two word lines corresponding to the active region, and the dielectric constant of the material of the insulating structure is smaller than that of the material of the trench isolation structure, so that the parasitic capacitance between the two word lines corresponding to the same active region is reduced, and the performance and stability of the integrated circuit memory are improved.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.