阅读说明：本技术 半导体封装件
(Semiconductor package
) 是由 崔在薰
李斗焕
崔朱伶
韩成
金炳镐 于 2019-05-10 设计创作，主要内容包括：本发明提供一种半导体封装件,所述半导体封装件包括：半导体芯片,包括钝化膜和保护膜,所述钝化膜设置在有效表面上并且具有使连接焊盘的至少一部分暴露的第一开口,所述保护膜设置在所述钝化膜上,填充所述第一开口中的至少一部分并且具有使所述连接焊盘的至少一部分在所述第一开口中暴露的第二开口；包封剂,覆盖所述半导体芯片的至少一部分；以及连接结构,包括绝缘层、重新分布层以及连接过孔,所述绝缘层具有连接到所述第二开口的通路孔,以使所述连接焊盘的至少一部分暴露,所述连接过孔将所述连接焊盘连接到所述重新分布层同时填充所述通路孔和所述第二开口中的每个的至少一部分。所述第二开口和所述通路孔连接,以具有台阶部。(The present invention provides a semiconductor package, including: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad, and a protective film disposed on the passivation film, filling at least a portion of the first opening and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the passage hole are connected to have a stepped portion.)
1. A semiconductor package, comprising:
a semiconductor chip having an active surface provided with a connection pad and an inactive surface opposite to the active surface and including a passivation film and a protective film, the passivation film being provided on the active surface and having a first opening exposing at least a part of the connection pad, and the protective film being provided on the passivation film, filling at least a part of the first opening and having a second opening exposing at least a part of the connection pad in the first opening;
an encapsulant covering at least a portion of the semiconductor chip; and
a connection structure including an insulating layer disposed on the protective film and having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening,
wherein the second opening and the passage hole are connected to have a stepped portion.
2. The semiconductor package according to claim 1, wherein a wall surface of the second opening is recessed toward a wall surface of the first opening,
a recessed region is disposed between the insulating layer and the connection pad, and
the connecting via fills at least a portion of the recessed region.
3. The semiconductor package according to claim 2, wherein the protective film and the insulating layer comprise different materials.
4. The semiconductor package according to claim 1, wherein in a connection point of the second opening and the via hole, a width of the second opening is larger than a width of the via hole.
5. The semiconductor package of claim 4, wherein the second opening and the via hole taper in opposite directions.
6. The semiconductor package according to claim 4, wherein the width of the second opening is wider closer to the connection pad, and
the width of the via hole is narrower the closer to the connection pad.
7. The semiconductor package according to claim 1, wherein an area of the connection pad exposed through the first opening other than an area exposed through the second opening is covered with the protective film.
8. The semiconductor package of claim 7, wherein the insulating layer is physically spaced apart from the connection pads.
9. The semiconductor package according to claim 1, wherein the passivation film and the protective film are provided in a region within the effective surface.
10. The semiconductor package according to claim 9, wherein the encapsulant covers a side surface of each of the passivation film and the protective film.
11. The semiconductor package according to claim 9, wherein the encapsulant fills a portion between the protective film and the insulating layer.
12. The semiconductor package according to claim 1, wherein a thickness of the protective film is thinner than a thickness of the passivation film.
13. The semiconductor package of claim 1, further comprising: a frame having a through-hole formed therein,
wherein the semiconductor chip is disposed in the through hole,
the encapsulant covers at least a portion of the frame, and
the encapsulant fills at least a portion of the via.
14. The semiconductor package of claim 13, wherein the frame comprises: a first insulating layer in contact with the connection structure; a first wiring layer in contact with the connection structure and embedded in the first insulating layer; a second wiring layer provided on a side of the first insulating layer opposite to a side of the first insulating layer in which the first wiring layer is embedded; a second insulating layer covering the second wiring layer and disposed on the first insulating layer; and a third wiring layer provided on the second insulating layer,
the first wiring layer to the third wiring layer are electrically connected to the connection pads, and
the lower surface of the first insulating layer is coplanar with the lowermost surface of the protective film.
15. The semiconductor package of claim 13, wherein the frame comprises: a first insulating layer; a first wiring layer provided on a lower surface of the first insulating layer; a second wiring layer disposed on an upper surface of the first insulating layer; a second insulating layer disposed on the lower surface of the first insulating layer and covering the first wiring layer; a third wiring layer provided on a lower surface of the second insulating layer; a third insulating layer provided on the upper surface of the first insulating layer and covering the second wiring layer; and a fourth wiring layer provided on an upper surface of the third insulating layer,
the first wiring layer to the fourth wiring layer are electrically connected to the connection pads, and
the lower surface of the third wiring layer is coplanar with the lowermost surface of the protective film.
16. The semiconductor package of claim 1, wherein the semiconductor package is a fan-out semiconductor package.
17. A semiconductor package, comprising:
a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface;
an encapsulant covering at least a portion of the semiconductor chip; and
a connection structure including an insulating layer disposed on the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer,
wherein the connecting via has a portion that: the width of the portion is smaller than the width of the uppermost portion of the connection via in contact with the connection pad and the width of the lowermost portion of the connection via in contact with the redistribution layer.
18. The semiconductor package of claim 17, wherein the insulating layer is physically spaced apart from the connection pads.
19. The semiconductor package of claim 17, further comprising:
a protective film disposed between the connection pad and the insulating layer and exposing a portion of the connection pad; and
a passivation film disposed between the connection pad and the protective film and exposing a portion of the connection pad,
wherein a width of a portion of the connection pad exposed through the passivation film is greater than a width of a portion of the connection pad exposed through the protective film.
20. The semiconductor package according to claim 19, wherein the encapsulant fills a portion between the protective film and the insulating layer.
Technical Field
The present disclosure relates to a semiconductor package, for example, a fan-out type semiconductor package.
Background
A significant recent trend in the development of technologies involving semiconductor chips is to reduce the size of the semiconductor chips. Therefore, in the field of packaging technology, with the rapid increase in demand for small-sized semiconductor chips and the like, it is required to realize a semiconductor package having a compact size while including a plurality of pins. One packaging technique that has been proposed to meet the above-mentioned technical needs is a fan-out package. Such a fan-out type package has a compact size, and a plurality of pins can be realized by redistributing connection terminals to the outside of an area where a semiconductor chip is disposed.
On the other hand, in the case of a semiconductor chip, aluminum (Al) or copper (Cu) is used as a material of the connection pad. In this case, in a process for manufacturing the package, the connection pad of the semiconductor chip may be exposed to air, moisture, a chemical solution, or the like, which may cause corrosion and damage.
Disclosure of Invention
An aspect of the present disclosure provides a novel semiconductor package structure for significantly reducing corrosion and damage to connection pads of a semiconductor chip, and improving reliability of connection vias and reducing resist distribution.
According to an aspect of the present disclosure, a protective film is formed on a passivation film having an opening exposing a connection pad of a semiconductor chip in a chip state before the semiconductor chip is packaged. Further, when a via hole is formed in the insulating layer in an operation of packaging the semiconductor chip, an undercut is formed in the protective film.
According to an aspect of the present disclosure, a semiconductor package includes: a semiconductor chip having an active surface provided with a connection pad and an inactive surface opposite to the active surface and including a passivation film and a protective film, the passivation film being provided on the active surface and having a first opening exposing at least a part of the connection pad, and the protective film being provided on the passivation film, filling at least a part of the first opening and having a second opening exposing at least a part of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer disposed on the protective film and having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the passage hole are connected to have a stepped portion.
According to another aspect of the present disclosure, a semiconductor package includes: a semiconductor chip having an active surface on which connection pads are provided and an inactive surface opposite to the active surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure including an insulating layer disposed on the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer. The connecting via has a portion that: the width of the portion is smaller than the width of the uppermost portion of the connection via in contact with the connection pad and the width of the lowermost portion of the connection via in contact with the redistribution layer.
Drawings
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a block diagram schematically illustrating an example of an electronic device system;
fig. 2 is a schematic perspective view showing an example of an electronic device;
fig. 3A and 3B are schematic sectional views showing states of a fan-in type semiconductor package before and after being packaged;
fig. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package;
fig. 5 is a schematic sectional view showing a case where a fan-in type semiconductor package is mounted on a printed circuit board and is finally mounted on a main board of an electronic device;
fig. 6 is a schematic sectional view showing a case where a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device;
fig. 7 is a schematic sectional view showing a fan-out type semiconductor package;
fig. 8 is a schematic sectional view showing a case where a fan-out type semiconductor package is mounted on a main board of an electronic device;
fig. 9 is a schematic cross-sectional view showing an example of a semiconductor package;
fig. 10 is a schematic plan view taken along line I-I' of the semiconductor package of fig. 9;
fig. 11 is a schematic process diagram illustrating a part of a process of manufacturing the semiconductor package of fig. 9;
fig. 12 illustrates another example of a fan-out type semiconductor package; and
fig. 13 shows another example of a fan-out type semiconductor package.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.
This disclosure may, however, be embodied in many different forms and should not be construed as limited to the particular embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Throughout the specification, it will be understood that when an element such as a layer, region or wafer (substrate) is referred to as being "on," "connected to" or "bonded to" another element, it can be directly on, "connected to or" bonded to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there may be no other elements or layers intervening between the two. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be apparent that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, any such elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
Spatially relative terms, such as "above … …," "above," "below … …," and "below," may be used herein for ease of description to describe one element's relationship to another element as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "upper" relative to other elements would then be oriented "below" or "lower" relative to the other elements. Thus, the term "above … …" can encompass both an orientation of "above" and "below," depending on the particular orientation of the figure. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and the disclosure is not limited thereto. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and/or groups thereof.
Hereinafter, embodiments of the present disclosure will be described with reference to schematic drawings showing embodiments of the present disclosure. In the drawings, the deformation of the illustrated shape may be estimated, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The following embodiments may also be constructed singly, in combination, or in partial combination.
The disclosure described below may have various configurations and only required configurations are set forth herein, but is not limited thereto.
Electronic device
Fig. 1 is a schematic block diagram illustrating an example of an electronic device system.
Referring to fig. 1, the electronic device 1000 may accommodate a motherboard 1010. Motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. that are physically or electrically connected thereto. These components may be connected to other components described below by various signal lines 1090.
The chip related components 1020 may include the following chips, etc.: a memory chip such as a volatile memory (e.g., a Dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., a Read Only Memory (ROM)), a flash memory, or the like; an application processor chip such as a central processing unit (e.g., Central Processing Unit (CPU)), a graphics processor (e.g., Graphics Processing Unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and logic chips such as analog-to-digital converters, Application Specific Integrated Circuits (ASICs), and the like. However, the chip-related component 1020 is not limited thereto, but may also include other types of chip-related components. Further, the chip related components 1020 may be combined with each other.
Network-related components 1030 may include components that implement protocols such as: wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE)802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), evolution data optimized (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), Enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless and wired protocols specified after the above protocols. However, network-related components 1030 are not so limited, but may also include components that implement various other wireless or wired standards or protocols. Further, the network-related component 1030 may be combined with each other together with the above-described chip-related component 1020.
Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), and so forth. However, the other components 1040 are not limited thereto, and may also include passive components and the like for various other purposes. Further, the other components 1040 may be combined with each other together with the above-described chip-related component 1020 or network-related component 1030.
Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a Compact Disc (CD) drive (not shown), a Digital Versatile Disc (DVD) drive (not shown), and so forth. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000 and the like.
The electronic device 1000 may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, and so forth. However, the electronic device 1000 is not limited thereto, but may be any other electronic device that processes data.
Fig. 2 is a schematic perspective view showing an example of the electronic device.
Referring to fig. 2, the semiconductor package may be used for various purposes in various electronic devices 1000 as described above. For example, a printed circuit board 1110 such as a motherboard may be housed in the main body 1101 of the smartphone 1100, and various electronic components 1120 may be physically or electrically connected to the printed circuit board 1110. In addition, other components (such as camera module 1130) that may or may not be physically or electrically connected to printed circuit board 1110 may be housed in main body 1101. Some of the electronic components 1120 may be chip-related components, such as, but not limited to, semiconductor packages 1121. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.
Semiconductor package
Typically, a large number of microelectronic circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product, and may be damaged by external physical or chemical impact. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device or the like in a packaged state.
Here, the reason why the semiconductor package is required is that: in terms of electrical connections, there is often a difference in circuit width between the semiconductor chip and the motherboard of the electronic device. In detail, the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip are very fine, while the size of the component mounting pads of the main board used in the electronic device and the pitch between the component mounting pads of the main board are significantly larger than the size of the connection pads of the semiconductor chip and the pitch between the connection pads of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technique for alleviating the difference in circuit width between the semiconductor chip and the main board is required.
Semiconductor packages manufactured by the packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and purposes.
Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.
Fan-in type semiconductor package
Fig. 3A and 3B are schematic sectional views showing states of the fan-in type semiconductor package before and after being packaged.
Fig. 4 is a schematic sectional view illustrating a packaging process of a fan-in type semiconductor package.
Referring to fig. 3A, 3B, and 4, the semiconductor chip 2220 may be, for example, an Integrated Circuit (IC) in a bare state, the semiconductor chip 2220 including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like; a connection pad 2222 formed on one surface of the body 2221 and including a metal material such as aluminum (Al); and a passivation layer 2223, such as an oxide layer, a nitride layer, or the like, formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222. In this case, since the connection pads 2222 may be very small, it may be difficult to mount an Integrated Circuit (IC) on a medium-sized grade Printed Circuit Board (PCB) and a main board of an electronic device or the like.
Therefore, according to the size of the semiconductor chip 2220, the connection structures 2240 may be formed on the semiconductor chip 2220 to redistribute the connection pads 2222. The connecting structure 2240 may be formed by: an insulating layer 2241 is formed on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin, via holes 2243h that open the connection pads 2222 are formed, and then wiring patterns 2242 and vias 2243 are formed. Then, a passivation layer 2250 protecting the connection structure 2240 may be formed, an opening 2251 may be formed and an under bump metallization 2260 may be formed, etc. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection structure 2240, the passivation layer 2250, and the under bump metallization 2260 may be manufactured through a series of processes.
As described above, the fan-in type semiconductor package may have a package form in which all connection pads (e.g., input/output (I/O) terminals) of the semiconductor chip are disposed inside the semiconductor chip, may have excellent electrical characteristics, and may be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in a fan-in type semiconductor package form. In detail, many elements installed in a smart phone have been developed to achieve fast signal transmission while having a compact size.
However, in the fan-in type semiconductor package, since all the I/O terminals need to be disposed inside the semiconductor chip, the fan-in type semiconductor package has a large spatial limitation. Therefore, it is difficult to apply such a structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the above disadvantages, it may not be possible to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. The reason is that: even in the case where the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip are increased by the redistribution process, the size of the I/O terminals of the semiconductor chip and the pitch between the I/O terminals of the semiconductor chip may not be sufficient to allow the fan-in type semiconductor package to be directly mounted on the main board of the electronic device.
Fig. 5 is a schematic sectional view showing a case where the fan-in type semiconductor package is mounted on a printed circuit board and is finally mounted on a main board of an electronic device.
Fig. 6 is a schematic sectional view showing a case where the fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.
Referring to fig. 5 and 6, in the fan-in type semiconductor package 2200, connection pads 2222 (i.e., I/O terminals) of the semiconductor chip 2220 may be redistributed by the printed circuit board 2301, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device in a state where the fan-in type semiconductor package 2200 is mounted on the printed circuit board 2301. In this case, the solder balls 2270 and the like may be fixed by the underfill resin 2280 and the like, and the outside of the semiconductor chip 2220 may be covered with the molding material 2290 and the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate printed circuit board 2302, connection pads 2222 (i.e., I/O terminals) of the semiconductor chip 2220 may be redistributed through the printed circuit board 2302 in a state where the fan-in type semiconductor package 2200 is embedded in the printed circuit board 2302, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device.
As described above, it may be difficult to directly mount and use the fan-in type semiconductor package on the main board of the electronic device. Accordingly, the fan-in type semiconductor package may be mounted on a separate printed circuit board and then mounted on the main board of the electronic device through a packaging process, or the fan-in type semiconductor package may be mounted and used on the main board of the electronic device in a state in which the fan-in type semiconductor package is embedded in the printed circuit board.
Fan-out type semiconductor package
Fig. 7 is a schematic sectional view showing a fan-out type semiconductor package.
Referring to fig. 7, in the fan-out type semiconductor package 2100, for example, the outside of the semiconductor chip 2120 may be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by connection structures 2140. In this case, a passivation layer 2150 may be further formed on the connection structure 2140, and an under bump metal 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal 2160. The semiconductor chip 2120 may be an Integrated Circuit (IC) including a body 2121, connection pads 2122, and the like. The connecting structure 2140 may include: an insulating layer 2141; a wiring layer 2142 formed over the insulating layer 2141; and a via 2143 electrically connecting the connection pad 2122 and the wiring layer 2142 to each other.
As described above, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor chip are redistributed by the connection structure formed on the semiconductor chip and are disposed outside the semiconductor chip. As described above, in the fan-in type semiconductor package, all the I/O terminals of the semiconductor chip need to be provided inside the semiconductor chip. Therefore, as the size of the semiconductor chip is reduced, the size and pitch of the balls need to be reduced, so that a standardized ball layout may not be used in the fan-in type semiconductor package. On the other hand, as described above, the fan-out type semiconductor package has a form in which the I/O terminals of the semiconductor chip are redistributed by the connection structure formed on the semiconductor chip and are disposed outside the semiconductor chip. Therefore, even in the case where the size of the semiconductor chip is reduced, the standardized ball layout can be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate printed circuit board, as described below.
Fig. 8 is a schematic sectional view showing a case where the fan-out type semiconductor package is mounted on a main board of an electronic device.
Referring to fig. 8, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device by solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection structure 2140 formed on the semiconductor chip 2120 and enables the connection pads 2122 to be redistributed to the fan-out region outside the size of the semiconductor chip 2120, so that the standardized ball layout can be used as it is in the fan-out type semiconductor package 2100. As a result, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate printed circuit board or the like.
As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate printed circuit board, the fan-out type semiconductor package can be implemented in a thickness smaller than that of the fan-in type semiconductor package using the printed circuit board. Therefore, the fan-out type semiconductor package can be miniaturized and slimmed. In addition, the fan-out type semiconductor package has excellent thermal and electrical characteristics, making it particularly suitable for mobile products. Accordingly, the fan-out type semiconductor package can be realized in a more compact form than a general Package On Package (POP) type form using a Printed Circuit Board (PCB), and a problem due to the occurrence of a warpage phenomenon can be solved.
On the other hand, the fan-out type semiconductor package refers to a packaging technique for mounting a semiconductor chip on a main board or the like of an electronic device and protecting the semiconductor chip from external impact as described above, and is a concept different from that of a printed circuit board or the like such as a Printed Circuit Board (PCB) having a specification, a use, or the like different from that of the fan-out type semiconductor package and having a fan-in type semiconductor package embedded therein.
Hereinafter, a novel semiconductor package structure capable of significantly reducing corrosion and damage of connection pads of a semiconductor chip will be described with reference to the accompanying drawings.
Fig. 9 is a schematic cross-sectional view illustrating an example of a semiconductor package.
Fig. 10 is a schematic plan view taken along line I-I' of the semiconductor package of fig. 9.
Referring to fig. 9, a semiconductor package 100A according to an example may include a semiconductor chip 120, an encapsulant 130, and a connection structure 140, the semiconductor chip 120 having an active surface on which a connection pad 122 is disposed and an inactive surface opposite to the active surface and including a passivation film 123 and a protective film 124, the passivation film 123 being disposed on the active surface and having a first opening 123h exposing at least a portion of the connection pad 122, the protective film 124 being disposed on the passivation film 123, filling at least a portion of the first opening 123h and having a second opening 124h exposing at least a portion of the connection pad 122 in the first opening 123h, the encapsulant 130 covering at least a portion of the semiconductor chip 120, the connection structure 140 including: a first insulating layer 141a provided on the protective film 124 and having a via hole 143h connected to the second opening 124h and exposing at least a portion of the connection pad 122; a first redistribution layer 141b disposed on the first insulating layer 141 a; the first connection via 143a fills at least a portion of each of the via hole 143h and the second opening 124h and connects the connection pad 122 to the first redistribution layer 142 a. In this case, the second opening 124h is connected with the passage hole 143h to have a stepped portion. For example, a predetermined undercut (undercut) is provided to the protective film 124, and thus the wall surface of the second opening 124h is recessed toward the wall surface of the first opening 123 h. A recess region is disposed between the first insulating layer 141a and the connection pad 122, and the first connection via 143a may fill at least a portion of the recess region.
In addition, in the case of the semiconductor chip 120, the material of the connection pad 122 is typically aluminum (Al) or copper (Cu). In this case, in the process for manufacturing the package 100A, if no measures are taken, the connection pads 122 of the semiconductor chip 120 may be exposed to air, moisture, a chemical solution, or the like. Therefore, problems may occur that cause corrosion and damage. In detail, when the first connection via 143a is directly formed on the semiconductor chip 120 without any measures, the organic layer and the oxide layer on the surface of the connection pad 122 are removed by chemical treatment before the first insulating layer 141a, which typically includes a photosensitive dielectric (PID) material, is coated. In this case, the connection pad 122 may be damaged due to chemical treatment. In addition, in the formation process of the via hole 143h, the connection pad 122 is also damaged due to the PID developer. The damage may cause corrosion of the connection pad 122 and may roughen the surface roughness of the connection pad 122. Accordingly, the seed layer for forming the first connection via hole 143a is made uneven, and thus may cause corrosion of the connection pad 122 when a packaging process is performed later.
On the other hand, in a similar manner to the semiconductor package 100A according to the example, when the protective film 124 having the second opening 124h having a smaller width than the width of the first opening 123h is formed on the passivation film 123 having the first opening 123h, an area of the connection pad 122 exposed through the first opening 123h except for the area exposed through the second opening 124h may be covered with the protective film 124. In this regard, in the process for manufacturing the package 100A, exposure of the connection pad 122 to air, moisture, a chemical solution, etc. may be significantly reduced, and thus corrosion and damage may be significantly reduced. Here, the width refers to a width in a sectional view (e.g., fig. 9). When the corresponding opening is tapered, the width represents the widest width.
In detail, the protective film 124 may serve as a barrier to prevent oxidation and corrosion of the connection pad 122 that may occur in a process for forming the first insulating layer 141a of the connection structure 140. Thereafter, after the via hole 143h is formed in the first insulating layer 141a, only the protective film 124 in the region of the via hole 143h is selectively removed to connect the via hole 143h to the second opening 124 h. Therefore, an electrical connection path through the first connection via 143a is easily provided. In other words, although the first insulating layer 141a such as PID for forming the first redistribution layer 142a is introduced in a similar manner to the related art, oxidation and corrosion of the connection pad 122 may be significantly reduced by the protective film 124. In this case, the first insulating layer 141a may be physically spaced apart from the connection pad 122 by the protective film 124, and the first insulating layer 141a may fill at least a portion of a space between the protective film 124 and the first connection via 143a, which is located in the first opening 123 h.
In detail, the second opening 124h is connected with the passage hole 143h to have a stepped portion. For example, the protective film 124 and the first insulating layer 141a may include different materials. In the process of forming the via hole 143h in the first insulating layer 141a and then selectively removing the protective film 124 located in the region of the via hole 143h, a predetermined undercut may be provided in the formation region of the second opening 124h of the protective film 124. In other words, in a connection point of the second opening 124h and the via hole 143h, the width of the second opening 124h may be wider than the width of the via hole 143 h. As a result, the wall surface of the second opening 124h is recessed toward the wall surface of the first opening 123h, a recessed region is disposed between the first insulating layer 141a and the connection pad 122, and the first connection via 143a may fill at least a portion of the recessed region. Accordingly, the first connection through hole 143a may have a portion in which: the width of the portion is smaller than the width of the uppermost portion of the first connection via 143a in contact with the connection pad 122 and the width of the lowermost portion of the first connection via 143a in contact with the first redistribution layer 142 a. In this case, the contact area of the first connection through hole 143a is widened, and an anchor effect (anchor effect) due to the stepped portion is also provided. In this regard, the reliability of the first connection via 143a connected to the connection pad 122 may be improved, and the resist distribution may also be reduced.
On the other hand, the second opening 124h may be gradually narrowed to have a predetermined inclination angle α 1 with respect to an interface between the protective film 124 and the first insulating layer 141a parallel to the lower surface of the connection pad 122, and the via hole 143h may be gradually narrowed to have a predetermined inclination angle α 2 with respect to an interface between the protective film 124 and the first insulating layer 141a parallel to the lower surface of the connection pad 122.
Further, before the semiconductor chip 120 is packaged, the protective film 124 is preferably formed on the passivation film 123 having the first opening 123h exposing the connection pad 122 of the semiconductor chip 120 in a chip state. In this case, the protective film 124 is formed on the passivation film 123 as described above, and the protective film 124 is also provided in a region within the effective surface of the semiconductor chip 120. In addition, the encapsulant 130 may cover not only the side surface of the passivation film 123 but also the side surface of the protection film 124. In addition, the encapsulant 130 may fill a portion between the protective film 124 and the first insulating layer 141a of the connection structure 140. As described above, since the protective film 124 is formed in a chip state (e.g., a wafer state), only good products are selected before packaging, and thus yield can be improved. Further, it is not necessary to form the protective film 124 even to other components such as the encapsulant 130 or the frame 110, and thus the process can be simplified and the cost can be reduced. In addition, contamination of the connection pads 122 can be significantly reduced more effectively.
Hereinafter, each component included in the semiconductor package 100A according to an exemplary embodiment will be described in more detail.
The frame 110 as an additional component may improve rigidity of the fan-out type semiconductor package 100A according to a specific material of the insulating layer 111 and serves to ensure uniformity of thickness of the encapsulant 130. The frame 110 may have a via hole 110H passing through the insulating layer 111. In the through hole 110H, the semiconductor chip 120 is disposed, and passive components (not shown) may be disposed together as necessary. The through-hole 110H may have a form of a wall surface surrounding the semiconductor chip 120, but is not limited thereto.
The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer 111. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a thermosetting resin, or a material in which a thermoplastic resin is impregnated in a core material such as glass fiber (or glass cloth) together with an inorganic filler, for example, a Copper Clad Laminate (CCL), an Unclad copper clad laminate (CCL Unclad), a prepreg, or the like, but is not limited thereto. The material of the insulating layer 111 may be glass, ceramic, or the like, if necessary. The lower surface of the insulating layer 111 is coplanar with the lowermost surface of the protective film 124 of the semiconductor chip 120. This is because the protective film 124 is formed in a chip state.
In addition, although not shown in the drawings, if necessary, a metal layer (not shown) may be disposed on a wall surface of the through-hole 110H of the frame 110 for the purpose of electromagnetic shielding or for heat dissipation, and the metal layer (not shown) may surround the semiconductor chip 120.
The semiconductor chip 120 may be an Integrated Circuit (IC) provided by integrating a number of elements in a single chip of hundreds to millions or more. In this case, the IC may be, for example, an application processor chip such as, but not limited to, a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like. Here, the IC may be a power management IC (pmic), a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or a logic chip such as an analog-to-digital converter, an application specific IC (asic).
The semiconductor chip 120 may be an integrated circuit in a bare state without providing a separate bump or wiring layer. However, the semiconductor chip 120 is not limited thereto, and the semiconductor chip 120 may be a package type integrated circuit if necessary. The integrated circuits may be placed based on the active wafer. In this case, the base material of the body 121 of the semiconductor chip 120 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body 121. The connection pads 122 may electrically connect the semiconductor chip 120 to other components. The material of each of the connection pads 122 may be a metal material such as aluminum (Al), copper (Cu), or the like, without limitation. A passivation film 123 having a first opening 123h exposing at least a portion of the connection pad 122 is formed on the body 121, and the passivation film 123 may be an oxide film or a nitride film. Although the passivation film 123 is illustrated as having a thickness similar to that of the connection pad 122, it is not limited thereto. Optionally, passivatingThe film 123 may have a thickness thinner than that of the connection pad 122. A protective film 124 filling at least a portion of the first opening 123h and having a second opening 124h exposing at least a portion of the connection pad 122 in the first opening 123h may be formed on the passivation film 123, and the protective film 124 may also be an oxide film or a nitride film that is the same as or different from the passivation film 123. In detail, the protective film 124 may be utilized to have an insulating property (e.g., SiO)2、SiN、TiO2、ZnO、Al2O3Other polymers), the thickness of the protective film 124 may be thinner than that of the passivation film 123, for example, about 1nm to about 500 nm. Such as SiO2The insulating film (not shown) of (a) may be further disposed in other desired positions, for example, in a space between the body 121, the connection pad 122, and the passivation film 123. Further, in the semiconductor chip 120, the side on which the connection pad 122 is provided is an effective surface, and the opposite side is an ineffective surface.
The encapsulant 130 may cover at least a portion of the semiconductor chip 120. When the frame 110 is disposed, the encapsulant 130 may cover at least a portion of the frame 110. Further, the encapsulant may fill at least a portion of the via 110H. The encapsulant 130 may include an insulating material. The insulating material may be a material containing an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a reinforcing material such as an inorganic filler is contained in a thermosetting resin or a thermoplastic resin (in detail, ABF (Ajinomoto build-up film), FR-4 resin, Bismaleimide Triazine (BT) resin), or the like. Further, a molding material such as EMC may be used, or a photosensitive material, for example, a photosensitive encapsulant (PIE), may be used as needed. As required, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in a core material such as an inorganic filler and/or glass fiber (or glass cloth) may be used.
Further, before the semiconductor chip 120 is packaged, the protective film 124 is preferably formed on the passivation film 123 having the first opening 123h exposing the connection pad 122 of the semiconductor chip 120 in a chip state. In this case, the protective film 124 is formed on the passivation film 123 as described above, and the protective film 124 is also provided in a region inside the effective surface of the semiconductor chip 120. In addition, the encapsulant 130 may cover not only the side surface of the passivation film 123 but also the side surface of the protection film 124. In addition, the encapsulant 130 may fill a portion between the protective film 124 and the first insulating layer 141a of the connection structure 140. As described above, since the protective film 124 is formed in a chip state (e.g., a wafer state), only good products are selected before packaging, and thus yield can be improved. Further, it is not necessary to form the protective film 124 even to other components such as the encapsulant 130 or the frame 110, and thus the process can be simplified and the cost can be reduced. In addition, contamination of the connection pads 122 can be significantly reduced more effectively.
The connection structures 140 may redistribute the connection pads 122 of the semiconductor chip 120. Tens to hundreds of connection pads 122 of the semiconductor chip 120 having various functions may be redistributed by the connection structure 140 and may be physically connected to the outside or electrically connected to the outside through the electrical connection metal 170 according to the function. The connection structure 140 includes: a first insulating layer 141a disposed on the active surface of the semiconductor chip 120 and having a via hole 143h connected to the second opening 124h and exposing at least a portion of the connection pad 122 in the second opening 124 h; a first redistribution layer 142a disposed on the first insulating layer 141 a; a first connection via 143a filling at least a portion of each of the via hole 143h and the second opening 124h and electrically connecting the connection pad 122 to the first redistribution layer 142 a; a second insulating layer 141b disposed on the first insulating layer 141a and covering at least a portion of the first redistribution layer 142 a; a second redistribution layer 142b disposed on the second insulating layer 141 b; and a second connection via 143b passing through the second insulating layer 141b and electrically connecting the first redistribution layer 142a to the second redistribution layer 142 b. These may be more or less than what is shown in the figures.
The material of the first and second insulating layers 141a and 141b may be an insulating material. In this case, the insulating material may be a photosensitive dielectric (PID) material. In this case, a fine pitch may be introduced through the photolithographic via (photovia), and thus tens to millions of connection pads 122 of the semiconductor chip 120 may be effectively redistributed. The first and second insulating layers 141a and 141b may have boundaries separated from each other. The first insulating layer 141a may be physically spaced apart from the connection pad 122 by the protective film 124. The first insulating layer 141a may fill at least a portion of a space between the protective film 124 and the first connection via hole 143a in the first opening 123 h.
The first and second redistribution layers 142a and 142b may redistribute the connection pads 122 of the semiconductor chip 120 to be electrically connected to the electrical connection metal 170. The material of the first and second redistribution layers 142a and 142b may be a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer may also perform various functions depending on its design. For example, the redistribution layer may include a Ground (GND) pattern, a Power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern, etc., in addition to a Ground (GND) pattern, a Power (PWR) pattern, etc. Additionally, the redistribution layer may include via pads, electrical connection metal pads, and the like.
The first connection via 143a may electrically connect the connection pad 122 of the semiconductor chip 120 to a first redistribution layer 142a formed in a different layer, and the second connection via 143b may electrically connect the first redistribution layer 142a to a second redistribution layer 142b formed in a different layer. When the semiconductor chip 120 is a bare chip, the first connection via 143a may physically contact the connection pad 122. The material of the connection via 143 may also be a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first and second connection vias 143a and 143b may be a filling type in which the via hole is completely filled with a metal material, or a conformal type in which a metal material is coated along a wall surface of the via hole. In addition, the first and second connection through holes 143a and 143b may employ a tapered shape.
In addition, the first redistribution layer 142a and the first connection via hole 143a may be simultaneously formed using a plating process. In this case, a seed layer and a plating layer formed on the seed layer may be included. In detail, the seed layer may be formed very thin by sputtering the exposed surface of the connection pad, the wall surface of the via hole, and the surface of the first insulating layer, and the seed layer may include a titanium (Ti) layer or a titanium (Ti)/copper (Cu) double layer. A plating layer is formed on the seed layer by electroplating, filling the via hole 143h and the second opening 124 h. The second redistribution layer 142b and the second connection via 143b may be simultaneously formed using a plating process in a similar manner. In this case, a seed layer and a plating layer may be included.
The passivation layer 150 as an additional component may protect the connection structure 140 from external physical or chemical damage. The passivation layer 150 may include an insulating resin and an inorganic filler, but may not include glass fiber. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 may have a third opening 150h exposing at least a portion of the second redistribution layer 142 b.
The under bump metallization 160 as an additional component may improve the connection reliability of the electrical connection metallization 170 to improve the board-level reliability of the semiconductor package 100A. The number of the underbump metallization 160 may be several tens to several millions. Each of the under bump metallurgy 160 may be connected to the second redistribution layer 142b through the third opening 150h passing through the passivation layer 150. The under bump metallization 160 may be formed by any known metallization method using metal, but is not limited thereto.
The electrical connection metal 170 physically and/or electrically connects the semiconductor package 100A to an external power source. For example, the semiconductor package 100A may be mounted on a motherboard of an electronic device through the electrical connection metal 170. The electrical connection metal 170 may be formed using a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). In more detail, the electrical connection metal 170 may be formed using solder or the like. However, this is merely an example, and the material of the electrical connection metal 170 is not particularly limited thereto. Each of the electrical connection metals 170 may be a pad, a solder ball, a pin, etc. The electrical connection metal 170 may be formed in a multi-layer or single-layer structure. When the electrical connection metal includes a plurality of layers, the electrical connection metal includes a copper pillar and a solder. When the electrical connection metal includes a single layer, the electrical connection metal includes tin-silver solder or copper. However, the electrical connection metal is only an example, and the present disclosure is not limited thereto. The number, interval, arrangement form, etc. of the electrical connection metals 170 are not particularly limited, but may be sufficiently modified by those skilled in the art according to the design details. For example, the electrical connection metals 170 may be disposed in a number of tens to thousands, or may be disposed in a number of tens to thousands or more, or tens to thousands or less, according to the number of the connection pads 122.
At least one of the electrical connection metals 170 may be disposed in the fan-out region. The fan-out region refers to a region other than the region where the semiconductor chip 120 is disposed. For example, the semiconductor package 100A according to an exemplary embodiment may be a fan-out type semiconductor package. The fan-out package may have excellent reliability, may realize a plurality of input/output (I/O) terminals, and may facilitate 3D interconnection, compared to the fan-in package. In addition, the fan-out type package may be manufactured to have a small thickness and may have price competitiveness as compared to a Ball Grid Array (BGA) package, a Land Grid Array (LGA) package, or the like.
Fig. 11 is a schematic process diagram illustrating a part of a process of manufacturing the semiconductor package of fig. 9.
Referring to fig. 11, first, in a chip state (e.g., a wafer state), a protective film 124 covering the passivation film 123 and the connection pad 122 is formed on the passivation film 123. The protective film 124 is formed to completely cover the already exposed surface of the connection pad 122 and the wall surface of the first opening 123h of the passivation film 123. Then, a first insulating layer 141a is formed over the protective film 124. In this case, since the connection pad 122 is covered with the protective film 124, contamination problems occurring in the process of forming the first insulating layer 141a and the via hole 143h can be significantly reduced. After the first insulating layer 141a is formed, a via hole 143h is formed using a photolithography method. Then, the protective film 124 is selectively removed from the region of the via hole 143h by etching, thereby forming a second opening 124h exposing the connection pad 122. In this case, by forming the undercut, the wall surface of the second opening 124h is recessed toward the wall surface of the first opening 123 h. Then, a seed layer is formed by sputtering while forming a first connection via hole 143a filling the via hole 143h and the second opening 124h and a first redistribution layer 142a disposed on the first insulating layer 141a by a plating process such as a semi-additive process (SAP) or a modified semi-additive process (MSAP). The first connection through hole 143a may include a first portion filling the second opening 124h and a second portion filling the via hole 143 h. The first and second portions of the first connection through hole 143a may be tapered in opposite directions. Then, the second insulating layer 141b is formed. As described above, through a series of processes, in a chip state, the connection pad 122 is first protected by the protective film 124, and then the connection structure 140 is formed. Therefore, the contamination problem of the connection pad 122 can be effectively solved. Further, a concave space is formed when the second opening 124h of the protective film 124 is formed. Accordingly, the recess space is filled with the first connection via 143a, thereby improving reliability and reducing resist distribution.
Fig. 12 schematically illustrates another example of a semiconductor package.
Referring to fig. 12, a semiconductor package 100B according to another example may have a frame 110, the frame 110 having a shape different from that of the frame 110 of the semiconductor package 100A according to the above example. In detail, the frame 110 may include a plurality of wiring layers 112a, 112b, and 112c electrically connected to the connection pads 122. In other words, the frame 110 may include wiring layers 112a, 112b, and 112c and wiring vias 113a and 113b in addition to the insulating layers 111a and 111b, and thus may serve as a connection structure. In this case, the wiring layers 112a, 112b, and 112c and the wiring vias 113a and 113b may serve as electrical connection members.
In more detail, the frame 110 may include: a first insulating layer 111a contacting the connection structure 140; a first wiring layer 112a in contact with the connection structure 140 and embedded in the first insulating layer 111 a; a second wiring layer 112b provided on a side of the first insulating layer 111a opposite to a side of the first insulating layer 111a where the first wiring layer 112a is embedded; a second insulating layer 111b provided on a side of the first insulating layer 111a opposite to a side of the first insulating layer 111a where the first wiring layer 112a is embedded and covering at least a part of the second wiring layer 112 b; and a third wiring layer 112c provided on a side of the second insulating layer 111b opposite to a side of the second insulating layer 111b in which the second wiring layer 112b is embedded. The first and second wiring layers 112a and 112b and the second and third wiring layers 112b and 112c may be electrically connected to each other through first and second wiring vias 113a and 113b, respectively, which pass through the first and second insulating layers 111a and 111 b. The first to third wiring layers 112a, 112b and 112c may be electrically connected to the connection pad 122 through the first and second redistribution layers 142a and 142b of the connection structure 140.
The material of each of the first insulating layer 111a and the second insulating layer 111b is not particularly limited. For example, an insulating material may be used as a material of each of the first insulating layer and the second insulating layer. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler, for example, ABF (Ajinomoto build-up film) or the like. Alternatively, the insulating material may be a material in which a thermosetting resin or a thermoplastic resin is impregnated in a core material such as glass fiber (or glass cloth) together with an inorganic filler, for example, a prepreg. The lower surface of the first insulating layer 111a is coplanar with the lowermost surface of the protective film 124 of the semiconductor chip 120. This is because the protective film 124 is formed in a chip state.
The first to third wiring layers 112a, 112b and 112c may set up upper/lower electrical connection paths of the package using the first and second wiring vias 113a and 113b and may serve to redistribute the connection pads 122. The material of the first to third wiring layers 112a, 112b, and 112c may be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The wiring layers 112a, 112b, and 112c may perform various functions according to the design of the respective layers. For example, the wiring layer may include a Ground (GND) pattern, a Power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern, etc., in addition to a Ground (GND) pattern, a Power (PWR) pattern, etc. In addition, the routing layer may include via pads, line pads, electrically connecting metal pads, and the like. The first to third wiring layers 112a, 112b, and 112c may be formed using a known plating process, and each wiring layer may be formed using a seed layer and an electroplating layer. A thickness of each of the first to third wiring layers 112a, 112b, and 112c may be thicker than a thickness of each of the first and second redistribution layers 142a and 142 b. The first wiring layer 112a may be recessed inside the first insulating layer 111 a. As described above, when the first wiring layer 112a is recessed inside the first insulating layer 111a and a step is provided between the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a, the first wiring layer 112a can be prevented from being contaminated due to bleeding of the forming material of the encapsulant 130.
The first and second wire vias 113a and 113b may electrically connect the first to third wire layers 112a, 112b, and 112c formed on different layers to each other, thereby forming an electrical path in the frame 110. The material of the first and second wire vias 113a and 113b may be a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first and second wire vias 113a and 113b may be a filled via filled with a metal material, or may be a conformal via in which a metal material is formed along a wall surface of a via hole. Further, the first and second wiring vias 113a and 113b may employ a tapered shape. The first and second wiring vias 113a and 113b may also be formed using a known plating process, and each of the first and second wiring vias 113a and 113b may be formed using a seed layer and a plating layer.
When forming the hole for the first wiring via 113a, some of the pads of the first wiring layer 112a may function as stoppers. In this regard, it may be advantageous in a process in which the first wire via 113a has a tapered shape in which the width of the upper surface is greater than the width of the lower surface. In this case, the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112 b. When forming the hole for the second wiring via 113b, some of the pads of the second wiring layer 112b may function as stoppers. In this regard, it may be advantageous in a process in which the second wire via 113b has a tapered shape in which the width of the upper surface is greater than the width of the lower surface. In this case, the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112 c.
The encapsulant 130 may have a fourth opening 130h, the fourth opening 130h exposing at least a portion of the third wiring layer 112c of the frame 110, and a surface treatment layer (not shown) such as nickel (Ni)/gold (Au) may be formed on a surface of the third wiring layer 112c exposed through the fourth opening 130 h. Other contents are repeated as those described above with reference to fig. 9 to 11, and thus, detailed descriptions thereof are omitted.
Fig. 13 schematically illustrates another example of a semiconductor package. Referring to fig. 13, a semiconductor package 100C according to another example may also have a frame 110, the frame 110 having a shape different from that of the frame of the semiconductor package 100A according to the above example. In detail, the frame 110 may include a plurality of wiring layers 112a, 112b, 112c, and 112d electrically connected to the connection pads 122. In other words, the frame 110 may include wiring layers 112a, 112b, 112c, and 112d and wiring vias 113a, 113b, and 113c in addition to the insulating layers 111a, 111b, and 111c, and thus may serve as a connection structure. In this case, the wiring layers 112a, 112b, 112c, and 112d and the wiring vias 113a, 113b, and 113c may serve as electrical connection members.
In more detail, the frame 110 includes: a first insulating layer 111 a; a first wiring layer 112a provided on a lower surface of the first insulating layer 111 a; a second wiring layer 112b provided on the upper surface of the first insulating layer 111 a; a second insulating layer 111b provided on a lower surface of the first insulating layer 111a and covering at least a part of the first wiring layer 112 a; a third wiring layer 112c provided on the lower surface of the second insulating layer 111 b; a third insulating layer 111c provided on the upper surface of the first insulating layer 111a and covering at least a part of the second wiring layer 112 b; a fourth wiring layer 112d provided on the upper surface of the third insulating layer 111 c; a first wiring via 113a passing through the first insulating layer 111a and electrically connecting the first wiring layer 112a to the second wiring layer 112 b; a second wiring via 113b passing through the second insulating layer 111b and electrically connecting the first wiring layer 112a to the third wiring layer 113 c; and a third wiring via 113c passing through the third insulating layer 111c and electrically connecting the second wiring layer 112b to the fourth wiring layer 112 d. Since the frame 110 may include a greater number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 may be further simplified.
The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111 c. The first insulating layer 111a may be substantially relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a greater number of wiring layers 112c and 112 d. Similarly, the diameter of the first wire via 113a passing through the first insulating layer 111a may be larger than the diameter of the second wire via 113b passing through the second insulating layer 111b and the diameter of the third wire via 113c passing through the third insulating layer 111 c. The first wiring via 113a may have an hourglass shape or a cylindrical shape, and the second and third wiring vias 113b and 113c may have tapered shapes with directions opposite to each other. A thickness of each of the first to fourth wiring layers 112a, 112b, 112c, and 112d may be thicker than a thickness of each of the first and second redistribution layers 142a and 142 b. The lower surface of the third wiring layer 112c is coplanar with the lowermost surface of the protective film 124 of the semiconductor chip 120. This is because the protective film 124 is formed in a chip state. The materials or functions including the first to fourth wiring layers 112a, 112b, 112c, and 112d and the first to third wiring vias 113a, 113b, and 113c, and the other contents of the fourth opening 130h and the like are repeated as those described above with reference to fig. 9 to 12. Therefore, a detailed description thereof is omitted.
As set forth above, according to exemplary embodiments, a new semiconductor package structure capable of significantly reducing corrosion and damage to connection pads of a semiconductor chip, and improving reliability of connection vias and reducing resist distribution may be provided.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention defined by the appended claims.
