阅读说明：本技术 封装结构 (Packaging structure ) 是由 陈宪伟 陈明发 叶松峯 于 2019-01-29 设计创作，主要内容包括：一种封装结构包括至少一个第一半导体管芯、绝缘封装体、隔离层及重布线层。至少一个第一半导体管芯具有半导体衬底及安置在半导体衬底上的导电杆。绝缘封装体部分地包封第一半导体管芯,其中导电杆具有被绝缘封装体环绕的第一部分及从绝缘封装体凸出的第二部分。隔离层安置在绝缘封装体上且环绕导电杆的第二部分。重布线层安置在第一半导体管芯及隔离层上,其中重布线层电连接到第一半导体管芯的所述导电杆。(A package structure includes at least one first semiconductor die, an insulating package, an isolation layer, and a redistribution layer. At least one first semiconductor die has a semiconductor substrate and a conductive bar disposed on the semiconductor substrate. An insulating package partially encapsulates the first semiconductor die, wherein the conductive posts have first portions surrounded by the insulating package and second portions protruding from the insulating package. An isolation layer is disposed on the insulating package and surrounds the second portion of the conductive rod. A redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive bars of the first semiconductor die.)

1. A package structure, comprising:

at least one first semiconductor die having a semiconductor substrate and conductive posts disposed on the semiconductor substrate;

an insulating package partially encapsulating the first semiconductor die, wherein the conductive bar has a first portion surrounded by the insulating package and a second portion protruding from the insulating package;

an isolation layer disposed on the insulating package and surrounding the second portion of the conductive rod; and

a redistribution layer disposed on the first semiconductor die and the isolation layer, the redistribution layer electrically connected to the conductive bars of the first semiconductor die.

Technical Field

The present disclosure relates to a package structure, and more particularly, to an integrated fan-out package structure.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by the following steps: layers of insulating or dielectric material, conductive material, and semiconductor material are sequentially deposited over a semiconductor substrate, and photolithography is used to pattern the various material layers to form circuit elements and components thereon. Many semiconductor integrated circuits are typically fabricated on a single semiconductor wafer. The die of the wafer may be processed and packaged at the wafer level, and various techniques have been developed for performing wafer level packaging.

Disclosure of Invention

A package structure of an embodiment of the present invention includes at least one first semiconductor die, an insulating package, an isolation layer, and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive bar disposed on the semiconductor substrate. The insulating package partially encapsulates the first semiconductor die, wherein the conductive posts have first portions surrounded by the insulating package and second portions protruding from the insulating package. The isolation layer is disposed on the insulating package and surrounds the second portion of the conductive rod. The redistribution layer is disposed on the first semiconductor die and the isolation layer, the redistribution layer being electrically connected to the conductive bars of the first semiconductor die.

Drawings

Aspects of embodiments of the present invention are best understood from the following detailed description when read with the accompanying drawing figures. Note that, according to standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-9 are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some example embodiments of the present disclosure.

Fig. 10A and 10B are schematic cross-sectional views of stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure.

Fig. 11A-11C are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure.

Fig. 12A and 12B are schematic cross-sectional views of stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure.

Fig. 13A-13C are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure.

[ description of symbols ]

10A, 10B, 10C, 10D: laminated packaging structure

102: carrier

104: buffer layer

104A: debonding layer

104B: dielectric layer

106A: first semiconductor die

106 a-1: semiconductor substrate

106a-2, 114C, 250: conductive pad

106 a-3: passivation layer

106 a-4: conducting rod

106 a-5: protective layer

106B: second semiconductor die

106 b-1: a second semiconductor substrate

106 b-2: second conductive rod

106 TSC: top surface of conductive rod

106 TSCx: top surface of the second conductive rod

106 TSP: top surface of the protective layer

108: through insulating layer hole

108 TS: top surface of through-insulation layer hole

110: insulating material

110': insulating package

110 TS: top surface of insulating package

112: insulating material

112': insulating layer

112 TS: top surface of the isolation layer

114: redistribution layer

114A: dielectric layer/first dielectric layer

114B: box layer

116. 118: conductive ball

117: integrated passive device

210: substrate

220: semiconductor chip

230: bonding wire

240: connecting pad

260: insulating package

270: underfill

301: strip tape

302: frame structure

AS: active surface

BS: backside surface

CE: connecting element

DF: tube core laminating film

HR: pouring way hole

MD: die set

P1: the first part

P2: the second part

PK1, PK 2: packaging structure

RF: release film

T1: thickness of the spacer layer

T2: thickness of insulating package

W1: width of the second conductive rod

W2: width of the conductive rod

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to provide a concise embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, formation of a second feature over or on a first feature may include embodiments in which the second feature is formed in direct contact with the first feature, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature and the first feature may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "on," "over," "overlying," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Other features and processes may also be included. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structure may include test pads formed, for example, in a redistribution layer or on a substrate, which allow 3D packages or 3DIC testing using probes and/or probe cards, and the like. Verification tests may be performed on the intermediate structures and the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include verifying known good dies at an intermediate stage to improve yield and reduce cost.

Fig. 1-9 are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some example embodiments of the present disclosure. Referring to fig. 1, a carrier 102 is provided, the carrier 102 being coated with a buffer layer 104. In one embodiment, carrier 102 may be a glass carrier or any suitable carrier for carrying semiconductor wafers or reconstituted wafers to which the method of fabricating a package structure is to be applied.

In some embodiments, the buffer layer 104 includes a debonding layer 104A and a dielectric layer 104B, wherein the debonding layer 104A is located between the carrier 102 and the dielectric layer 104B. In certain embodiments, the debonding layer 104A is disposed on the carrier 102, and the material of the debonding layer 104A may be any material suitable for bonding the carrier 102 and peeling the carrier 102 from an overlying layer (e.g., the dielectric layer 104B) or from any wafer disposed on the debonding layer 104A. In some embodiments, the release layer 104A may include a release layer (e.g., a light-to-heat conversion ("LTHC") layer) or an adhesive layer (e.g., an ultraviolet-curable adhesive layer or a thermally-curable adhesive layer). In some embodiments, a dielectric layer 104B may be formed over the debonding layer 104A. The dielectric layer 104B may be made of a dielectric material, such as benzocyclobutene ("BCB"), polybenzoxazole (polybenzoxaz0le, "PBO"), or any other suitable polymer-based dielectric material.

Note that the material of the carrier 102, the material of the debonding layer 104A, and the material of the dielectric layer 104B are not limited to the description of the embodiment. In some alternative embodiments, the dielectric layer 104B may be optionally omitted; in other words, only the debonding layer 104A may be formed on the carrier 102. In some embodiments, a die attach film (not shown) may be formed directly on the release layer 104A for attachment to an overlying component.

After the buffer layer 104 is provided, a plurality of through-insulating layer holes 108 are formed on the buffer layer 104 and above the carrier 102, and a plurality of first semiconductor dies 106A are provided on the buffer layer 104. In some embodiments, the through insulator layer holes 108 are integrated fan-out ("InFO") perforations. In one embodiment, forming the through insulation layer hole 108 includes forming a mask pattern (not shown) having an opening, then forming a metal material (not shown) by electroplating or deposition to fill the opening, and removing the mask pattern to form the through insulation layer hole 108 on the buffer layer 104. The material of the mask pattern may include a positive photoresist or a negative photoresist. In one embodiment, the material of the through insulation layer hole 108 may include a metal material, such as copper or a copper alloy. However, embodiments of the invention are not limited in this regard.

In an alternative embodiment, the through-insulator hole 108 may be formed by: forming a seed layer (not shown) on the buffer layer 104; forming a mask pattern having openings such that portions of the seed layer are exposed; forming a metal material on the exposed portion of the seed layer by plating to form a through insulating layer hole 108; removing the mask pattern; and then the portion of the seed layer exposed by the through insulating layer hole 108 is removed. For example, the seed layer may be a titanium/copper composite layer. For simplicity, only four through insulation layer holes 108 are illustrated in fig. 1. It should be noted, however, that the number of through insulation layer holes 108 is not limited thereto and may be selected based on requirements.

As shown in fig. 1, one or more first semiconductor die 106A may be picked up and placed on the buffer layer 104. In some embodiments, the first semiconductor die 106A has an active surface AS and a backside surface BS opposite the active surface AS. For example, the backside surface BS of the first semiconductor die 106A may be attached to the buffer layer 104 by a die attach film DF. By using the die attach film DF, better adhesion between the first semiconductor die 106A and the buffer layer 104 is ensured. In the exemplary embodiment, only two first semiconductor dies 106A are illustrated. However, embodiments of the invention are not limited in this regard. It should be noted that the number of first semiconductor dies 106A disposed on the buffer layer 104 may be adjusted based on product requirements.

In an exemplary embodiment, each of the first semiconductor dies 106A includes a semiconductor substrate 106A-1, a plurality of conductive pads 106A-2, a passivation layer 106A-3, a plurality of conductive bars 106A-4, and a protective layer 106A-5. As shown in fig. 1, the plurality of conductive pads 106a-2 is disposed on a semiconductor substrate 106 a-1. The passivation layer 106a-3 is formed over the semiconductor substrate 106a-1 and has an opening that partially exposes the conductive pad 106a-2 located on the semiconductor substrate 106 a-1. The semiconductor substrate 106a-1 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate and also includes active components (e.g., transistors, etc.) and optionally passive components (e.g., resistors, capacitors, inductors, etc.) formed in the semiconductor substrate 106 a-1. The conductive pads 106a-2 may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 106a-3 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material. Further, in some embodiments, a post-passivation layer (not shown) is optionally formed over the passivation layer 106 a-3. The post-passivation layer covers the passivation layer 106a-3 and has a plurality of contact openings. The contact opening of the post passivation layer partially exposes the conductive pad 106 a-2. The post-passivation layer may be a benzocyclobutane (BCB) layer, a polyimide layer, a Polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers. In some embodiments, the conductive posts 106a-4 are formed by plating on the conductive pads 106 a-2. In some embodiments, the protective layer 106a-5 is formed on the passivation layer 106a-3 or on a subsequent passivation layer, and the protective layer 106a-5 covers the conductive rod 106a-4 to protect the conductive rod 106 a-4.

In some embodiments, when more than one first semiconductor die 106A is placed on the buffer layer 104, the first semiconductor dies 106A may be arranged in an array, and when the first semiconductor dies 106A are arranged in an array, the through-insulator holes 108 may be divided into groups. The number of first semiconductor die 106A may correspond to the number of groups of through insulator holes 108. In the illustrated embodiment, the first semiconductor die 106A may be picked up and placed on the buffer layer 104 after the through-insulator hole 108 is formed. However, embodiments of the invention are not limited in this regard. In some alternative embodiments, the first semiconductor die 106A may be picked up and placed on the buffer layer 104 prior to forming the through-insulator layer hole 108.

In some embodiments, the first semiconductor die 106A may be selected from an application-specific integrated circuit (ASIC) chip, an analog chip (e.g., a radio frequency (rf) chip), a digital chip (e.g., a baseband chip), an Integrated Passive Device (IPD), a voltage regulator chip, a sensor chip, a memory chip, and the like. Embodiments of the invention are not limited in this respect.

Referring to fig. 2A, in a next step, a mold MD is provided on the carrier 102, covering the first semiconductor die 106A and the plurality of through-insulator holes 108. In some embodiments, the mold MD may include runner holes HR and a release film RF fitted to the inner surface of the mold MD. The gate hole HR is located on one side of the die MD. In some embodiments, the release film RF is pressed onto the first semiconductor die 106A to partially cover the first semiconductor die 106A. In some embodiments, the release film RF is also pressed onto the through insulating layer hole 108 to partially cover the through insulating layer hole 108. Fig. 2B is a top view of the structure shown in fig. 2A, in which the mold MD, the release film RF, and the through insulating layer hole 108 are omitted for illustration purposes. As shown in fig. 2B, the first semiconductor die 106A is located on the buffer layer 104 and exposes a top surface of the buffer layer 104 before forming the insulating package.

Referring to fig. 3A, an insulating material 110 is injected into the mold MD through the runner hole RH such that the insulating material 110 partially encapsulates the first semiconductor die 106A and the through-insulating layer hole 108. Fig. 3B is a top view of the structure shown in fig. 3A, in which the mold MD, the release film RF, and the through insulating layer hole 108 are omitted for illustration purposes. As shown in fig. 3B, the insulating material 110 is injected from one side of the die MD and diffused onto the buffer layer 104 to cover the buffer layer 104. In some embodiments, the insulating material 110 diffuses and surrounds each of the first semiconductor dies 106A. In some embodiments, the insulating material 110 fills the gap between the first semiconductor die 106A and the adjacent through insulator layer hole 108. Due to the presence of the release film RF, portions of the first semiconductor die 106A and portions of the through-insulation layer hole 108 are not covered by the insulating material 110. By injecting the insulating material 110 from one side of the mold MD, the insulating package formed in a subsequent step may have a predetermined height. In other words, the insulating package can be formed without performing other grinding or planarization steps. Thus, molding pits in the insulating package due to the presence of the filler after the grinding or planarization step can be reduced.

In some embodiments, the insulating material 110 comprises a polymer (e.g., a polymer)Epoxy, phenolic, silicon-containing, or other suitable resins), dielectric materials having low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating material 110 may comprise an acceptable insulating encapsulation material. The insulating material 110 may be injected in liquid form or other form that flows at a slower rate than liquid. In some embodiments, the insulating material 110 can also include an inorganic filler or inorganic compound (e.g., silicon dioxide, clay, etc.) that can be added to the insulating material 110 to optimize the Coefficient of Thermal Expansion (CTE) of the insulating material 110. In certain embodiments, the inorganic filler may be SiO ₂、Al ₂O ₃Dielectric particles of silicon dioxide, etc., and may have a spherical shape. In some embodiments, fine fillers or large fillers may be used as filler particles based on requirements.

Referring to fig. 4A, after the insulating material 110 is injected, the insulating material 110 is cured to form an insulating package 110'. Then, the mold MD may be removed and the release film RF stripped to reveal portions of the first semiconductor die 106A and portions of the through-insulation layer holes 108. Fig. 4B is a top view of the structure shown in fig. 4A, with the through insulator layer hole 108 omitted for illustration purposes. As shown in fig. 4B, an insulating package 110' is formed around each of the first semiconductor dies 106A, revealing the top surface of the first semiconductor dies 106A. Furthermore, as shown in fig. 4A and 4B, the first semiconductor die 106A and the through insulator hole 108 protrude from the insulating package 110'. In some embodiments, the first portion P1 of the conductive rod 106a-4 is surrounded by the insulating package 110 ', while the second portion P2 of the conductive rod 106a-4 protrudes from the insulating package 110'. In some embodiments, portions of the protective layers 106a-5 also protrude from the insulating package 110'.

Referring to fig. 5, in a next step, an isolation material 112 is formed on the insulating package 110' to cover the protruding portion (or exposed portion) of the first semiconductor die 106A and the protruding portion (or exposed portion) of the through-insulating layer hole 108. In some embodiments, the isolation material 112 is formed by a suitable fabrication technique, such as Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. Embodiments of the invention are not limited in this respect. At this stage, the first semiconductor die 106A and the through-insulation layer hole 108 are well protected by the isolation material 112 and covered by the isolation material 112. In some embodiments, the isolation material 112 may comprise a dielectric material, such as polyimide, Polybenzoxazole (PBO), benzocyclobutane (BCB), and the like. Embodiments of the invention are not limited in this respect. In some embodiments, the isolation material 112 may be made of a different material than the insulating package 110'. In some other embodiments, the isolation material 112 may comprise a material similar to the materials listed for the insulating package 110', but the isolation material 112 does not contain any filler particles therein. Since the isolation material 112 and the insulating package 110 ' are formed in different steps, there will be an interface between the isolation material 112 and the insulating package 110 ' when the isolation material 112 is formed over the insulating package 110 '.

Referring to fig. 6, after forming the isolation material 112, the isolation material 112 is partially removed to expose the conductive posts 106a-4 and the through insulating layer holes 108. In some embodiments, the isolation material 112 and the protective layers 106a-5 are ground or polished by a planarization step. The planarization step is performed, for example, by a mechanical grinding process and/or a Chemical Mechanical Polishing (CMP) process until the top surfaces 106TSC of the conductive rods 106a-4 are revealed. In some embodiments, the through insulation layer hole 108 may be partially polished such that a top surface 108TS of the through insulation layer hole 108 is flush with a top surface 106TSC of the conductive rod 106 a-4. In other words, the conductive posts 106a-4 and the through insulator holes 108 may also be lightly ground/polished. In some embodiments, the top surface 110TS of the insulating package 110' is below the level of the top surface 106TSC of the plurality of conductive bars 106 a-4.

In the illustrated embodiment, the isolation material 112 is polished to form an isolation layer 112'. In some embodiments, top surface 112TS of isolation layer 112', top surface 108TS of through insulation layer hole 108, top surface 106TSC of conductive post 106a-4, and top surface 106TSP of polished protective layer 106a-5 are coplanar and flush with one another. In some embodiments, a cleaning step may optionally be performed after a mechanical grinding or Chemical Mechanical Polishing (CMP) step. For example, a cleaning step is performed to clean and remove residues resulting from the planarization step. However, embodiments of the invention are not so limited and the planarization step may be performed by any other suitable method.

In addition, as shown in FIG. 6, an isolation layer 112 'is formed on the insulating package 110' and surrounds the second portion P2 of the conductive bar 106a-4 and also surrounds the protective layer 106 a-5. In some embodiments, the isolation layer 112 'and the conductive posts 106a-4 are separated from each other due to the positioning of the protective layer 106a-5 between the isolation layer 112' and the conductive posts 106 a-4. In other words, the isolation layer 112' is not in physical contact with the conductive rod 106 a-4. Further, the ratio of the thickness T1 of the isolation layer 112 'to the thickness T2 of the insulating package 110' is in the range of 1: 6 to 1: 40. By controlling the thickness T1 of the isolation layer 112 'and the thickness T2 of the insulating package 110' in this range, protection of the first semiconductor die 106A can be ensured, while the molding pits (if present) on the insulating package 110 'can be effectively covered or isolated by the isolation layer 112'. If the thickness T1 of the isolation layer 112 'is too small, the molding pits on the insulating package body 110' may not be well covered and isolated, and there may still be a redistribution layer (RDL) collapse problem. In some embodiments, the thickness T1 of isolation layer 112' is in the range from 1 μm to 30 μm. In some embodiments, the thickness T1 of isolation layer 112' is in the range from 5 μm to 20 μm. In one exemplary embodiment, the thickness T1 of isolation layer 112' is about 5 μm.

Referring to fig. 7, after the planarization step is performed, a rewiring layer 114 is formed on the isolation layer 112', on the through-insulation layer hole 108, and on the first semiconductor die 106A. As shown in fig. 7, a rewiring layer 114 is formed on the top surface 108TS of the through-insulation layer hole 108, on the top surface 106TSC of the conductive rod 106a-4 and on the top surface 112TS of the isolation layer 112'. In some embodiments, an isolation layer 112 'separates the redistribution layer 114 from the insulating package 110'. In some embodiments, the redistribution layer 114 is electrically connected to the through-insulator hole 108 and to the first semiconductor die 106A through the conductive bars 106A-4. In some embodiments, the first semiconductor die 106A is electrically connected to the through insulator layer hole 108 through the re-routing layer 114.

In some embodiments, forming the redistribution layer 114 includes sequentially and alternately forming one or more dielectric layers 114A and one or more metal layers 114B. In some embodiments, the metal layer 114B is sandwiched between several dielectric layers 114A. Although only two metal layers 114B and three dielectric layers 114A are illustrated herein, the scope of the present disclosure is not limited by the embodiments of the present invention. In other embodiments, the number of metal layers 114B and dielectric layers 114A may be adjusted based on product requirements. In some embodiments, the metal layer 114B is electrically connected to the conductive bars 106A-4 of the first semiconductor die 106A. Further, the metal layer 114B is electrically connected to the through insulating layer hole 108.

In some embodiments, the material of the dielectric layer 114A may be polyimide, Polybenzoxazole (PBO), benzocyclobutane (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, and the like, and the material of the dielectric layer 114A may be patterned using photolithography and/or etching processes. In some embodiments, the dielectric layer 114A is formed by a suitable fabrication technique including, for example, spin-on coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like. Embodiments of the invention are not limited in this respect.

In some embodiments, the material of the metal layer 114B may be made of a conductive material formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, which may be patterned using photolithography and etching processes. In some embodiments, the metal layer 114B may be a patterned copper layer or other suitable patterned metal layer. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper with inevitable impurities, and copper alloys containing trace amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

After the redistribution layer 114 is formed, a plurality of conductive pads 114C may be disposed on the exposed top surface of the topmost layer of the metal layer 114B to be electrically connected with the conductive balls. In some embodiments, for example, the conductive pad 114C is an under-ball metal (UBM) pattern for mounting a ball. As shown in fig. 7, conductive pad 114C is formed on redistribution layer 114 and electrically connected to redistribution layer 114. In some embodiments, the material of the conductive pad 114C may include copper, nickel, titanium, tungsten, or alloys thereof, and may be formed by a plating process. The number of conductive pads 114C is not limited to the embodiment of the invention, and can be selected based on the design layout. In some alternative embodiments, conductive pad 114C may be omitted. In other words, the conductive balls 116 formed in a subsequent step may be directly disposed on the redistribution layer 114.

Still referring to fig. 7, after forming conductive pad 114C, a plurality of conductive balls 116 are disposed on conductive pad 114C and above redistribution layer 114. In some embodiments, the conductive balls 116 may be disposed on the conductive pads 114C by a ball-attach process or a reflow process. In some embodiments, conductive balls 116 are solder balls or Ball Grid Array (BGA) balls, for example. In some embodiments, conductive balls 116 are connected to redistribution layer 114 through conductive pads 114C. In some embodiments, some of the conductive balls 116 may be electrically connected to the first semiconductor die 106A through the redistribution layer 114. In addition, some of the conductive balls 116 may be electrically connected to the through insulating layer hole 108 through the rewiring layer 114. The number of conductive balls 116 is not limited to the embodiment of the invention, and can be designated and selected based on the number of conductive pads 114C. In some alternative embodiments, an Integrated Passive Device (IPD) (not shown) may optionally be disposed on the rerouting layer 114 and electrically connected to the rerouting layer 114.

Referring to fig. 8, in the next step, after the redistribution layer 114 and the conductive balls 116 are formed, the structure shown in fig. 7 may be turned upside down and attached to a tape 301 supported by a frame 302. Subsequently, the carrier 102 is peeled to separate the dielectric layer 104B and other elements formed on the carrier 102 from the carrier 102. In an exemplary embodiment, the lift-off process includes projecting light (e.g., laser or Ultraviolet (UV) light) onto the debonding layer 104A (e.g., LTHC release layer) such that the carrier 102 may be easily removed. In some embodiments, the debonding layer 104A may also be removed or stripped to reveal the dielectric layer 104B. The remaining dielectric layer 104B may then be patterned to form a plurality of openings (not shown) that expose the bottom surface of the through-insulation layer holes 108. The number of openings formed corresponds to the number of through-insulation layer holes 108. Thereafter, a plurality of conductive balls 118 may be placed on the bottom surfaces of the through-insulation layer holes 108 exposed by the openings. For example, reflow is performed on the conductive balls 118 to bond with the bottom surface of the through-insulator hole 108. After the conductive balls 118 are formed, the package structure PK1 with the double-sided terminals is completed.

Referring to fig. 9, in some embodiments, another package structure PK2 may be stacked on the package structure PK1 to form a package-on-package (PoP) structure. As shown in fig. 9, package structure PK2 is electrically connected to conductive balls 118 of package structure PK 1. In some embodiments, the package structure PK2 has a substrate 210, a plurality of semiconductor chips 220 mounted on one surface (e.g., top surface) of the substrate 210 and stacked on each other. In some embodiments, bond wires 230 are used to provide electrical connection between the semiconductor chip 220 and pads 240 (e.g., bond pads). In some embodiments, an insulating package 260 is formed to encapsulate the semiconductor chip 220 and the bonding wires 230 to protect these components. In some embodiments, through-insulator holes (not shown) may be used to provide electrical connections between the pads 240 and conductive pads 250 (e.g., bond pads) located on another surface (e.g., bottom surface) of the substrate 210. In some embodiments, the conductive pads 250 are electrically connected to the semiconductor chip 220 through the through-insulation layer holes (not shown). In some embodiments, the conductive pads 250 of the package structure PK2 are electrically connected to the conductive balls 118 of the package structure PK 1. In some embodiments, an underfill 270 is also provided to fill in the spaces between the conductive balls 118 to protect the conductive balls 118. After stacking package structure PK2 on package structure PK1 and providing electrical connection therebetween, stacked package structure 10A may be fabricated.

Fig. 10A and 10B are schematic cross-sectional views of stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure. The embodiment shown in fig. 10A and 10B is similar to the embodiment shown in fig. 1 to 9, and thus the same reference numerals are used to refer to the same or similar parts, and a detailed description thereof will be omitted herein. The difference between the embodiment of fig. 10A to 10B and the embodiment of fig. 1 to 9 is the design of the isolation layer 112'. As shown in fig. 10A, an isolation layer 112' is formed to surround the second portion P2 of the conductive rod 106 a-4. Furthermore, in some embodiments, top surface 106TSP of protective layer 106a-5 is lower than top surface 112TS of isolation layer 112'. In other words, no planarization step is performed on isolation layer 112 ', and isolation layer 112' will surround through-insulator hole 108 and be located on top surface 108TS of through-insulator hole 108 and on top surface 106TSP of protective layers 106 a-5. In a subsequent step, the first dielectric layer 114A of the rewiring layer 114 is formed on the isolation layer 112'. The first dielectric layer 114A and the isolation layer 112' are patterned to form an opening that reveals the top surface 108TS of the through-insulator hole 108 and the top surface 106TSC of the conductive post 106 a-4. A metal layer 114B is then formed within the opening to electrically connect to the first semiconductor die 106A and the through insulator hole 108.

Referring to fig. 10B, in some embodiments, the same steps as described in fig. 7 to 9 may then be performed to form the redistribution layer 114, the conductive balls 116, and the conductive balls 118 of the package structure PK 1. Subsequently, the same package structure PK2 may be stacked over package structure PK1, and package structure PK2 is electrically connected to package structure PK 1. After stacking package structure PK2 on package structure PK1 and providing electrical connection therebetween, stacked package structure 10B may be fabricated.

Fig. 11A-11C are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure. The embodiment shown in fig. 11A to 11C is similar to the embodiment shown in fig. 1 to 9, and thus the same reference numerals are used to refer to the same or similar parts, and detailed description thereof will be omitted herein. The difference between the embodiment of fig. 11A to 11C and the embodiment of fig. 1 to 9 is the design of the first semiconductor die 106A.

As shown in fig. 11A, in some embodiments, the protective layer 106A-5 of the first semiconductor die 106A may be omitted. As such, during formation of the insulating package 110 ', the insulating package 110' will be in contact with the conductive bars 106A-4 of the first semiconductor die 106A. In some embodiments, the insulating package 110 'is in contact with the first portion P1 of the conductive rod 106a-4, while the second portion P2 of the conductive rod 106a-4 is exposed from the insulating package 110'. Referring to fig. 11B, in a next step, an isolation material (not shown) may be formed over the insulating package 110 'and a planarization step may be performed to form an isolation layer 112'. In an exemplary embodiment, after the planarization step is performed, the top surface 112TS of the isolation layer 112', the top surface 108TS of the through insulator hole 108, and the top surface 106TSC of the conductive post 106a-4 are coplanar and flush with one another. Further, in some embodiments, the isolation layer 112' surrounds and contacts the plurality of conductive posts 106 a-4. In some embodiments, the isolation layer 112' is in contact with the second portion P2 of the conductive rod 106 a-4. Referring to fig. 11C, after forming the isolation layer 112', the same steps as described in fig. 7 to 9 may then be performed to form the redistribution layer 114, the conductive balls 116, and the conductive balls 118 of the package structure PK 1. Subsequently, the same package structure PK2 may be stacked over package structure PK1, and package structure PK2 is electrically connected to package structure PK 1. After stacking package structure PK2 on package structure PK1 and providing electrical connection therebetween, a stacked package structure 10C may be fabricated.

Fig. 12A and 12B are schematic cross-sectional views of stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure. The embodiment shown in fig. 12A and 12B is similar to the embodiment shown in fig. 11A to 11C, and thus the same reference numerals are used to refer to the same or similar parts, and detailed description thereof will be omitted herein. The difference between the embodiment of fig. 12A to 12B and the embodiment of fig. 11A to 11C is the design of the isolation layer 112'. As shown in fig. 12A, an isolation layer 112' is formed to surround and contact the second portion P2 of the conductive bar 106 a-4. Further, in some embodiments, the top surface 106TSC of the conductive rod 106a-4 is lower than the top surface 112TS of the isolation layer 112'. In other words, no planarization step is performed on the isolation layer 112 ', and the isolation layer 112 ' is conformally located on the top surface 108TS of the through insulating layer hole 108, on the top surface 106TSC of the conductive post 106a-4, and over the insulating package 110 '. In a subsequent step, a first dielectric layer 114A of the rewiring layer 114 is formed over the isolation layer 112'. The first dielectric layer 114A and the isolation layer 112' are patterned to form an opening that reveals the top surface 108TS of the through-insulator hole 108 and the top surface 106TSC of the conductive post 106 a-4. A metal layer 114B is then formed within the opening to electrically connect to the first semiconductor die 106A and the through insulator hole 108.

Referring to fig. 12B, in some embodiments, the same steps described in fig. 7-9 may then be performed to form the redistribution layer 114, the conductive balls 116, and the conductive balls 118 of the package structure PK 1. Subsequently, the same package structure PK2 may be stacked over package structure PK1, and package structure PK2 is electrically connected to package structure PK 1. After stacking package structure PK2 on package structure PK1 and providing electrical connection therebetween, stacked package structure 10D may be fabricated.

Fig. 13A-13C are schematic cross-sectional views of various stages of a method of fabricating a package structure, according to some other example embodiments of the present disclosure. The embodiment shown in fig. 13A to 13C is similar to the embodiment shown in fig. 1 to 9, and thus the same reference numerals are used to refer to the same or similar parts, and detailed description thereof will be omitted herein. The difference between the embodiment of fig. 13A to 13C and the embodiment of fig. 1 to 9 is that a second semiconductor die 106B is also provided in the embodiment of fig. 13A to 13C.

As shown in fig. 13A, a second semiconductor die 106B is stacked on the first semiconductor die 106A to form a stacked die. In some embodiments, the second semiconductor die 106B is connected to the first semiconductor die 106A by a connection element CE. In some embodiments, the connection elements CE may be conductive bumps or conductive pads that provide the necessary connections between the first semiconductor die 106A and the second semiconductor die 106B, and the embodiments of the invention are not limited in this respect. In an exemplary embodiment, the first semiconductor die 106A does not have the protective layer 106A-5, and the second semiconductor die 106B is located on the semiconductor substrate 106A-1 of the first semiconductor die 106A, intermediate the two conductive bars 106A-4. In some embodiments, the second semiconductor die 106B includes a second semiconductor substrate 106B-1 and a plurality of second conductive bars 106B-2 disposed on the second semiconductor substrate 106B-1. In some embodiments, the conductive bars 106A-4 of the first semiconductor die 106A and the second conductive bars 106B-2 of the second semiconductor die 106B have a first portion P1 surrounded by the insulating package 110 'and a second portion P2 protruding from the insulating package 110', respectively. In some embodiments, the width W1 of the second conductor bar 106b-2 is less than the width W2 of the conductor bar 106 a-4. In other words, the conductive rod 106a-4 is different in size from the second conductive rod 106 b-2. In one exemplary embodiment, the width W1 of the second conductive bar 106b-2 is in the range of 1 μm to 10 μm, and the width W2 of the conductive bar 106a-4 is in the range of 10 μm to 90 μm. Embodiments of the invention are not limited in this respect.

Referring to fig. 13B, in a next step, an isolation material (not shown) may be formed over the insulating package 110 'and a planarization step may be performed to form an isolation layer 112'. In an exemplary embodiment, after the planarization step is performed, the top surface 112TS of the isolation layer 112', the top surface 108TS of the through insulator hole 108, the top surface 106TSC of the conductive post 106a-4, and the top surface 106TSCX of the second conductive post 106b-2 are coplanar and flush with one another. In some embodiments, the isolation layer 112 'is formed to surround and contact the conductive bar 106A-4 of the first semiconductor die 106A, and the isolation layer 112' is formed to surround and contact the second conductive bar 106B-2 of the second semiconductor die 106B. Referring to fig. 13C, after forming the isolation layer 112', the same steps as described in fig. 7 to 9 may then be performed to form the redistribution layer 114, the conductive balls 116, and the conductive balls 118 of the package structure PK 1. In some embodiments, an integrated passive device 117 may also be disposed on the redistribution layer 114. Subsequently, the same package structure PK2 may be stacked over package structure PK1, and package structure PK2 is electrically connected to package structure PK 1. After stacking package structure PK2 on package structure PK1 and providing electrical connections therebetween, a stacked package structure 10E may be fabricated.

In the above embodiments, the insulating package is formed to directly encapsulate the semiconductor die without performing other grinding or planarization steps. Further, an isolation layer is formed between the insulating package and the rewiring layer. Thus, molding pits in the insulating package due to the presence of the filler after the grinding or planarization step can be reduced. In addition, the isolation layer will serve as a barrier to isolate the mold pits in the insulating package from the redistribution layer. As such, when a redistribution layer (RDL) is formed over the insulating package, RDL collapse problems or malformed RDL patterns may be prevented. In general, the isolation layer formed on the insulating package provides a flatter surface, so that the redistribution layer can be efficiently fabricated, and the yield of the RDL pattern can be improved.

According to some embodiments of the present disclosure, a package structure is provided that includes at least one semiconductor die, an insulating package, an isolation layer, and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive bar disposed on the semiconductor substrate. The insulating package partially encapsulates the first semiconductor die, wherein the conductive posts have first portions surrounded by the insulating package and second portions protruding from the insulating package. The isolation layer is disposed on the insulating package and surrounds the second portion of the conductive rod. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive bars of the first semiconductor die.

In some embodiments, the isolation layer separates the redistribution layer from the insulating package. In some embodiments, the first semiconductor die further comprises a protective layer disposed on the semiconductor substrate and surrounding the conductive bars, the isolation layer surrounds the protective layer, and a top surface of the protective layer is coplanar with a top surface of the isolation layer. In some embodiments, the first semiconductor die further comprises a protective layer disposed on the semiconductor substrate and surrounding the conductive bars, the isolation layer surrounds the protective layer, and a top surface of the protective layer is lower than a top surface of the isolation layer. In some embodiments, the isolation layer surrounds and contacts the conductive rod. In some embodiments, the package structure further comprises a plurality of through-insulator holes surrounding the first semiconductor die, wherein the plurality of through-insulator holes protrude from the insulating package body, and the isolation layer surrounds the protruding portions of the plurality of through-insulator holes. In some embodiments, the package structure further comprises a second semiconductor die stacked on the first semiconductor die, the second semiconductor die comprising a second semiconductor substrate and a second conductive bar disposed on the second semiconductor substrate, wherein the second conductive bar has a first portion surrounded by the insulating package and a second portion protruding from the insulating package, and the isolation layer surrounds the second portion of the second conductive bar. In some embodiments, a top surface of the conductive bar of the first semiconductor die is substantially coplanar with a top surface of the second conductive bar of the second semiconductor die.

According to some other embodiments of the present disclosure, a package structure is provided that includes a first semiconductor die, an insulating package, an isolation layer, and a redistribution layer. The first semiconductor die has a semiconductor substrate and a plurality of conductive bars disposed on the semiconductor substrate. The insulating package partially encapsulates the first semiconductor die, wherein a top surface of the insulating package is at a level below a top surface of the plurality of conductive bars. The isolation layer is disposed on a top surface of the insulating package and surrounds the plurality of conductive posts, wherein a top surface of the isolation layer is substantially coplanar with the top surfaces of the plurality of conductive posts, and a ratio of a thickness of the isolation layer to a thickness of the insulating package is in a range of 1: 6 to 1: 40. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the plurality of conductive bars of the first semiconductor die.

In some embodiments, the isolation layer separates the redistribution layer from the insulating package. In some embodiments, the first semiconductor die further comprises a protective layer disposed on the semiconductor substrate and surrounding the plurality of conductive bars, the isolation layer surrounds the protective layer, and a top surface of the protective layer is coplanar with the top surface of the isolation layer. In some embodiments, the isolation layer surrounds and contacts each of the plurality of conductive rods. In some embodiments, a portion of the plurality of conductive rods is surrounded by the insulating encapsulation and another portion of the plurality of conductive rods is surrounded by the isolation layer. In some embodiments, the package structure further comprises a second semiconductor die stacked on the first semiconductor die, the second semiconductor die comprising a second semiconductor substrate and a plurality of second conductive bars disposed on the second semiconductor substrate, wherein the insulating package partially encapsulates the second semiconductor die and the top surface of the isolation layer is coplanar with top surfaces of the plurality of second conductive bars.

According to yet another embodiment of the present disclosure, a method of fabricating a package structure is set forth. The method comprises the following steps. Bonding a first semiconductor die on a carrier, wherein the first semiconductor die comprises a semiconductor substrate and a plurality of conductive bars disposed on the semiconductor substrate. Forming an insulating package to partially encapsulate the first semiconductor die, wherein the insulating package is formed to surround a first portion of the plurality of conductive bars and a second portion of the plurality of conductive bars protrudes from the insulating package. Forming an isolation layer on the insulating package to surround the second portions of the plurality of conductive bars. Forming a redistribution layer on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the first semiconductor die.

In some embodiments, the insulating package includes: disposing a mold on the carrier so as to cover the first semiconductor die, wherein the mold includes a runner hole and a release film attached to an inner surface of the mold, and the release film partially covers the first semiconductor die; injecting an insulating material into the mold through the runner hole such that the insulating material partially encapsulates the first semiconductor die; curing the insulating material to form the insulating package; and removing the mold and separating the release film from the first semiconductor die such that the insulating package partially encapsulates the first semiconductor die and exposes portions of the first semiconductor die. In some embodiments, the isolation layer is formed to cover the exposed portion of the first semiconductor die after the mold is removed. In some embodiments, the method of fabricating a package structure further comprises injecting the insulating material into the mold through the runner hole located on one side of the mold such that the insulating material diffuses from one side of the carrier to another side of the carrier to partially encapsulate the first semiconductor die. In some embodiments, the isolation layer is formed to contact the plurality of conductive bars. In some embodiments, the method of fabricating a package structure further comprises stacking a second semiconductor die on the first semiconductor die, the second semiconductor die comprising a second semiconductor substrate and a plurality of second conductive bars disposed on the second semiconductor substrate, wherein the insulating package is formed to surround a first portion of the plurality of second conductive bars, and a second portion of the plurality of second conductive bars protrudes from the insulating package, and the isolation layer is formed to surround the second portion of the plurality of second conductive bars.

The foregoing has outlined features of several embodiments in order that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.