Chip package
阅读说明:本技术 芯片封装件 (Chip package ) 是由 陈冠宇 苏安治 叶德强 黄立贤 叶名世 于 2019-04-12 设计创作,主要内容包括:一种芯片封装件,包括集成电路组件、导热层、绝缘包封体及重布线路结构。所述集成电路组件包括位于所述集成电路组件的后表面处的非晶半导体部分。所述导热层覆盖所述集成电路组件的所述非晶半导体部分,其中所述导热层的导热率大于或大体上等于10W/mK。所述绝缘包封体在横向上对所述集成电路组件及所述导热层进行包封。所述重布线路结构设置在所述绝缘包封体及所述集成电路组件上,其中所述重布线路结构电连接到所述集成电路组件。(A chip package includes an integrated circuit assembly, a heat conductive layer, an insulating package and a redistribution circuit structure. The integrated circuit assembly includes an amorphous semiconductor portion at a back surface of the integrated circuit assembly. The thermally conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity greater than or substantially equal to 10W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermally conductive layer. The redistribution circuitry structure is disposed on the insulating enclosure and the integrated circuit component, wherein the redistribution circuitry structure is electrically connected to the integrated circuit component.)
1. A chip package, comprising:
an integrated circuit assembly comprising an amorphous semiconductor portion at a rear surface of the integrated circuit assembly;
a thermally conductive layer overlying the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity in a range of about 10W/mK to about 250W/mK;
an insulating encapsulant encapsulating the integrated circuit component and the thermally conductive layer; and
a redistribution line structure disposed on the insulating enclosure and the integrated circuit component, wherein the redistribution line structure is electrically connected to the integrated circuit component.
Technical Field
The embodiment of the invention relates to a chip packaging piece.
Background
The semiconductor industry has experienced rapid growth due to the continued increase in integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the ever-decreasing minimum feature size (minimum feature size), which enables more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize smaller areas than previous packages. Some smaller types of packages for semiconductor components include Quad Flat Packages (QFPs), Pin Grid Array (PGA) packages, Ball Grid Array (BGA) packages, and the like.
Currently, integrated fan-out packages are becoming increasingly popular because of their compactness. Heat generated from the integrated circuit assembly of the integrated fan-out package cannot be effectively dispersed due to the low thermal conductivity of the die attach film (e.g., k < 1W/mK).
Disclosure of Invention
According to an embodiment of the present invention, a method of fabricating a chip package, the method comprising: attaching an integrated circuit component to a carrier via a first thermal paste, wherein the first thermal paste has a thermal conductivity in a range from about 10W/mK to about 250W/mK; forming an insulating packaging body to package the integrated circuit assembly attached to the carrier; and forming a redistribution circuit structure on the insulating encapsulation and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.
According to an embodiment of the present invention, a method of fabricating a chip package, the method comprising: providing an integrated circuit assembly, wherein a metal layer is formed on the integrated circuit assembly; attaching the integrated circuit assembly to a carrier through a die attach film such that the metal layer is located between the integrated circuit assembly and the die attach film, wherein the metal layer has a thermal conductivity greater than a thermal conductivity of the die attach film; forming an insulating packaging body to package the integrated circuit assembly attached to the carrier; and forming a redistribution circuit structure on the insulating encapsulation and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.
According to an embodiment of the invention, a chip package includes an integrated circuit assembly, a thermally conductive layer, an insulating encapsulation and a redistribution circuit structure. An integrated circuit assembly includes an amorphous semiconductor portion at a back surface of the integrated circuit assembly. A thermally conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity in a range of about 10W/mK to about 250W/mK. An insulating encapsulant encapsulates the integrated circuit component and the thermally conductive layer. A redistribution circuit structure is disposed on the insulating enclosure and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.
Drawings
Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-15 illustrate a process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure.
Fig. 16-30 illustrate a process flow for fabricating an integrated fan-out package, according to some alternative embodiments of the present disclosure.
Fig. 31 schematically illustrates an integrated fan-out package according to some embodiments of the present disclosure.
Fig. 32 schematically illustrates an integrated fan-out package, according to some alternative embodiments of the present disclosure.
[ description of symbols ]
100: a wafer;
100': thinning the wafer;
110. 110 a: a semiconductor substrate;
110': thinning the semiconductor substrate;
110S: an amorphous semiconductor portion;
120: a conductive pad;
130. 130 a: a passivation layer;
132. 142: a contact opening;
140. 140 a: a post-passivation layer;
150: a conductive post;
160. 160a, 160 a': a protective layer;
200: an integrated circuit component;
210: an insulating material;
210': an insulating enclosure;
b: a conductive feature;
BP: a conductive bump;
c: a carrier;
DAF, DAF 1: a die attach film;
DB: a peeling layer;
DT: cutting the adhesive tape;
m, M1: a metal layer;
p1, P11: a packaging structure;
p2: a semiconductor device;
RDL: re-routing the circuit structure;
ST: sawing the adhesive tape;
TP: heating to obtain paste;
TP 1: a first thermal paste;
TP 2: a second thermal paste;
TV: conducting through holes;
UF: and (4) filling the bottom with glue.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of illustration, spatially relative terms such as "below …", "below …", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
The present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3 DIC) devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of three-dimensional packages or three-dimensional integrated circuits, use of probes and/or probe cards (probecards), and the like. Verification tests may be performed on the intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methods that include intermediate verification of known good dies (known good die) to improve yield and reduce cost.
Fig. 1-15 illustrate a process flow for fabricating an integrated fan-out package according to some embodiments of the present disclosure.
Referring to fig. 1, a
As shown in fig. 1, in some embodiments, the
Referring to fig. 2, a plurality of
Referring to fig. 3, after the
Referring to fig. 3 and 4, after the
Referring to fig. 5, after performing the back side grinding process, the thinned wafer 100 'is mounted on the dicing tape DT so that the rear surface of the thinned semiconductor substrate 110' is adhered to the dicing tape DT. In some embodiments, the dicing tape DT may support the thinned wafer 100 'mounted on the dicing tape DT and temporarily stick with the rear surface of the thinned wafer 100'.
Referring to fig. 5 and 6, after the thinned wafer 100' is mounted on the dicing tape DT, a wafer cutting process is performed on the thinned wafer 100' to singulate the
The
Referring to fig. 6 and 7, a carrier C having a release layer DB formed thereon is provided. In some embodiments, the carrier C is a glass substrate, and the release layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the peeling layer DB such that the peeling layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a Polybenzoxazole (PBO) layer formed on the peeling layer DB.
After providing the carrier C having the peeling layer DB formed thereon, a plurality of conductive through holes TV are formed on the peeling layer DB. In some embodiments, the plurality of conductive vias TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of vias, photoresist stripping, and patterning of a seed layer. For example, the conductive perforated TV includes copper posts (copper posts) or other suitable metal posts.
As shown in fig. 6 and 7, in some embodiments, one of the singulated
The singulated
As shown in fig. 7, for example, the top surface of the
Referring to fig. 8, an insulating
Referring to fig. 8 and 9, the insulating
As shown in fig. 9, the insulating encapsulation 210 'laterally encapsulates the sidewalls of the singulated
Referring to fig. 10, after forming the insulating encapsulation 210 'and the
Referring to fig. 11, after the redistribution routing structure RDL is formed, a plurality of conductive features B are formed, which are electrically connected to the redistribution routing structure RDL. The conductive features B are disposed on the redistribution line structure RDL and arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. As shown in fig. 11, a package structure P1 is fabricated on the peeling layer DB carried by the carrier C, the package structure P1 includes a first thermal paste TP1, a singulated
Referring to fig. 12, the peeling layer DB and the carrier C are peeled off from the package structure P1 such that the bottom surface of the conductive via TV, the bottom surface of the insulating encapsulant 210', and the surface of the first thermal paste TP1 are peeled off from the carrier C and exposed. The bottom surface of insulating encapsulant 210' is at substantially the same level as the exposed surface of first thermal paste TP 1. In some embodiments, external energy (e.g., ultraviolet laser, visible light, or heat) may be applied to release layer DB to make encapsulation structure P1 detachable from release layer DB carried by carrier C.
Referring to fig. 13, after performing the peeling process, the package structure P1 may be flipped (upside down) and mounted on the saw tape ST to stick the conductive features B of the package structure P1 and the saw tape ST together. In some embodiments, the dicing tape ST may support the above-described package structure P1 mounted on the dicing tape ST and temporarily adhere to the conductive features B of the package structure P1. Because the thermal conductivity (k) of the first thermal paste TP1 is high (i.e., greater than or substantially equal to 10W/mK), the first thermal paste TP1 may effectively conduct and dissipate heat generated from the singulated
Referring to fig. 14, a second thermal paste TP2 may be formed to cover the exposed surface of the first thermal paste TP1, wherein the thermal conductivity (k) of the second thermal paste TP2 is greater than or substantially equal to 10W/mK. For example, the thermal conductivity (k) of the second thermal paste TP2 may be in the range of about 10W/mK to about 250W/mK. In some embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be substantially equal to the thermal conductivity (k) of the second thermal paste TP 2. In some alternative embodiments, the thermal conductivity (k) of the first thermal paste TP1 may be greater than or less than the thermal conductivity (k) of the second thermal paste TP 2. Since the thermal conductivity (k) of both the first and second thermal pastes TP1 and TP2 is high (i.e., greater than or substantially equal to 10W/mK), the first and second thermal pastes TP1 and TP2 can effectively conduct and dissipate heat generated from the singulated
As shown in fig. 14, the first thermal paste TP1 is embedded in the insulating encapsulant 210 'and the first thermal paste TP1 contacts the
When at least one of the first thermal paste TP1 and the second thermal paste TP2 contains metal particles (e.g., copper particles), the
In some alternative embodiments, the fabrication of the second thermal paste TP2 may be omitted, as shown in fig. 31.
As shown in fig. 14, the combination of the first thermal paste TP1 and the second thermal paste TP2 can be considered as a thermally conductive layer covering the
Referring to fig. 15, a semiconductor device P2 is provided and a semiconductor device P2 is placed on the package structure P1 to electrically connect the semiconductor device P2 to the conductive via TV. Semiconductor device P2 is electrically connected to
In some embodiments, semiconductor device P2 may be a memory device (e.g., DRAM) that includes conductive bumps BP on its bottom surface. The semiconductor device P2 is, for example, a Ball Grid Array (BGA) type package. In the semiconductor device P2, at least one memory chip may be mounted on a BGA circuit board, electrically connected to the BGA board via bonding wires, and encapsulated by a molding compound. Before mounting the semiconductor device P2 on the package structure P1, a solder material may be applied to the conductive through-holes TV of the package structure P1 by, for example, a screen printing process (stenciling process), and then the semiconductor device P2 including the conductive bumps BP is placed on the conductive through-holes TV. Thereafter, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive through-hole TV of the package structure P1.
After performing the reflow process, an underfill UF is formed between the package structure P1 and the semiconductor device P2 to encapsulate the second thermal paste TP2 and the conductive bump BP. In some embodiments, the material of the underfill UF may include an epoxy containing filler and the thermal conductivity of the underfill UF may be less than about 1W/mK. The underfill UF laterally encapsulates the conductive bump BP and serves as a stress buffer to minimize fatigue (fatigue) of the conductive bump BP due to a Coefficient of Thermal Expansion (CTE) mismatch between the package structure P1 and the semiconductor device P2.
After forming the underfill UF, a sawing process is performed on the package structure P1 to form a plurality of singulated package-on-package (PoP) structures. After performing the sawing process of the package structure P1, the singulated package on package (PoP) structure is attached to a sawing tape ST. In addition, the underfill UF may ensure reliability of a package on package (PoP) structure including the package structure P1 and the semiconductor device P2.
Fig. 16-30 illustrate a process flow for fabricating an integrated fan-out package, according to some alternative embodiments of the present disclosure.
Referring to fig. 16, a
As shown in fig. 16, in some embodiments, the
Referring to fig. 17, a plurality of
Referring to fig. 18, after the
Referring to fig. 18 and 19, after the
After performing the backside grinding process, a metal layer M is formed on the rear surface of the thinned semiconductor substrate 110'. For example, metal is formed on the back surface of the thinned semiconductor substrate 110' by sputtering or other suitable deposition process. The metal layer M covers and contacts the
Referring to fig. 20, after the metal layer M is formed, a dicing tape DT including a die attach film DAF is provided and the thinned wafer 100 'is mounted on the die attach film DAF carried by the dicing tape DT so that the metal layer M formed on the rear surface of the thinned semiconductor substrate 110' is adhered to the die attach film DAF on the dicing tape DT. In some embodiments, the dicing tape DT may support the thinned wafer 100 'mounted on the dicing tape DT and the die attach film DAF may be temporarily stuck with the metal layer M formed on the rear surface of the thinned wafer 100'. In addition, the material of the die attach film DAF may be viscous and the thermal conductivity (k) of the die attach film DAF is less than or substantially equal to 1W/mK. In some embodiments, the die attach film DAF may have a thermal conductivity (k) in a range from about 0.01W/mK to about 1W/mK.
Referring to fig. 20 and 21, after the thinned wafer 100' is mounted on the dicing tape DT, a wafer dicing process is performed on the thinned wafer 100', the metal layer M, and the die attach film DAF to singulate the
The
Referring to fig. 21 and 22, a carrier C having a release layer DB formed thereon is provided. In some embodiments, the carrier C is a glass substrate, and the exfoliation layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate. In some alternative embodiments, a dielectric layer (not shown) may be formed on the peeling layer DB such that the peeling layer DB is located between the carrier C and the dielectric layer. For example, the dielectric layer is a Polybenzoxazole (PBO) layer formed on the peeling layer DB.
After providing the carrier C having the peeling layer DB formed thereon, a plurality of conductive through holes TV are formed on the peeling layer DB. In some embodiments, the plurality of conductive vias TV may be formed by sputtering of a seed layer, photoresist coating, photolithography, electroplating of vias, photoresist stripping, and patterning of a seed layer. For example, the conductive via TV includes copper pillars or other suitable metal pillars.
As shown in fig. 21 and 22, in some embodiments, one of the singulated
The singulated
As shown in fig. 22, for example, the top surface of the
Referring to fig. 23, an insulating
Referring to fig. 23 and 24, the insulating
As shown in fig. 24, the insulating encapsulation 210 'laterally encapsulates the sidewalls of the singulated
Referring to fig. 25, after forming the insulating encapsulation 210 'and the
Referring to fig. 26, after the redistribution routing structure RDL is formed, a plurality of conductive features B are formed, which are electrically connected to the redistribution routing structure RDL. The conductive features B are disposed on the redistribution line structure RDL and arranged in an array. In some embodiments, the conductive features B may be conductive balls (e.g., solder balls) arranged in an array. As shown in fig. 26, a package structure P11 is fabricated on the peeling layer DB carried by the carrier C, the package structure P11 includes a singulated metal layer M1, a singulated die attach film DAF1, a singulated
Referring to fig. 27, the peeling layer DB and the carrier C are peeled off from the package structure P11 such that the bottom surface of the conductive through hole TV, the bottom surface of the insulating encapsulant 210', and the surface of the singulated die attach film DAF1 are peeled off from the carrier C and exposed. The bottom surface of insulating encapsulant 210' is at substantially the same level as the exposed surface of singulated die attach film DAF 1. In some embodiments, external energy (e.g., ultraviolet laser, visible light, or heat) may be applied to release layer DB to separate encapsulation structure P11 from release layer DB carried by carrier C.
Referring to fig. 28, after performing the peeling process, the package structure P11 may be flipped (upside down) and mounted on the saw tape ST to stick the conductive features B of the package structure P11 and the saw tape ST together. In some embodiments, the dicing tape ST may support the above-described package structure P11 mounted on the dicing tape ST and temporarily adhere to the conductive features B of the package structure P11. Because the thermal conductivity (k) of the singulated die attach film DAF1 is low (i.e., less than or substantially equal to 1W/mK), the singulated die attach film DAF1 may not be able to effectively conduct and dissipate heat generated from the singulated
Referring to fig. 29, after removing the singulated die attach film DAF1, a thermal paste TP may be formed by dispensing or other suitable process to cover the exposed surface of the singulated metal layer M1, wherein the thermal paste TP has a thermal conductivity (k) greater than or substantially equal to 10W/mK. For example, the thermal conductivity (k) of the thermal paste TP is in the range of about 10W/mK to about 250W/mK. In some embodiments, the thermal conductivity (k) of the thermal paste TP may be less than the thermal conductivity (k) of the singulated metal layer M1. In some alternative embodiments, the thermal conductivity (k) of the thermal paste TP may be greater than or substantially equal to the thermal conductivity (k) of the singulated metal layer M1. Since the thermal conductivity (k) of both the thermal paste TP and the singulated metal layer M1 is high (i.e., greater than or substantially equal to 10W/mK), the thermal paste TP and the singulated metal layer M1 can effectively conduct and dissipate heat generated from the singulated
As shown in fig. 29, the singulated metal layer M1 is embedded in the insulating encapsulant 210 'and contacts the
When the thermal paste TP contains metal particles (e.g., copper particles), the singulated metal layer M1 may serve as a diffusion barrier for the metal particles. In addition, the
In some alternative embodiments, the fabrication of the thermal paste TP may be omitted, as shown in fig. 32.
As shown in fig. 29, the combination of the singulated metal layer M1 and the thermal paste TP may be considered as a thermally conductive layer covering the
Referring to fig. 30, a semiconductor device P2 is provided and a semiconductor device P2 is placed on the package structure P11 to electrically connect the semiconductor device P2 to the conductive via TV. The semiconductor device P2 is electrically connected to the singulated
In some embodiments, semiconductor device P2 may be a memory device (e.g., DRAM) that includes conductive bumps BP on its bottom surface. Before mounting the memory device on the package structure P11, a solder material may be applied to the conductive through-hole TV of the package structure P11 by, for example, a screen printing process, and then the semiconductor device P2 including the conductive bump BP is placed on the conductive through-hole TV. Thereafter, a reflow process is performed to form a solder joint between the semiconductor device P2 and the conductive through-hole TV of the package structure P11.
After performing the reflow process, an underfill UF is formed between the package structure P11 and the semiconductor device P2 to encapsulate the thermal paste TP and the conductive bumps BP. In some embodiments, the material of the underfill UF may include an epoxy containing filler and the thermal conductivity of the underfill UF may be less than about 1W/mK. The underfill UF laterally encapsulates the conductive bumps BP and acts as a stress buffer to minimize fatigue of the conductive bumps BP due to Coefficient of Thermal Expansion (CTE) mismatch between the package structure P11 and the semiconductor device P2.
After forming the underfill UF, a sawing process is performed on the package structure P11 to form a plurality of singulated package on package (PoP) structures. After performing the sawing process of the package structure P11, the singulated package on package (PoP) structure is attached to a sawing tape ST. In addition, the underfill UF may ensure reliability of a package on package (PoP) structure including the package structure P11 and the semiconductor device P2.
According to some embodiments of the present disclosure, there is provided a method of fabricating a chip package including the following steps. The integrated circuit assembly is attached to the carrier by a first thermal paste, wherein the first thermal paste has a thermal conductivity in a range from about 10W/mK to about 250W/mK. And forming an insulating packaging body to package the integrated circuit assembly attached to the carrier. Forming a redistribution circuit structure on the insulating encapsulation and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises: forming a plurality of conductive vias on the carrier prior to forming the insulating encapsulation such that the plurality of conductive vias are encapsulated by the insulating encapsulation, wherein after forming the redistribution routing structure, the plurality of conductive vias are electrically connected to the integrated circuit component via the redistribution routing structure. In an embodiment, the method further comprises: after the redistribution line structure is formed, peeling the first thermal paste and the insulating encapsulant from the carrier; and electrically connecting a semiconductor device to the plurality of conductive vias such that the first thermal paste is between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the redistribution circuit structure. In an embodiment, the method further comprises: an underfill is formed between the integrated circuit assembly and the semiconductor device to cover the first thermal paste. In an embodiment, the method further comprises: after the redistribution line structure is formed, peeling the first thermal paste and the insulating encapsulation from the carrier to expose a surface of the first thermal paste; forming a second thermal paste on the exposed surface of the first thermal paste, wherein the thermal conductivity of the second thermal paste is greater than or substantially equal to 10W/mK; and electrically connecting a semiconductor device to the plurality of conductive vias such that the first thermal paste and the second thermal paste are between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the redistribution circuit structure. In an embodiment, the method further comprises: an underfill is formed between the integrated circuit assembly and the semiconductor device to encapsulate the second thermal paste. In an embodiment, the integrated circuit component includes an amorphous semiconductor portion at a back surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the first thermal paste.
According to some embodiments of the present disclosure, there is provided a method of fabricating a chip package including the following steps. An integrated circuit assembly is provided having a metal layer formed thereon. And attaching the integrated circuit assembly on a carrier through a die attach film so that the metal layer is positioned between the integrated circuit assembly and the die attach film, wherein the thermal conductivity of the metal layer is greater than that of the die attach film. And forming an insulating packaging body to package the integrated circuit assembly attached to the carrier. Forming a redistribution circuit structure on the insulating encapsulation and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. In an embodiment, the method further comprises: forming a plurality of conductive vias on the carrier prior to forming the insulating encapsulation such that the plurality of conductive vias are encapsulated by the insulating encapsulation, wherein after forming the redistribution routing structure, the plurality of conductive vias are electrically connected to the integrated circuit component via the redistribution routing structure. In an embodiment, the method further comprises: peeling the die attach film and the insulating encapsulant from the carrier after the redistribution line structure is formed; removing the die attach film to expose the metal layer; electrically connecting a semiconductor device to the plurality of conductive vias such that the die attach film is between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the redistribution circuit structure. In an embodiment, the method further comprises: an underfill is formed between the integrated circuit assembly and the semiconductor device to cover the metal layer. In an embodiment, the method further comprises: after the redistribution line structure is formed, peeling the die attach film and the insulating encapsulant from the carrier to expose the die attach film; removing the die attach film to expose the metal layer; forming a thermal paste on the metal layer; and electrically connecting a semiconductor device to the plurality of conductive vias such that the metal layer and the thermal paste are between the integrated circuit assembly and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit assembly via the plurality of conductive vias and the redistribution circuit structure. In an embodiment, the method further comprises: an underfill is formed between the integrated circuit assembly and the semiconductor device to encapsulate the thermal paste. In an embodiment, the integrated circuit component includes an amorphous semiconductor portion at a back surface of the integrated circuit component, and the amorphous semiconductor portion of the integrated circuit component contacts the metal layer. In an embodiment, the metal layer has a thermal conductivity in a range from about 20W/mK to about 406W/mK.
According to some embodiments of the present disclosure, a chip package is provided that includes an integrated circuit assembly, a thermally conductive layer, an insulating encapsulant, and a redistribution circuit structure. The integrated circuit assembly includes an amorphous semiconductor portion at a back surface of the integrated circuit assembly. The thermally conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein the thermally conductive layer has a thermal conductivity in a range of about 10W/mK to about 250W/mK. The insulating encapsulant encapsulates the integrated circuit component and the thermally conductive layer. The redistribution circuitry structure is disposed on the insulating enclosure and the integrated circuit component, wherein the redistribution circuitry structure is electrically connected to the integrated circuit component. In an embodiment, the thermally conductive layer includes a first thermal paste that contacts the amorphous semiconductor portion of the integrated circuit component. In an embodiment, the thermally conductive layer includes a first thermal paste and a second thermal paste. A first thermal paste contacts the amorphous semiconductor portion of the integrated circuit component, the first thermal paste having a thermal conductivity in a range of about 10W/mK to about 250W/mK. A second thermal paste covers the first thermal paste, wherein the thermal conductivity of the second thermal paste is in a range from about 10W/mK to about 250W/mK. In an embodiment, the thermally conductive layer comprises a metal layer contacting the amorphous semiconductor portion of the integrated circuit component, and the metal layer has a thermal conductivity in a range of about 20W/mK to about 406W/mK. In an embodiment, the thermally conductive layer includes a metal layer and a thermal paste. A metal layer contacts the amorphous semiconductor portion of the integrated circuit assembly. A thermal paste covers the metal layer, wherein the thermal paste is partially embedded in the insulating encapsulant.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:半导体装置封装体及其制造方法