阅读说明：本技术 半导体封装件 (Semiconductor package ) 是由 林俊成 卢思维 于 2019-06-28 设计创作，主要内容包括：提供了半导体封装件。半导体封装件中的一个包括半导体管芯、导热图案、密封剂和导热层。导热图案设置在半导体管芯旁边。密封剂密封半导体管芯和导热图案。导热层覆盖半导体管芯的后表面,其中,导热图案通过导热层热耦合至半导体管芯并且与半导体管芯电绝缘。(A semiconductor package is provided. One of the semiconductor packages includes a semiconductor die, a thermally conductive pattern, an encapsulant, and a thermally conductive layer. The thermally conductive pattern is disposed alongside the semiconductor die. An encapsulant encapsulates the semiconductor die and the thermally conductive pattern. A thermally conductive layer overlies the back surface of the semiconductor die, wherein the thermally conductive pattern is thermally coupled to and electrically insulated from the semiconductor die by the thermally conductive layer.)

1. A semiconductor package, comprising:

a semiconductor die;

a thermally conductive pattern located beside the semiconductor die;

an encapsulant encapsulating the semiconductor die and the thermally conductive pattern; and

a thermally conductive layer covering a rear surface of the semiconductor die, wherein the thermally conductive pattern is thermally coupled to and electrically insulated from the semiconductor die by the thermally conductive layer.

2. The semiconductor package of claim 1, further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.

3. The semiconductor package of claim 1, wherein the thermally conductive pattern comprises a plurality of discrete vias.

4. The semiconductor package of claim 3, wherein the plurality of discrete vias are arranged along at least one annular path around the semiconductor die.

5. The semiconductor package of claim 1, wherein the thermally conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.

6. The semiconductor package of claim 1, wherein the thermally conductive pattern comprises a plurality of discrete wall-like structures.

7. The semiconductor package of claim 1, further comprising a redistribution circuitry structure disposed over an active surface of the semiconductor die and the first surface of the encapsulant, wherein the active surface of the semiconductor die is opposite the back surface of the semiconductor die, and the redistribution circuitry structure is electrically connected to the semiconductor die.

8. The semiconductor package of claim 7, wherein the redistribution circuit structure further comprises a dummy pattern disposed on the first surface of the encapsulant, and the thermally conductive pattern is connected to the dummy pattern.

9. A semiconductor package, comprising:

a semiconductor die;

an encapsulant laterally encapsulating the semiconductor die;

a first via embedded in the encapsulant and electrically connected to the semiconductor die;

a second via embedded in the encapsulant and electrically insulated from the semiconductor die; and

a thermally conductive layer overlying the semiconductor die, wherein the second via is thermally coupled to the semiconductor die through the thermally conductive layer.

10. A semiconductor package, comprising:

a semiconductor die;

an encapsulant laterally encapsulating the semiconductor die;

a first via embedded in the encapsulant and electrically connected to the semiconductor die;

a second via embedded in the encapsulant and electrically insulated from the semiconductor die; and

a thermally conductive layer covering the semiconductor die and the encapsulant, wherein the thermally conductive layer includes a first portion covering the semiconductor die and a second portion covering the second via, and the first portion of the thermally conductive layer is thicker than the second portion of the thermally conductive layer.

Technical Field

Embodiments of the present application relate to semiconductor packages.

Background

In the packaging of integrated circuits, semiconductor dies may be packaged by a molding compound and may be bonded to other package components, such as interposers and package substrates. Heat dissipation is a challenge in semiconductor packaging. There is a bottleneck in effectively dissipating heat generated in the internal die of the semiconductor package.

Disclosure of Invention

An embodiment of the present application provides a semiconductor package, including: a semiconductor die; a thermally conductive pattern located beside the semiconductor die; an encapsulant encapsulating the semiconductor die and the thermally conductive pattern; and a thermally conductive layer covering the rear surface of the semiconductor die, wherein the thermally conductive pattern is thermally coupled to and electrically insulated from the semiconductor die by the thermally conductive layer.

Another embodiment of the present application provides a semiconductor package, including: a semiconductor die; an encapsulant laterally encapsulating the semiconductor die; a first via embedded in the encapsulant and electrically connected to the semiconductor die; a second via embedded in the encapsulant and electrically insulated from the semiconductor die; and a thermally conductive layer overlying the semiconductor die, wherein the second via is thermally coupled to the semiconductor die through the thermally conductive layer.

Another embodiment of the present application provides a semiconductor package including: a semiconductor die; an encapsulant laterally encapsulating the semiconductor die; a first via embedded in the encapsulant and electrically connected to the semiconductor die; a second via embedded in the encapsulant and electrically insulated from the semiconductor die; and a thermally conductive layer covering the semiconductor die and the encapsulant, wherein the thermally conductive layer includes a first portion covering the semiconductor die and a second portion covering the second via, and the first portion of the thermally conductive layer is thicker than the second portion of the thermally conductive layer.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is an exemplary flow chart illustrating process steps of a method of forming a semiconductor package according to some embodiments.

Fig. 2A-2I are cross-sectional views of methods of forming semiconductor packages according to some embodiments.

Fig. 3 is a simplified top view of fig. 2I.

Fig. 4 is a simplified top view of a semiconductor package according to some embodiments.

Figure 5 is a simplified top view of a semiconductor package according to some embodiments.

Figure 6 is a simplified top view of a semiconductor package according to some embodiments.

Figure 7 is a simplified top view of a semiconductor package according to some embodiments.

Figure 8 is a simplified top view of a semiconductor package according to some embodiments.

Fig. 9 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments.

Fig. 10 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Moreover, for ease of description, terms such as "first," "second," "third," "fourth," and the like may be used herein to describe similar or different elements or components illustrated in the figures and may be used interchangeably depending on the order of appearance or context of description.

Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. The test structure may include, for example, test pads formed in the redistribution circuit structure or on the substrate to allow testing of the 3D package or 3DIC using a probe and/or probe card or the like. Verification tests may be performed on the intermediate structure as well as the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with testing methods that incorporate intermediate verification of known good dies to improve yield and reduce cost.

Fig. 1 is an exemplary flow chart illustrating process steps of a method of forming a semiconductor package according to some embodiments. Fig. 2A-2I are cross-sectional views of methods of forming semiconductor packages according to some embodiments. Fig. 3 is a simplified top view of fig. 2I. For simplicity and clarity of illustration, only a few elements such as semiconductor die, vias, thermally conductive patterns, and thermally conductive layers are shown in the simplified top view of fig. 3.

Referring to fig. 1 and 2A, in step S10, a carrier 102 having a buffer layer 104 coated thereon is provided. In some embodiments, carrier 102 may be a glass carrier or any suitable carrier for carrying semiconductor wafers or reconstituted wafers for use in a method of manufacturing semiconductor packages. In some embodiments, the buffer layer 104 includes a debonding layer, and the material of the debonding layer may be any material suitable for bonding and debonding the carrier 102 with an overlying layer or wafer disposed thereon. In some embodiments, the buffer layer 104 includes, for example, a light-to-heat conversion ("LTHC") layer, and such layer can be debonded from the support by application of laser radiation. In some embodiments, the buffer layer 104 may also include a dielectric layer between the release layer and the carrier 102, and the dielectric layer is made of a dielectric material including benzocyclobutene ("BCB"), polybenzoxazole ("PBO"), or any other suitable polymer-based dielectric material.

In step S20, vias 106a, 106b and a thermal conductive pattern 108 are formed over the buffer layer 104. In some embodiments, for example, a plurality of vias 106a, 106b are formed on the buffer layer 104 to surround the area for the semiconductor die. In some embodiments, as shown in fig. 3, the vias 106a, 106b may be arranged along at least one annular path around the area of the semiconductor die. In some embodiments, for example, the first set of through-holes 106a is arranged along a first annular path and the second set of through-holes 106b is arranged along a second annular path that surrounds the first annular path. In other words, the via 106a is disposed between the via 106b and the region for the semiconductor die. In some embodiments, the through holes 106a, 106b of the same group may be regularly arranged, i.e. the distance between adjacent through holes 106a, 106b of the same group is constant. In some alternative embodiments, the through holes 106a, 106b of the same group may be arranged irregularly or randomly, i.e. the distance between the through holes 106a, 106b of the same group is not constant. In some alternative embodiments, the through holes may be arranged along one annular path or more than two annular paths. In some alternative embodiments, the distance between adjacent groups of through holes may be constant when the through holes are arranged along more than two circular paths.

In some embodiments, the material of the vias 106a, 106b includes copper (Cu), aluminum (Al), aluminum copper alloy (AlCu), gold, titanium, cobalt, an alloy, or any suitable conductive material. The vias 106a, 106b may be formed by, for example, electrochemical plating (ECP), electroplating, electroless plating, or any other suitable process.

In some embodiments, a thermally conductive pattern 108 is disposed on the buffer layer 104 between the vias 106a, 106b and the area for the semiconductor die. In some embodiments, the thermally conductive pattern 108 includes, for example, a plurality of discrete through holes 108 a. In some embodiments, for example, the vias 108a are arranged along one annular path P1 that surrounds the area for the semiconductor die. In some embodiments, the through holes 108a may be regularly arranged, i.e., the distance between adjacent through holes 108a is constant. In some alternative embodiments, the through holes 108a may be arranged irregularly or randomly, i.e., the distance between the through holes 108a is not constant. In some alternative embodiments, the circular path P1 is, for example, rectangular. However, depending on the shape and/or requirements of the semiconductor die, the annular path P1 may be designed as other suitable annular shapes, such as a circle, square, or polygon.

Herein, vias 106a, 106b indicate functional vias and via 108a indicates a non-functional via. In particular, the vias 106a, 106b in a package structure are electrically connected to a front-side or back-side redistribution circuit structure or electrical component of the same package structure or another package structure. However, the vias 108a may be at a floating potential and electrically isolated from a front-side or back-side redistribution circuit structure or electrical component of the same package structure or another package structure.

In some embodiments, as shown in fig. 3, the via 108a may be partially aligned with the vias 106a, 106b in at least one of a first direction and a second direction, the first direction and the second direction being perpendicular to a stacking direction along which the die and the semiconductor device are stacked. In some embodiments, for example, the first direction and the second direction are horizontal directions such as an x direction and a y direction, and the stacking direction is a vertical direction such as a z direction. In some alternative embodiments, the through-hole 108a may not be aligned with the through- holes 106a, 106b in the first direction and/or the second direction. In some embodiments, the distance between the via 108a and the area for the semiconductor die may be less than the distance between adjacent vias 106a, 108 a. However, in some alternative embodiments, the distance between the via 108a and the area for the semiconductor die may be greater than or substantially equal to the distance between adjacent vias 106a, 108 a. In some embodiments, the distance between adjacent vias 106a, 108a may be greater than the distance between adjacent vias 106a, 106 b. In some embodiments, the distance between adjacent vias 106a, 108a may be two or more times the distance between adjacent vias 106a, 106 b. For example, the distance between adjacent vias 106a, 108a may be three, four, five, or six times the distance between adjacent vias 106a, 106 b. However, in some alternative embodiments, the distance between adjacent vias 106a, 108a may be less than or substantially equal to the distance between adjacent vias 106a, 106 b.

In some embodiments, the top surface of the thermally conductive pattern 108 may be substantially flush and coplanar with the top surface of the vias 106a, 106 b. In some embodiments, for example, the top surface of the via 108a may be substantially flush and coplanar with the top surfaces of the vias 106a, 106 b. However, in some alternative embodiments, the top surface of the thermal conductive pattern 108 may be lower or higher than the top surface of the vias 106a, 106 b.

In some embodiments, the material of the thermal conductive pattern 108 includes copper (Cu), aluminum (Al), aluminum copper alloy (AlCu), gold, titanium, cobalt, an alloy, or any other suitable electrically conductive material. The thermally conductive pattern 108 may be formed by, for example, electrochemical plating (ECP), electroplating, electroless plating, or any other suitable process. In some embodiments, for example, the material of the thermally conductive pattern 108 may be the same as the material of the vias 106a, 106 b. In some alternative embodiments, the material of the thermal conductive pattern 108 may be different from the material of the vias 106a, 106 b. In some embodiments, the thermally conductive pattern 108 and the vias 106a, 106b may be formed simultaneously. For example, the via 108a and the vias 106a, 106b may be formed simultaneously. In some embodiments, for plating uniformity, the size of the via 108a (e.g., width W2) ranges from half to twice the size of one of the vias 106a, 106b (e.g., width W1). In some embodiments, width W2 is less than width W1, for example. In some alternative embodiments, the vias 106a, 106b and the thermal conductive pattern 108 may be formed separately.

Referring to fig. 1 and 2B, in step S30, a semiconductor die 110 is provided and disposed on the exposed buffer layer 104 over the carrier 102. In some embodiments, semiconductor die 110 may be a digital chip, an analog chip, or a mixed signal chip, such as an application specific integrated circuit ("ASIC") chip, a sensor chip, a wireless and radio frequency chip, a memory chip, a logic chip, a voltage regulator chip, or any other suitable chip. In some embodiments, semiconductor die 110 is, for example, a system on a chip (SoC). In some embodiments, semiconductor die 110 includes a substrate 112, an active surface 114a, a back surface 114b opposite active surface 114a, a plurality of bonding pads 116 distributed on active surface 114a, a passivation layer 118 covering active surface 114a, a plurality of metal pillars 120, and a protective layer 122. Substrate 112 may be a semiconductor substrate, such as a silicon substrate, but it may be formed of other semiconductor materials including, but not limited to, silicon germanium, silicon carbon, gallium arsenide, and the like. Semiconductor die 110 may include device layers formed in substrate 112 or on substrate 112. In some embodiments, the device layer may include transistors, resistors, capacitors, inductors, and the like. The pads 116 may be formed on and electrically connected to the device layer, and may be pads of an interconnect structure. Pad 116 is partially exposed by passivation layer 118, and metal pillar 120 is disposed on pad 116 and electrically connected to pad 116. The pads 116 are, for example, aluminum contact pads. For example, the metal pillar 120 is a copper pillar or a copper alloy pillar. Protective layer 122 covers metal pillars 120 and passivation layer 118. In some alternative embodiments, the metal pillars 120 are uncovered (i.e., a bare die that is not molded or packaged) prior to placing the semiconductor die 110 on the carrier 102. In some embodiments, the protective layer 122 is a polymer layer. For example, the protective layer 122 includes a photosensitive material such as PBO, polyimide, BCB, combinations thereof, and the like.

In some embodiments, the top surface of the semiconductor die 110 is not coplanar with the top surfaces of the vias 106a, 106b and the thermally conductive pattern 108. In some embodiments, for example, the top surface of the semiconductor die 110 is lower than the top surfaces of the vias 106a, 106b and the thermally conductive pattern 108. In some alternative embodiments, the top surface of the semiconductor die 110 may be substantially flush with the top surfaces of the vias 106a, 106b and the thermally conductive pattern 108 or higher than the top surfaces of the vias 106a, 106b and the thermally conductive pattern 108. In some embodiments, a die attach film 124 is disposed between the back surface 114b of the semiconductor die 110 and the buffer layer 104 for better attachment, and the back surface 114b of the semiconductor die 110 is bonded to the carrier 102. In some embodiments, the semiconductor die 110 is placed over the carrier 102 in an area beside the thermally conductive pattern 108. In some embodiments, the semiconductor die 110 is disposed within an area surrounded by the thermally conductive pattern 108.

In some embodiments, the thermally conductive pattern 108 surrounds the semiconductor die 110, and the vias 106a, 106b surround the thermally conductive pattern 108. In other words, the thermal conductive pattern 108 is disposed between the semiconductor die 110 and the vias 106a, 106 b. Thus, a first minimum distance D1 between via 108a and semiconductor die 110 is less than a second minimum distance D2 between via 106a and semiconductor die 110. In some embodiments, the vias 106a, 106b and the thermally conductive pattern 108 are distributed, for example, on four sides of the semiconductor die 110, respectively. In some embodiments, vias 106a, 106b and vias 108a are distributed, for example, on four sides of semiconductor die 110, respectively. In some embodiments, for example, the distribution of vias 106a, 106b and 108a at one side of semiconductor die 110 is substantially symmetrical to the distribution of vias 106a, 106b and 108a at the other side of semiconductor die 110. Specifically, the vias 106a, 106b and 108a at one side are symmetrical in configuration and location with respect to the central semiconductor die 110 with the vias 106a, 106b and 108a at the other side. In some embodiments, as shown in fig. 2B, the dashed lines represent cut lines of the entire package in a subsequent dicing process, and the vias 106B are arranged near but not on the cut lines and around the thermal conductive pattern 108 and the semiconductor die 110.

Referring to fig. 1 and 2C, in step S40, an encapsulant 130 is formed over the carrier 102 to encapsulate the semiconductor die 110, the vias 106a, 106b, and the thermally conductive pattern 108. In some embodiments, an encapsulant 130 covers the buffer layer 104 and fills between the semiconductor die 110, the thermal conductive pattern 108, and the vias 106a, 106 b. In some embodiments, encapsulant 130 is disposed between semiconductor die 110, vias 108a, and vias 106a, 106 b. In some embodiments, encapsulant 130 laterally encapsulates semiconductor die 110, i.e., the sidewalls of semiconductor die 110 are encapsulated by encapsulant 130. In some embodiments, the encapsulant 130 is formed by forming a molding material covering the semiconductor die 110, the vias 106a, 106b, and the top surface of the heat conductive pattern 108 by an over-molding process, and then removing a portion of the molding material by a planarization process to expose the semiconductor die 110, the vias 106a, 106b, and the top surface of the heat conductive pattern 108. In some embodiments, the planarization process used to planarize the molding material and the semiconductor die 110, the vias 106a, 106b, and the thermally conductive pattern 108 includes a fly-cutting process, a grinding process, a chemical-mechanical polishing ("CMP") process, or any other suitable process. In some embodiments, portions of the protective layer 122, the vias 106a, 106b, and the thermally conductive pattern 108 of the semiconductor die 110 are also removed by the planarization process. In some embodiments, the first surface 130a of the encapsulant 130 is substantially coplanar and flush with the protective layer 122 of the semiconductor die 110 and the metal pillars 120, vias 106a, 106b, and thermally conductive pattern 108. In some embodiments, the vias 106a, 106b and the thermally conductive pattern 108 penetrate and are embedded in the encapsulant 130, respectively. In some embodiments, encapsulant 130 includes a molding compound, a molding underfill, a resin (such as an epoxy), a photosensitive material (such as PBO, polyimide, BCB), combinations thereof, and the like.

Referring to fig. 1 and 2D, in step S50, in some embodiments, redistribution circuitry structures 140 are formed over encapsulant 130, semiconductor die 110, vias 106a, 106b, and thermally conductive pattern 108. In some embodiments, redistribution circuitry structures 140 are formed over the first surface 130a of the encapsulant 130, the active surface 114a of the semiconductor die 110, and the top surfaces of the vias 106a, 106b and the thermally conductive pattern 108. In some embodiments, the redistribution circuit structure 140 is disposed on the top surface of the metal pillar 120 of the semiconductor die 110. In some embodiments, the redistribution circuit structure 140 is electrically connected to the vias 106a, 106b and the semiconductor die 110 and is electrically insulated from the thermally conductive pattern 108.

In some embodiments, the redistribution circuit structure 140 includes a dielectric layer 142 and a plurality of redistribution patterns 144 located in the dielectric layer 142. In some embodiments, the redistribution pattern 144 is electrically connected to the vias 106a, 106b or electrical components of the same package structure, such as the metal posts 120 of the semiconductor die 110. In some embodiments, the redistribution pattern 144 is electrically insulated from the thermally conductive pattern 108. In some embodiments, the bottom redistribution pattern 144 of the redistribution circuit structure 140 is in contact with, for example, the vias 106a, 106b and the metal posts 120 of the semiconductor die 110. In some embodiments, the thermally conductive pattern 108 is electrically insulated from the redistribution pattern 144 by the dielectric layer 142. In some embodiments, the thermally conductive pattern 108 is in contact with the bottom dielectric layer 142, for example. In some embodiments, the material of the redistribution pattern 144 includes aluminum, titanium, copper, nickel, tungsten, silver, and/or alloys thereof. In some embodiments, the material of the dielectric layer 142 includes polyimide, benzocyclobutene, or polybenzoxazole. In some embodiments, the dielectric layer 142 may be a single layer or a multi-layer structure. In some embodiments, the redistribution circuit structures 140 are front side redistribution circuit structures that are electrically connected to the semiconductor die 110 and are electrically connected to the vias 106a, 106 b. In some embodiments, since the underlying encapsulant 130 provides better planarization and uniformity, the redistribution circuit structures 140 formed thereafter, particularly the redistribution patterns 144 with fine line widths or close spacing, may be formed with uniform line widths or uniform profiles over the planar and horizontal encapsulant 130, thereby improving the reliability of the lines/wires.

In some embodiments, a plurality of conductive elements 146 are disposed on the redistribution circuit structure 140 and electrically connected to the redistribution circuit structure 140. In some embodiments, prior to disposing the conductive elements 146, solder may be applied so that the conductive elements 146 are better secured to the top redistribution pattern 144 of the redistribution circuit structure 140, and the top redistribution pattern 144 may serve as contact pads for the conductive elements 146. In some embodiments, the conductive elements 146 are, for example, solder balls or ball grid array ("BGA") balls placed on the redistribution circuit structure 140, and the top redistribution pattern 144 underlying the conductive elements 146 serves as ball pads. In some embodiments, some of the conductive elements 146 are electrically connected to the semiconductor die 110 through the redistribution circuit structure 140, and some of the conductive elements 146 are electrically connected to the vias 106a, 106 b. In some embodiments, the electrically conductive element 146 is electrically insulated from the thermally conductive pattern 108.

Referring to fig. 1 and 2D and 2E, in step S60, in some embodiments, the entire package is debonded from carrier 102 to separate semiconductor die 110 from carrier 102. In some embodiments, after debonding from carrier 102, buffer layer 104 remaining on the entire package is removed by an etching process or a cleaning process. Optionally, in some optional embodiments, the buffer layer 104 may be retained.

Then, in some embodiments, the entire package is turned upside down and disposed on carrier film 150. When the package structure is turned upside down, the top surface may become the bottom surface and the relative positional relationship (such as above, below, above, or below) may become the opposite of the package structure as described above, but the same surface, common surface, or interface will be labeled with the same reference numeral of the semiconductor package. After debonding from carrier 102, die attach film 124 is exposed. In some embodiments, the top surface of the die attach film 124 is substantially coplanar and flush with the top surfaces of the encapsulant 130, the vias 106a, 106b, and the thermally conductive pattern 108.

Thereafter, the die attach film 124 is removed, and thus a trench 132 is formed in the encapsulant 130 over the semiconductor die 110. In some embodiments, the back surface 114b of the semiconductor die 110 is exposed after the die attach film 124 is removed. In some embodiments, the back surface 114b of the semiconductor die 110 is lower than a second surface 130b opposite the first surface 130a of the encapsulant 130. Furthermore, the back surface 114b of the semiconductor die 110 is lower than the top surfaces of the vias 106a, 106b and the thermal conductive pattern 108.

Referring to fig. 1 and 2E and 2F, in step S70, in some embodiments, a thermally conductive layer 160 is formed over the semiconductor die 110 and the encapsulant 130, wherein the thermally conductive pattern 108 is thermally coupled to the semiconductor die 110 through the thermally conductive layer 160. In some embodiments, the heat dissipation structure includes a thermally conductive pattern 108 and a thermally conductive layer 160. As used herein, thermally coupled means that temperature changes of the heat dissipating structure will cause temperature changes of the semiconductor die and vice versa. In some embodiments, a thermally conductive layer 160 is formed over the back surface 114b of the semiconductor die 110 to fill the trench 132. Thus, the thermally conductive layer 160 and the redistribution circuit structures 140 are disposed on opposite sides of the semiconductor die 110. In some embodiments, the thermally conductive layer 160 extends outwardly from the back surface 114b of the semiconductor die 110 to cover portions of the second surface 130b of the encapsulant 130 and the top surface of the thermally conductive pattern 108. In some embodiments, the thermally conductive layer 160 covers the second surface 130b of the encapsulant 130 beside the top surface of the thermally conductive pattern 108. In some embodiments, the thermally conductive layer 160 is separated from the top surfaces of the vias 106a, 106b to electrically isolate the vias 106a, 106 b. In other words, the edge of the heat conductive layer 160 is separated from the edge of the through-hole 106a, and thus the heat conductive layer 160 is electrically insulated from the through-hole 106 a.

In some embodiments, the thermally conductive layer 160 may be in contact with the back surface 114b of the semiconductor die 110, portions of the second surface 130b of the encapsulant 130, and the top surface of the thermally conductive pattern 108. In some embodiments, the thermally conductive layer 160 completely covers, for example, the top surface of the thermally conductive pattern 108. However, in some alternative embodiments, the thermally conductive layer 160 may partially cover the thermally conductive pattern 108, or may not cover the thermally conductive pattern 108.

In some embodiments, the thermally conductive layer 160 includes a first portion 162 overlying the semiconductor die 110 and a second portion 164 overlying the encapsulant 130 and the thermally conductive pattern 108. In some embodiments, for example, a top surface of first portion 162 is substantially flush with a top surface of second portion 164. However, in some alternative embodiments, the top surfaces of the first and second portions 162, 164 may not be coplanar with one another. In some embodiments, first portion 162 is thicker than second portion 164 because portions of first portion 162 fill in trench 132. In other words, the thickness T1 of the first portion 162 from the back surface 114b of the semiconductor die 110 to its own top surface is greater than the thickness T2 of the second portion 164 from the top surface of the second surface 130b of the encapsulant 130 to its own top surface. In some embodiments, thickness T2 may be, for example, greater than or equal to 5 μm. In some embodiments, the interface between the semiconductor die 110 and the thermally conductive layer 160 is lower than the interface between the encapsulant 130 and the thermally conductive layer 160. The heat conductive layer 160 is an electrically conductive paste such as silver paste, and is formed by a printing process, for example.

Referring to fig. 1 and 2G, in step S80, semiconductor device 170 is stacked over semiconductor die 110 and electrically connected to semiconductor die 110. In some embodiments, semiconductor device 170 is a package such as a Dynamic Random Access Memory (DRAM) package or any other suitable semiconductor device. In some embodiments, the semiconductor device 170 is disposed on the thermally conductive layer 160 above the semiconductor die 110, and the thermally conductive layer 160 is disposed between the semiconductor die 110 and the semiconductor device 170. In some embodiments, semiconductor device 170 includes a plurality of contacts 172. For example, the contact 172 may be a pad or a metal pillar on a pad. The contacts 172 of the semiconductor device 170 are electrically connected to the redistribution structure 140 through the conductive elements 174 and the vias 106a, 106 b. In some embodiments, conductive elements 174 are, for example, solder balls or BGA balls that are placed on semiconductor device 170. In some embodiments, a gap G is formed between semiconductor device 170 and thermally conductive layer 160, i.e., gap G is less than the height of electrically conductive elements 174. Thus, the thermally conductive layer 160 is not in contact with the semiconductor device 170 and is therefore electrically insulated from the semiconductor device 170. In some embodiments, the gap G may be in the range of, for example, 25% to 40% of the height of the conductive element 174. In some embodiments, the vertical distance between semiconductor die 110 and semiconductor device 170 may be in the range from 50 to 60 μm, and gap G may be greater than 10 μm, for example. In some alternative embodiments, at least a portion of the thermally conductive layer 160 is in direct contact with the second die 170. In other words, for example, a portion of the thermally conductive layer 160 may be in contact with the second die 170, a portion of the thermally conductive layer 160 may be separated from the second die 170 by a distance, and a top surface of the thermally conductive layer 160 may not be flat.

Referring to fig. 2H, in some embodiments, an underfill 176 is formed between the conductive elements 174, the semiconductor device 170, and the thermally conductive layer 160. Thus, the gap G is filled with the underfill 176. In some embodiments, the underfill 176 in the gap G between the semiconductor device 170 and the thermally conductive layer 160 ensures electrical insulation between the semiconductor device 170 and the thermally conductive layer 160.

Referring to fig. 1, 2H and 2I, in some embodiments, a dicing process is performed to dice the entire package structure (at least through the encapsulant 130 and the redistribution circuit structure 140) along dicing lines (dashed lines) into individual and separate semiconductor packages 100, as shown in fig. 2I. In one embodiment, the dicing process is a wafer dicing process that includes mechanical blade sawing or laser cutting. In some embodiments, semiconductor package 100 is, for example, an integrated fan out package (InFO PoP) device. In some alternative embodiments, the semiconductor package 100 may be further mounted on an electronic device, which may be, for example, a board such as a Printed Circuit Board (PCB). In some alternative embodiments, the semiconductor package 100 may be mounted with additional packages, chips/dies, or other electronic devices.

In some embodiments, as shown in fig. 2I, the vias 106a, 106b and the thermally conductive pattern 108 are embedded in the encapsulant 130 alongside the semiconductor die 110, and the thermally conductive layer 160 is disposed over the semiconductor die 110 and extends onto the encapsulant 130. The vias 106a, 106b are electrically connected to the semiconductor die 110, and the thermally conductive pattern 108 is electrically insulated from the semiconductor die 110, but is thermally coupled to the semiconductor die 110 by a thermally conductive layer 160. Accordingly, heat generated by any component of the semiconductor package 100 (such as the semiconductor die 110 or the semiconductor device 170) may be dissipated through the thermally conductive layer 160 and the thermally conductive pattern 108, and the heat dissipation area of the semiconductor package 100 is enlarged. Thus, for example, a conventional semiconductor package having a thermally conductive layer (which is not in contact with the semiconductor device) without a thermally conductive pattern, or a conventional semiconductor package having a thermally conductive layer (which is in contact with the semiconductor device) without a thermally conductive pattern, may improve the heat dissipation efficiency of the semiconductor die, as compared to a conventional semiconductor package without a thermally conductive pattern and a thermally conductive layer.

In some embodiments, the thermally conductive pattern 108 is shown as having a plurality of discrete through holes 108a arranged along one annular path P1, however, the invention is not limited thereto. In other words, the heat conductive pattern may be arranged along a plurality of annular paths. In some embodiments, as shown in fig. 4, the thermally conductive pattern 108 may include a plurality of through- holes 108a, 108b arranged along a plurality of annular paths P1, P2. In some embodiments, the first set of discrete vias 108a is arranged along a first annular path P1, the second set of discrete vias 108b is arranged along a second annular path P2 that surrounds the first annular path P1, and the annular paths P1, P2 respectively surround the semiconductor die 110. In some embodiments, the second set of vias 108b is disposed between the first set of vias 108a and the first set of vias 106 a. In some embodiments, the width of via 108a may be the same or different than the width of via 108 b. In some embodiments, for example, one of the vias 108a of the first set is partially aligned with one of the vias 108b of the second set in a direction perpendicular to a stacking direction of the semiconductor die 110 and the semiconductor device 170. In addition, the aligned vias 108a, 108b may be further aligned with the aligned vias 106a and 106 b. However, in some alternative embodiments, the through- holes 106a, 106b may not be aligned with each other or may not be aligned with the through- holes 108a, 108 b. For example, in some embodiments, as shown in fig. 5, one of the first set of vias 108a and one of the second set of vias 108b are immediately adjacent to each other in a direction perpendicular to the stacking direction, and they may be alternately disposed. Further, in some embodiments, the through holes 106a and 106b may be alternately disposed next to each other. In some embodiments, one of the first set of vias 108a may be partially aligned with one of the first set of vias 106a, and similarly one of the second set of vias 108b is partially aligned with one of the second set of vias 106b, in a direction perpendicular to the stacking direction.

The thermally conductive pattern 108 may have other configurations. For example, as shown in fig. 6, the thermally conductive pattern 108 includes an annular structure 108c surrounding the semiconductor die 110. The loop structure 108c is continuously formed along the loop path P. In other words, the ring structure 108c is continuously disposed around the semiconductor die 110. In some embodiments, for example, the width W2 of the ring structure 108c may be substantially the same, and the width W2 may be in a range from half to twice the size of one of the vias 106a, 106b (e.g., width W1). In some alternative embodiments, the thermally conductive pattern 108 may include a plurality of ring-shaped structures respectively disposed along a plurality of ring-shaped paths around the semiconductor die 110.

In some embodiments, as shown in fig. 7 and 8, the thermally conductive pattern 108 may include a plurality of discrete wall-like structures 108 d. The wall-like structures 108d are separated from each other, and the wall-like structures 108d are arranged along one annular path P. In some embodiments, as shown in fig. 7, the wall-like structures 108d are respectively disposed at one side of the semiconductor die 110. In some embodiments, the wall-like structure 108d is, for example, a cuboid. In some embodiments, as shown in fig. 8, at least one wall structure 108d may be disposed at two adjacent sides of the semiconductor die 110. In some alternative embodiments, for example, one wall-like structure 108d may be disposed at three or four adjacent sides of the semiconductor die 110. In some embodiments, for example, the width W2 of the wall-like structures 108d may be substantially the same, and the width W2 may be in a range from half to twice the size of one of the vias 106a, 106b (e.g., width W1). In some alternative embodiments, the width W2 of the wall-like structure 108d may be different. In some alternative embodiments, the wall-like structures 108d may be arranged along a plurality of annular paths that each surround the semiconductor die 110. Furthermore, it should be noted that in fig. 3 to 8, the distance between the semiconductor die 110 and the heat conductive pattern 108 or between the heat conductive pattern 108 and the via 106a is exemplarily shown, and actually, in some embodiments, the distance may be larger than, for example, the distance between the adjacent two vias 106a, 106 b. However, in some alternative embodiments, the distance may be equal to or less than the distance between two adjacent through holes 106a and 106 b. In addition, the material of the thermal conductive pattern 108 in fig. 3 to 8 may be an electrically conductive material, such as those described for the via hole 108 a.

In the above embodiments, the heat conductive pattern is shown to be arranged along one circular path or two circular paths, however, the present invention is not limited thereto. In other words, the heat conductive pattern may be arranged along more than two annular paths. Further, the annular paths may have the same or different shapes, and the intervals between the components of the heat conductive pattern along the adjacent two annular paths may be the same or different.

Fig. 9 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments. The difference between the semiconductor package of fig. 9 and the semiconductor package of fig. 2I is that: the redistribution circuit structure also includes dummy patterns. Differences are detailed below, and similarities are not repeated here. In some embodiments, as shown in fig. 9, the redistribution circuit structure 140 also includes dummy patterns 148 that are electrically isolated from the redistribution patterns 144 in the package structure or from electrical components of the same package structure or another package structure. In some embodiments, dummy patterns 148 are disposed at the bottom of the redistribution circuit structure 140. In some embodiments, the dummy patterns 148 are disposed on the first surface 130a of the encapsulant 130 and in the dielectric layer 142 of the redistribution circuitry 140. In some embodiments, the heat conductive pattern 108 is connected to the dummy pattern 148, which means that the heat conductive pattern 108 is electrically connected to the dummy pattern 148. In some embodiments, for example, the thermally conductive pattern 108 may be in contact with the dummy pattern 148. In some embodiments, the heat conductive pattern 108 is thermally coupled to the heat conductive layer 160 on a first side and to the dummy pattern 148 on a second side opposite the first side. Accordingly, heat generated by the semiconductor package may be dissipated through the heat conductive layer 160, the heat conductive pattern 108, and the dummy pattern 148, and the heat dissipation area of the semiconductor die 110 is enlarged. Therefore, heat dissipation efficiency can be improved.

Fig. 10 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments. The difference between the semiconductor package of fig. 10 and the semiconductor package of fig. 2I is that: the semiconductor package also includes a die attach film. Differences are detailed below, and similarities are not repeated here. In some embodiments, as shown in fig. 10, for example, if the die attach film 124 has good thermal conductivity, the die attach film 124 may not be removed prior to forming the thermally conductive layer 160, and thus the die attach film 124 may be disposed between the semiconductor die 110 and the thermally conductive layer 160. In some embodiments, the thermally conductive layer 160 may have substantially a constant thickness T, i.e., the first portion 162 over the semiconductor die 110 and the second portion 164 over the encapsulant 130 and the thermally conductive pattern 108 may have substantially the same thickness T. For example, the thickness T may be greater than or equal to 5 μm.

In some embodiments, a semiconductor package has a heat dissipation structure thermally coupled to a semiconductor die. In some embodiments, the heat dissipation structure includes a thermally conductive pattern beside the semiconductor die and a thermally conductive layer disposed on the semiconductor die and extending onto the thermally conductive pattern. Thus, the thermally conductive pattern may be thermally coupled to the semiconductor die by the thermally conductive layer. By arranging the heat dissipation structure, the heat dissipation area of the semiconductor packaging piece can be greatly expanded, and the heat dissipation efficiency of the semiconductor packaging piece can be obviously improved. Further, while the thermally conductive layer is disposed between the semiconductor die and the semiconductor device, the height of the thermally conductive layer is controlled to prevent contact with the semiconductor device above it. Therefore, cold-bonding risks such as a PoW (package on chip) cold-bonding risk and other process problems can be prevented. In addition, the extension of the thermally conductive layer over the encapsulant and the thermally conductive pattern increases the contact area between the semiconductor die and the thermally conductive layer, thereby enhancing the adhesion of the thermally conductive layer to the semiconductor die. Therefore, heat dissipation of the semiconductor package is stabilized and improved.

According to some embodiments, a semiconductor package includes a semiconductor die, a thermally conductive pattern, an encapsulant, and a thermally conductive layer. The thermally conductive pattern is disposed alongside the semiconductor die. An encapsulant encapsulates the semiconductor die and the thermally conductive pattern. A thermally conductive layer overlies the back surface of the semiconductor die, wherein the thermally conductive pattern is thermally coupled to and electrically insulated from the semiconductor die by the thermally conductive layer. According to some embodiments, the semiconductor package further comprises a semiconductor device stacked over and electrically connected to the semiconductor die. According to some embodiments, the thermally conductive pattern comprises a plurality of discrete through holes. According to some embodiments, the plurality of discrete vias are arranged along at least one annular path around the semiconductor die. According to some embodiments, the thermally conductive pattern comprises a ring-shaped structure surrounding the semiconductor die. According to some embodiments, the thermally conductive pattern comprises a plurality of discrete wall-like structures. According to some embodiments, the semiconductor package further comprises a redistribution circuitry structure disposed over the active surface of the semiconductor die and the first surface of the encapsulant, wherein the active surface of the semiconductor die is opposite the back surface of the semiconductor die, and the redistribution circuitry structure is electrically connected to the semiconductor die. According to some embodiments, the redistribution circuitry structure further comprises a dummy pattern disposed on the first surface of the encapsulant, and the thermally conductive pattern is connected to the dummy pattern. According to some embodiments, the thermally conductive layer extends outwardly from the back surface of the semiconductor die to partially cover the second surface of the encapsulant, and the second surface of the encapsulant is opposite the first surface of the encapsulant.

According to some embodiments, a semiconductor package includes a semiconductor die, an encapsulant, a first via, a second via, and a thermally conductive layer. The encapsulant laterally encapsulates the semiconductor die. The first via is embedded in the encapsulant and electrically connected to the semiconductor die. The second via is embedded in the encapsulant and electrically insulated from the semiconductor die. A thermally conductive layer overlies the semiconductor die, wherein the second via is thermally coupled to the semiconductor die through the thermally conductive layer. According to some embodiments, the semiconductor package further comprises a semiconductor device stacked over and electrically connected to the semiconductor die, wherein the thermally conductive layer and the semiconductor device are separated by a distance. According to some embodiments, the thermally conductive layer is disposed over the semiconductor die and extends onto the second via. According to some embodiments, the thermally conductive layer is in contact with the semiconductor die and the second via. According to some embodiments, the thermally conductive layer includes a first portion overlying the semiconductor die and a second portion overlying the encapsulant, and the first portion is thicker than the second portion. According to some embodiments, a first minimum distance between the first via and the semiconductor die is less than a second minimum distance between the second via and the semiconductor die.

According to some embodiments, a semiconductor package includes a semiconductor die, an encapsulant, a first via, a second via, and a thermally conductive layer. The encapsulant laterally encapsulates the semiconductor die. The first via is embedded in the encapsulant and electrically connected to the semiconductor die. The second via is embedded in the encapsulant and electrically insulated from the semiconductor die. A thermally conductive layer covers the semiconductor die and the encapsulant, wherein the thermally conductive layer includes a first portion covering the semiconductor die and a second portion covering the second via, wherein the first portion of the thermally conductive layer is thicker than the second portion of the thermally conductive layer. According to some embodiments, the thermally conductive layer partially covers the encapsulant. According to some embodiments, a first minimum distance between the first via and the semiconductor die is greater than a second minimum distance between the second via and the semiconductor die. According to some embodiments, the second width of the second via is in a range from half to twice the first width of the first via. According to some embodiments, the thermally conductive layer is in contact with the second via.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.