Amplifier chip packaging structure and manufacturing method
阅读说明:本技术 放大器芯片封装结构及制作方法 (Amplifier chip packaging structure and manufacturing method ) 是由 曲韩宾 张晓朋 吴兰 高博 邢浦旭 崔培水 谷江 于 2019-11-12 设计创作,主要内容包括:本发明提供了一种放大器芯片封装结构及制作方法,涉及芯片封装技术领域,包括芯片、封装基板以及封盖;封装基板设有至少两层介质层,且位于顶层的介质层上设有凹槽,封装基板上设有顶部金属层、中间金属层和底部金属层,封盖设置于封装基板上。本发明提供的放大器芯片封装结构,实现了多层布线,将芯片设置于凹槽内,有效的缩短了芯片与封装基板的顶部金属层之间的连接长度,提高了二者之间的传输能力,降低了射频传输的损耗,带有内腔的封盖使芯片的上方有一层低介电损耗的空气层,避免了传统封装芯片需要直接接触塑封料造成的介电损耗,有效的降低了封装结构造成的毫米波波段的性能损耗。(The invention provides an amplifier chip packaging structure and a manufacturing method thereof, relating to the technical field of chip packaging, wherein the amplifier chip packaging structure comprises a chip, a packaging substrate and a sealing cover; the packaging substrate is provided with at least two layers of dielectric layers, a groove is formed in the top layer of the dielectric layer, a top metal layer, a middle metal layer and a bottom metal layer are arranged on the packaging substrate, and the sealing cover is arranged on the packaging substrate. The amplifier chip packaging structure provided by the invention realizes multilayer wiring, the chip is arranged in the groove, the connection length between the chip and the top metal layer of the packaging substrate is effectively shortened, the transmission capability between the chip and the top metal layer is improved, the loss of radio frequency transmission is reduced, the sealing cover with the inner cavity enables an air layer with low dielectric loss to be arranged above the chip, the dielectric loss caused by the fact that the traditional packaging chip needs to be in direct contact with a plastic packaging material is avoided, and the performance loss of a millimeter wave band caused by the packaging structure is effectively reduced.)
1. An amplifier chip package, comprising:
the chip comprises a chip, wherein a plurality of metal pressure points are arranged on the outer periphery of the upper surface of the chip, and at least two metal pressure points are chip radio frequency ports;
the packaging substrate is provided with at least two layers of medium layers which are stacked from bottom to top, a groove which is provided with an upward opening and is used for accommodating the chip is arranged on the medium layer positioned on the top layer, a conducting layer is arranged on the bottom surface of the groove, a plurality of top metal layers which are positioned on the periphery of the chip and are respectively in one-to-one correspondence with the metal pressure points are arranged on the top surface of the medium layer, middle metal layers which are in one-to-one correspondence with the top metal layers are arranged between every two adjacent layers of medium layers, and bottom metal layers which are in one-to-one correspondence with the middle metal layers and in one-to-one correspondence; and
and the sealing cover is arranged on the packaging substrate and is used for sealing the packaging substrate, and the sealing cover is provided with an inner cavity with a downward opening.
2. The amplifier chip package of claim 1, wherein the top metal layers corresponding to the chip rf ports are first rf ports, respectively, the chip rf ports are connected to the first rf ports in a one-to-one correspondence, and the bottom metal layers corresponding to the first rf ports are provided with second rf ports, respectively.
3. The amplifier chip package of claim 2, wherein the package substrate has a plurality of copper bars disposed under the conductive layer, the copper bars extending to the bottom metal layer under the grooves, and the tops of the copper bars are connected to the conductive layer.
4. The amplifier chip package of claim 3, wherein the recess extends through a face of the dielectric layer at the top layer, and the conductive layer is flush with the intermediate metal layer.
5. The amplifier chip package of claim 2, wherein the chip rf port is connected to the first rf port by a bond wire; and a plating layer used for bonding with the bonding wire is arranged on the first radio frequency port.
6. The amplifier chip package of claim 5, wherein there are two bonding wires, and the bonding wires are connected to the chip and the first RF port by a wedge bond or a ball bond, respectively.
7. The amplifier chip package according to any one of claims 2 to 6, wherein an adhesive layer is disposed at an edge of a bottom surface of the cover for adhering to an outer periphery of the package substrate, and the chip and the groove are adhered by a conductive adhesive.
8. The amplifier chip package of any one of claims 2-6, wherein a top surface of the chip is flush with a top surface of the package substrate, and wherein a spacing value between two side surfaces of the chip adjacent to the first RF port and a side surface of the recess is 50-200 μm.
9. The amplifier chip package of any one of claims 2-6, wherein the first radio frequency port and the second radio frequency port are connected by a metalized via.
10. A method of making an amplifier chip package according to any of claims 2-9, comprising the steps of:
manufacturing a packaging substrate, stacking the top metal layer, the dielectric layer, the middle metal layer, the dielectric layer and the bottom metal layer, forming a groove on the dielectric layer at the top, and forming a conductive layer in the groove;
bonding the chip to the packaging substrate, placing the packaging substrate on a bonding table, bonding the chip to the groove, and drying the chip and the packaging substrate until bonding glue is cured;
bonding two radio frequency ports to two first radio frequency ports respectively, placing the chip and the packaging substrate on a bonding table, heating the chip and the packaging substrate, and connecting the radio frequency ports of the chip to the corresponding first radio frequency ports respectively;
mounting the cover, and heating the packaging substrate to 125 ℃; and fixing the sealing cover on the packaging substrate, heating and keeping the sealing cover, and then naturally cooling.
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to an amplifier chip packaging structure and a method for manufacturing the same.
Background
With the utilization and development of spectrum resources in the radio frequency band, the operating frequencies of various communication systems have been expanded from lower frequency bands to the millimeter wave band. The millimeter wave frequency band has the advantages of short wavelength, wide frequency band, large information capacity and the like, and the millimeter wave communication technology is widely applied to the fields of mobile communication, radar detection, electronic countermeasure, accurate guidance and the like. The millimeter wave amplifier can amplify microwave signals in a millimeter wave frequency band, and is a key device of a 5G communication receiving and transmitting system. The amplifier chip in the millimeter wave frequency band is generally designed by adopting a monolithic microwave integrated circuit, and has the advantages of good microwave performance and high integration level.
At present, the microwave radio frequency chip mostly adopts a plastic package packaging process. However, the conventional plastic package chip adopts a solid injection molding packaging process, which comprises the steps of firstly manufacturing a metal packaging carrier frame, then bonding a chip on the frame, bonding the chip to a packaging pin, completing chip injection molding through an injection molding machine, and finally forming a final packaging product through a cutting process. The packaging structure is only suitable for packaging chips with frequency bands lower than 10GHz, and for 5G millimeter wave frequency band amplifiers with frequency bands higher than 20GHz, the problems of overlarge parasitic loss and poor use performance exist, and normal use of the chips cannot be guaranteed.
The packaging process for the millimeter wave chip also adopts a ceramic tube shell packaging process for partial productsWith inorganic AL2O3The chip packaging process is that a chip is loaded into the tube shell and then sealed by gold-tin solder or high temperature resistant glue. Its advantages are less loss, high heat dissipation, high resistance to high temp and air tightness, high cost and large size. The method is mainly applied to military industry and is difficult to be used commercially.
Disclosure of Invention
The invention aims to provide an amplifier chip packaging structure and a method for manufacturing the same, and aims to solve the technical problems that a plastic packaging structure in the prior art easily causes overlarge loss and poor use performance of a millimeter wave amplifier.
In order to achieve the purpose, the invention adopts the technical scheme that: an amplifier chip packaging structure is provided, which comprises a chip, a packaging substrate and a sealing cover; the outer periphery of the upper surface of the chip is provided with a plurality of metal pressure points, wherein at least two metal pressure points are chip radio frequency ports; the packaging substrate is provided with at least two layers of medium layers which are stacked from bottom to top, the medium layer positioned on the top layer is provided with a groove with an upward opening and used for accommodating a chip, the bottom surface of the groove is provided with a conducting layer, the top surface of the medium layer is provided with a plurality of top metal layers which are positioned on the periphery of the chip and respectively correspond to a plurality of metal pressure points one by one, a middle metal layer which corresponds to the top metal layers one by one is arranged between every two adjacent layers of medium layers, the bottom surface of the medium layer positioned on the bottom layer is provided with a bottom metal layer which corresponds to the middle metal layers one by one and corresponds to the conducting layer one by one, a sealing cover.
As another embodiment of the present application, the top metal layers corresponding to the chip rf ports are respectively first rf ports, the chip rf ports are connected to the first rf ports in a one-to-one correspondence manner, and the bottom metal layers corresponding to the first rf ports are respectively provided with second rf ports.
As another embodiment of the present application, the package substrate is provided with a plurality of copper bars located below the conductive layer, the copper bars extend to the bottom metal layer located below the groove, and the top of the copper bars is communicated with the conductive layer.
As another embodiment of the present application, the groove penetrates through the top dielectric layer, and the conductive layer is flush with the middle metal layer.
As another embodiment of the present application, the chip rf port is connected to the first rf port through a bonding wire; and a plating layer used for bonding with the bonding wire is arranged on the first radio frequency port.
As another embodiment of the present application, two bonding wires are provided, and the bonding wires are connected to the chip and the first rf port by wedge bonding or ball bonding, respectively.
As another embodiment of the application, the edge of the bottom surface of the sealing cover is provided with an adhesive layer used for being bonded with the periphery of the packaging substrate, and the chip and the groove are bonded by adopting conductive adhesive.
As another embodiment of the present application, the top surface of the chip is flush with the top surface of the package substrate, and a distance between two side surfaces of the chip adjacent to the first RF port and the side surface of the groove has a value of 50-200 μm.
As another embodiment of the present application, a second rf port is disposed on the bottom metal layer corresponding to the first rf port up and down, and the second rf port is connected to the first rf port through a metalized through hole.
A method of making an amplifier chip package structure, comprising the steps of:
manufacturing a packaging substrate, laminating a top metal layer, a dielectric layer, a middle metal layer, a dielectric layer and a bottom metal layer, forming a groove on the dielectric layer positioned at the top, and forming a conductive layer in the groove;
bonding the chip to the packaging substrate, placing the packaging substrate on a bonding table, bonding the chip to the groove, and drying the chip and the packaging substrate until the bonding glue is cured;
bonding the chip radio frequency ports to the corresponding first radio frequency ports respectively, placing the chip and the packaging substrate on a bonding table, heating the chip and the packaging substrate, and connecting the chip radio frequency ports to the corresponding first radio frequency ports respectively;
mounting a sealing cover, and heating the packaging substrate to 125 ℃; and fixing the sealing cover on the packaging substrate, heating and keeping the sealing cover, and then naturally cooling.
The amplifier chip packaging structure provided by the invention has the beneficial effects that: compared with the prior art, the amplifier chip packaging structure provided by the invention adopts a form that the top metal layer, the bottom metal layer, the middle metal layer and the plurality of medium layers are combined, multilayer wiring can be realized, the chip is arranged in the groove, the connection length between the chip and the top metal layer of the packaging substrate is effectively shortened, the parasitic inductance of the bonding wire is reduced, the transmission capability of radio frequency signals between the chip and the packaging substrate is improved, the radio frequency performance of the chip is ensured to the maximum extent, the sealing cover with the inner cavity enables an air layer with low dielectric loss to be arranged above the chip, and the dielectric loss factor of air is far smaller than that of common plastic packaging materials, so that the dielectric loss caused by the fact that the traditional packaging chip needs to be directly contacted with the plastic packaging materials is avoided, and the performance loss of millimeter wave bands caused by the packaging.
According to the method for manufacturing the amplifier chip packaging structure, the molding mode that the top metal layer, the bottom metal layer, the middle metal layer and the plurality of medium layers are combined is adopted, the packaging structure manufactured by the mode can effectively improve the manufacturing efficiency, and the packaging cost of the chip can be effectively reduced. In addition, the sealing cover with the inner cavity is structurally sealed by bonding with the packaging substrate, and compared with the traditional injection molding type plastic package, the sealing cover is simple and convenient to bond and effectively reduces the loss of a high-frequency wave band. The packaging substrate is provided with the groove for mounting the chip, so that the length of the bonding wire is convenient to shorten, the distance between the chip and the bottom surface of the packaging substrate is effectively shortened, the heat dissipation path of the chip is shortened, the heat dissipation efficiency is increased, and the stable work of the chip is facilitated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic front cross-sectional view illustrating an amplifier chip package structure according to a first embodiment of the present invention;
FIG. 2 is a schematic top view of the package substrate of FIG. 1;
FIG. 3 is a schematic cross-sectional view of A-A in FIG. 2;
fig. 4 is a schematic cross-sectional front view illustrating a second amplifier chip package structure according to an embodiment of the present invention;
fig. 5 is a schematic sectional structure view of B-B in fig. 4.
Wherein, in the figures, the respective reference numerals:
100. a chip; 110. pressing points of metal; 111. a chip radio frequency port; 112. a chip DC port; 120. bonding wires; 200. a package substrate; 210. a dielectric layer; 220. a bottom metal layer; 221. a second radio frequency port; 222. a second DC port; 230. an intermediate metal layer; 240. a top metal layer; 241. a first radio frequency port; 242. a first DC port; 250. a groove; 251. a conductive layer; 260. a copper bar; 270. metallizing the through-hole; 300. sealing the cover; 310. an inner cavity.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 5, the amplifier chip package and the method for fabricating the same according to the present invention will be described. The amplifier chip packaging structure comprises a
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or be indirectly on the other element. It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," "outer," and the like are used in the orientations and positional relationships indicated in the drawings and are used merely for convenience in describing and simplifying the present invention, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and thus are not to be considered limiting of the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
Compared with the prior art, the amplifier chip packaging structure provided by the invention adopts a form of combining the
In this embodiment, the
According to the processing requirements and practical application, the thicknesses of the
The
By adopting the packaging structure, two layers of
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to fig. 5, the
Further, the
As an embodiment of the invention, referring to fig. 4 to 5, a plurality of
Further, the width of the
Referring to fig. 1 and 4, as a specific implementation manner of the embodiment of the present invention, the
As a specific implementation manner of the embodiment of the present invention, referring to fig. 2 to fig. 3, the
In this embodiment, the
Further, the
Coplanar waveguide, also called coplanar microstrip transmission line, is to make a central conductor on one surface of a dielectric substrate and to make reference ground conductors on two sides adjacent to the central conductor. In the coplanar waveguide transmission, because the central conductor and the reference ground conductor are positioned in the same plane, the change of an electromagnetic wave transmission mode can be effectively reduced and the radio frequency transmission loss of the chip
As a specific implementation manner of the embodiment of the present invention, an adhesive layer for adhering to the periphery of the
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to 5, a top surface of the
Further, the distance between the two adjacent side surfaces of the
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to fig. 5, the
In this embodiment, a form of providing a
Further, the
The invention also provides a method for manufacturing the amplifier chip packaging structure, which comprises the following steps:
1. manufacturing a package substrate 200: two
2. Bonding the
3. Bonding the chip
4. Mounting the cover 300: heating the
And finally, carrying out appearance and X-ray inspection on the packaged product, judging whether the packaged product is scratched or has the phenomena of
Further, after the
According to the method for manufacturing the amplifier chip packaging structure, the molding mode of combining the
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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