阅读说明：本技术 叠层芯片封装结构 (Laminated chip packaging structure ) 是由 芮平平 阮怀其 于 2019-08-02 设计创作，主要内容包括：本发明公开了一种叠层芯片封装结构,包括PCB基板、BGA球、外壳、上盖、叠层芯片组件,外壳内部安装有叠层芯片组件,叠层芯片组件上方设置上盖,上盖与外壳焊接固定,外壳下方设置PCB基板,外壳与PCB基板通过焊接固定。本发明通过在第一叠层芯片顶端设置焊盘,顶端的焊盘通过硅穿孔的形式与芯片底端电信号连接,同时通过在焊盘上安装毛纽扣与第二叠层芯片电信号连接,实现两组芯片的互联,并且通过毛纽扣在长度方向受压时收缩,压力消除后还原的特性,防止封装结构内部受热膨胀导致芯片焊盘导线受损失效,并且在第一叠层芯片上部开设填料通道,保证下填料充分填注到空腔内,通过上盖与第二叠层芯片之间安装缓冲柱,缓解外界应力对封装结构产生冲击。(The invention discloses a laminated chip packaging structure which comprises a PCB substrate, BGA balls, a shell, an upper cover and a laminated chip assembly, wherein the laminated chip assembly is installed in the shell, the upper cover is arranged above the laminated chip assembly and is fixedly welded with the shell, the PCB substrate is arranged below the shell, and the shell and the PCB substrate are fixedly welded. According to the invention, the bonding pad is arranged at the top end of the first laminated chip, the bonding pad at the top end is in electrical signal connection with the bottom end of the chip in a silicon perforation mode, meanwhile, the bonding pad is provided with the hair button which is in electrical signal connection with the second laminated chip, the interconnection of two groups of chips is realized, and the internal thermal expansion of the packaging structure is prevented from causing damage and failure of a chip bonding pad wire due to the shrinkage of the hair button in the length direction and the reduction after pressure is eliminated by virtue of the characteristic that the hair button is shrunk in the length direction, and the upper part of the first laminated chip is provided with the filler channel to ensure that the lower filler is fully filled into the cavity, and the buffer column is arranged between the upper cover and.)

1. A laminated chip packaging structure is characterized in that: including PCB base plate, BGA ball, shell, upper cover, stromatolite chip subassembly, shell internally mounted have the stromatolite chip subassembly, stromatolite chip subassembly top sets up the upper cover, the upper cover with shell welded fastening, the shell below sets up the PCB base plate, the shell with the PCB base plate passes through welded fastening, the shell with still set up between the PCB base plate the BGA ball.

2. The stacked chip package structure of claim 1, wherein: laminated chip subassembly includes first stromatolite chip, second stromatolite chip, first stromatolite chip bottom installation the BGA ball, first stromatolite chip top integrated into one piece has the pad seat, pad seat internally mounted has the pad, the pad with BGA ball electrical signal connection, first stromatolite chip upper end is still installed second stromatolite chip, the second is folded the chip and is passed through the pad with first stromatolite chip electrical signal connection.

3. The stacked chip package structure of claim 2, wherein: the pad pass through the through-silicon-via with BGA ball electricity signal connection, the pad upper end through the hair button with second stromatolite chip welded fastening.

4. The stacked chip package structure of claim 2, wherein: the upper end of the first laminated chip is also provided with a filler channel, one end of the filler channel is provided with a filling port, and a lower filler layer is filled between the first laminated chip and the second laminated chip.

5. The stacked chip package structure of claim 2, wherein: and a buffer column is arranged between the top end of the second laminated chip and the upper cover.

6. The stacked chip package structure of claim 2, wherein: the buffer column comprises a connecting column, an installation barrel and a limiting plate, wherein the installation barrel is fixedly installed at the upper end of the installation barrel and the bottom end of the upper cover, the limiting plate is installed in the installation barrel in a sliding mode, a spring is installed between the limiting plate and the installation barrel, one end, far away from the spring, of the limiting plate is installed on the connecting column, and the connecting column is fixedly installed at the top end of the second laminated chip.

7. The stacked chip package structure of claim 1, wherein: and a sealing ring is also arranged between the shell and the upper cover.

8. The stacked chip package structure of claim 1, wherein: and heat-conducting insulating silica gel is arranged between the laminated chip component and the shell and between the laminated chip component and the upper cover.

Technical Field

The invention relates to the technical field of chip packaging, in particular to a laminated chip packaging structure.

Background

The chip package is a shell for mounting semiconductor integrated circuit chip, and has the functions of placing, fixing, sealing, protecting chip and enhancing electrothermal property, and is also a bridge for communicating the internal world of chip with external circuit, and the contact points on the chip are connected with pins of package shell by means of conducting wires, and these pins are connected with other devices by means of conducting wires on printed circuit board, so that the package has important action for CPU and other LSI integrated circuits, and because the development direction of integrated circuit is miniaturized and miniaturized, the package of chip is regulated to adapt to the development of integrated circuit, and the surface area of circuit board occupied by chip is reduced, so that the circuit board has more space for arranging electronic components, and at the same time, the chips are fixed by means of lower filling material, and the lower filling material of fluid matter is solidified to produce supporting action for chip, the underfill fills the voids in the shortest time to fix the chip, the substrate and the solder balls, thereby greatly reducing thermal stress caused by mismatch of thermal expansion coefficients of the chip and the substrate, and thus, sufficient underfill filling plays an important role in packaging the chip.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a stacked chip package structure, which achieves interconnection between chips, ensures sufficient filling of underfill, prevents thermal damage of a chip pad wire, and alleviates damage of external pressure to the package structure.

The laminated chip packaging structure comprises a PCB substrate, BGA balls, a shell, an upper cover and a laminated chip assembly, wherein the laminated chip assembly is installed inside the shell, the upper cover is arranged above the laminated chip assembly, the upper cover and the shell are fixedly welded, the PCB substrate is arranged below the shell, the shell and the PCB substrate are fixedly welded, and the BGA balls are also arranged between the shell and the PCB substrate.

Preferably, the stromatolite chip subassembly includes first stromatolite chip, second stromatolite chip, first stromatolite chip bottom is installed the BGA ball, first stromatolite chip top integrated into one piece has the pad seat, pad seat internally mounted has the pad, the pad with BGA ball electrical signal connects, first stromatolite chip upper end is still installed the second stromatolite chip, the second is folded the chip and is passed through the pad with first stromatolite chip electrical signal connects.

Preferably, the bonding pad pass through the silicon perforation with BGA ball electrical signal connection, the bonding pad upper end through the hair button with second stromatolite chip welded fastening.

Preferably, the upper end of the first stacked chip is further provided with a filler channel, one end of the filler channel is provided with a filling port, and a lower filler layer is filled between the first stacked chip and the second stacked chip.

Preferably, a buffer column is installed between the top end of the second laminated chip and the upper cover.

Preferably, the cushion column includes spliced pole, an installation section of thick bamboo, limiting plate, an installation section of thick bamboo upper end with upper cover bottom end fixed mounting, the inside slidable mounting of an installation section of thick bamboo the limiting plate, the limiting plate with install the spring between the installation section of thick bamboo, the one end installation of spring is kept away from to the limiting plate the spliced pole, the spliced pole with second stromatolite chip top fixed mounting.

Preferably, a sealing ring is further installed between the outer shell and the upper cover.

Preferably, heat conduction insulating silica gel is arranged between the laminated chip assembly and the shell and between the laminated chip assembly and the upper cover.

According to the invention, the bonding pad is arranged at the top end of the first laminated chip, the bonding pad at the top end is in electrical signal connection with the bottom end of the chip in a silicon perforation mode, meanwhile, the bonding pad is provided with the hair button which is in electrical signal connection with the second laminated chip, the interconnection of two groups of chips is realized, and the hair button shrinks when being pressed in the length direction, and the characteristic of reduction after pressure is eliminated is utilized, so that the damage and failure of a chip bonding pad wire caused by the internal thermal expansion of the packaging structure are prevented, the upper part of the first laminated chip is provided with the filler channel, the lower filler is ensured to be fully filled into the cavity, and the buffer column is arranged between the upper cover and the second laminated chip, so that.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic structural diagram of a stacked chip package structure according to the present invention;

fig. 2 is an assembly view of a stacked chip package structure according to the present invention;

FIG. 3 is an assembly view of a laminated chip assembly according to the present invention;

FIG. 4 is a schematic structural diagram of a stacked chip assembly according to the present invention;

fig. 5 is a schematic structural diagram of a buffer column according to the present invention.

In the figure: the packaging structure comprises a PCB (1-printed circuit board) substrate, 2-BGA balls, 3-first laminated chips, 4-shells, 5-bonding pads, 6-second laminated chips, 7-upper covers, 8-buffer columns, 9-fuzzy buttons, 10-lower packing layers, 11-packing channels, 12-through silicon holes, 13-laminated chip components, 14-filling ports, 15-bonding pad seats, 16-connecting columns, 17-mounting cylinders, 18-springs, 19-limiting plates and 20-heat-conducting insulating silica gel.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Referring to fig. 1-5, a laminated chip packaging structure comprises a PCB substrate 1, BGA balls 2, a housing 4, an upper cover 7 and a laminated chip assembly 13, wherein the laminated chip assembly 13 is installed inside the housing 4, the upper cover 7 is arranged above the laminated chip assembly 13, the upper cover 7 is welded and fixed with the housing 4, the PCB substrate 1 is arranged below the housing 4, the housing 4 is fixed with the PCB substrate 1 by welding, and the BGA balls 2 are also arranged between the housing 4 and the PCB substrate 1; the laminated chip assembly comprises a first laminated chip 3 and a second laminated chip 6, wherein the bottom end of the first laminated chip 3 is provided with a BGA ball 2, the top end of the first laminated chip 3 is integrally formed with a pad seat 15, a pad 5 is arranged in the pad seat 15, the pad 5 is electrically connected with the BGA ball 2, the upper end of the first laminated chip 6 is also provided with the second laminated chip 6, and the second laminated chip 6 is electrically connected with the first laminated chip 3 through the pad 5; the bonding pad 5 is in electrical signal connection with the BGA ball 2 through a through silicon via 12, and the upper end of the bonding pad 5 is welded and fixed with the second laminated chip 6 through a fuzz button 9; the upper end of the first stacked chip 3 is also provided with a filler channel 11, one end of the filler channel 11 is provided with a filling port 14, and a lower filler layer 10 is filled between the first stacked chip 3 and the second stacked chip 6; a buffer column 8 is arranged between the top end of the second laminated chip 6 and the upper cover 7; the buffer column 8 comprises a connecting column 16, an installation barrel 17 and a limiting plate 19, the installation barrel 17 is fixedly installed at the upper end of the installation barrel 17 and the bottom end of the upper cover 7, the limiting plate 19 is installed in the installation barrel 17 in a sliding mode, a spring 18 is installed between the limiting plate 19 and the installation barrel 17, the connecting column 16 is installed at one end, far away from the spring 18, of the limiting plate 19, and the connecting column 16 and the top end of the second laminated chip 6 are fixedly installed; a sealing ring is also arranged between the shell 4 and the upper cover 7; and heat-conducting insulating silica gel 20 is arranged between the laminated chip assembly 13 and the shell 4 and between the laminated chip assembly 13 and the upper cover 7.

The underfill in the present invention is a mixture of inorganic fillers (such as silica and alumina) and organic materials mainly composed of epoxy resin. The inorganic filler accounts for about 65-80% by weight, and mainly has the functions of adjusting the thermal expansion coefficient and viscosity (reducing glue overflow) of the lower filler and increasing the mechanical strength. The organic component of the lower filler is mainly epoxy resin and accounts for about 10 to 15 weight percent. In the underfill, the epoxy resin mainly functions as a binder, and also has waterproof and insulating functions. In addition to inorganic fillers and organic epoxy resins, there are also a few functional agents which have a very small content but which have a significant effect on the properties of the underfill, including mainly hardeners (providing a bridging function), accelerators (accelerating the rate of sensitization), release agents (assisting release), stress moderators (reducing cracking), flame retardants, and colorants.

To sum up, this stromatolite chip package structure is through setting up the pad on first stromatolite chip top, the pad on top passes through silicon perforation's form and chip bottom electric signal connection, simultaneously through installation hair button and second stromatolite chip electric signal connection on the pad, realize the interconnection of two sets of chips, and shrink when length direction pressurized through the hair button, the characteristic of reduction after the pressure elimination, prevent that the inside thermal expansion that is heated of package structure from leading to the impaired inefficacy of chip pad wire, and set up the filler passageway on first stromatolite chip upper portion, guarantee that the lower filler fully fills in the cavity, through installation bumping post between upper cover and the second stromatolite chip, it produces the impact to package structure to alleviate external stress.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.