阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 熊谷建吾 田沼大吾 水野仁博 于 2019-02-26 设计创作，主要内容包括：本发明的实施方式提供一种能够抑制电容器的位置偏移的半导体存储装置。实施方式的半导体存储装置具备衬底、半导体存储器零件及电容器。所述衬底具有第1焊垫与第2焊垫。所述第1焊垫具有第1区域与第2区域。在将从所述第1焊垫朝向所述第2焊垫的方向设为第1方向,将与所述第1方向交叉的方向设为第2方向的情况下,所述第2区域的所述第2方向的尺寸与所述第1电极的所述第2方向的尺寸的差小于所述第1区域的所述第2方向的尺寸与所述第1电极的所述第2方向的尺寸的差。所述第1电极遍及所述第1区域的至少一部分与所述第2区域的至少一部分地配置。(Embodiments of the invention provide a semiconductor storage device capable of suppressing a positional shift of a capacitor. A semiconductor memory device according to an embodiment includes a substrate, a semiconductor memory component, and a capacitor. The substrate is provided with a No. 1 bonding pad and a No. 2 bonding pad. The 1 st pad has a 1 st region and a 2 nd region. When a direction from the 1 st pad toward the 2 nd pad is a 1 st direction and a direction intersecting the 1 st direction is a 2 nd direction, a difference between a dimension of the 2 nd direction of the 2 nd region and a dimension of the 2 nd direction of the 1 st electrode is smaller than a difference between a dimension of the 2 nd direction of the 1 st region and a dimension of the 2 nd direction of the 1 st electrode. The 1 st electrode is disposed over at least a portion of the 1 st region and at least a portion of the 2 nd region.)

1. A semiconductor memory device is characterized by comprising:

a substrate having a 1 st pad and a 2 nd pad;

a semiconductor memory part mounted on the substrate; and

a 1 st capacitor having a 1 st electrode fixed to the 1 st pad by solder and a 2 nd electrode fixed to the 2 nd pad by solder;

the 1 st welding pad is provided with a 1 st area and a 2 nd area which is positioned on the 2 nd welding pad side relative to the 1 st area;

when the direction from the 1 st pad to the 2 nd pad is the 1 st direction and the direction intersecting the 1 st direction is the 2 nd direction,

a difference between the 2 nd direction size of the 2 nd region and the 2 nd direction size of the 1 st electrode is smaller than a difference between the 2 nd direction size of the 1 st region and the 2 nd direction size of the 1 st electrode; and is

The 1 st electrode is disposed over at least a portion of the 1 st region and at least a portion of the 2 nd region.

2. The semiconductor memory device according to claim 1, wherein:

the dimension of the 1 st direction of the 1 st region is smaller than the dimension of the 1 st direction of the 1 st electrode.

3. The semiconductor memory device according to claim 1, wherein:

the 1 st electrode includes a 1 st portion overlapping with the 1 st region in a thickness direction of the substrate and a 2 nd portion overlapping with the 2 nd region in the thickness direction of the substrate, and

the dimension of the 1 st direction of the 2 nd part is larger than the dimension of the 1 st direction of the 1 st part.

4. The semiconductor memory device according to claim 1, wherein:

the 2 nd pad has a 3 rd region and a 4 th region located on the 1 st pad side with respect to the 3 rd region,

a difference between the 2 nd direction size of the 4 th region and the 2 nd direction size of the 2 nd electrode is smaller than a difference between the 2 nd direction size of the 3 rd region and the 2 nd direction size of the 2 nd electrode, and

the 2 nd electrode is disposed over at least a portion of the 3 rd region and at least a portion of the 4 th region.

5. The semiconductor memory device according to claim 4, wherein:

the 2 nd electrode includes a 3 rd portion overlapping with the 3 rd region in a thickness direction of the substrate and a 4 th portion overlapping with the 4 th region in the thickness direction of the substrate, and

the dimension of the 1 st direction of the 4 th part is larger than the dimension of the 1 st direction of the 3 rd part.

6. The semiconductor memory device according to claim 1, wherein:

the substrate can be provided with a 2 nd capacitor mounted instead of the 1 st capacitor,

the 2 nd capacitor has a 3 rd electrode fixed to the 1 st pad by solder and a 4 th electrode fixed to the 2 nd pad by solder,

a difference between the 2 nd direction size of the 1 st region and the 2 nd direction size of the 3 rd electrode is smaller than a difference between the 2 nd direction size of the 2 nd region and the 2 nd direction size of the 3 rd electrode, and

in a case where the 2 nd capacitor is mounted to the substrate instead of the 1 st capacitor, the 3 rd electrode is disposed over at least a part of the 1 st region and at least a part of the 2 nd region.

7. The semiconductor memory device according to claim 1, wherein:

an edge on the 2 nd direction side of the 1 st region and an edge on the 2 nd direction side of the 2 nd region are linearly continuous.

8. A semiconductor memory device is characterized by comprising:

a substrate having a 1 st pad and a 2 nd pad;

a semiconductor memory part mounted on the substrate; and

a capacitor having a 1 st electrode fixed to the 1 st pad by solder and a 2 nd electrode fixed to the 2 nd pad by solder;

the 1 st welding pad is provided with a 1 st area and a 2 nd area which is positioned on the 2 nd welding pad side relative to the 1 st area;

when the direction from the 1 st pad to the 2 nd pad is the 1 st direction and the direction intersecting the 1 st direction is the 2 nd direction,

a difference between the 2 nd direction dimension of the 1 st region and the 2 nd direction dimension of the 1 st electrode is smaller than a difference between the 2 nd direction dimension of the 2 nd region and the 2 nd direction dimension of the 1 st electrode; and is

The 1 st electrode is disposed over at least a portion of the 1 st region and at least a portion of the 2 nd region.

9. The semiconductor memory device according to claim 8, wherein:

the 1 st pad has a 1 st pad edge located on the 2 nd pad side in the 1 st direction,

the 1 st electrode has a 1 st electrode edge located on the 2 nd electrode side in the 1 st direction, and

the 1 st pad edge is located near the 1 st electrode edge.

10. The semiconductor memory device according to claim 8, wherein:

the 1 st pad has a 1 st pad edge located on the 2 nd pad side in the 1 st direction and a 2 nd pad edge located on an opposite side of the 1 st pad edge in the 1 st direction,

the 1 st electrode has a 1 st electrode edge located on the 2 nd electrode side in the 1 st direction and a 2 nd electrode edge located on the opposite side of the 1 st electrode edge in the 1 st direction, and

the distance of the 1 st direction between the 1 st pad edge and the 1 st electrode edge is smaller than the distance of the 1 st direction between the 2 nd pad edge and the 2 nd electrode edge.

11. The semiconductor memory device according to claim 8, wherein:

the surface of the substrate has an insulating portion at a position different from the 1 st pad and the 2 nd pad, and the 1 st electrode has a portion overlapping with the 1 st pad in a thickness direction of the substrate and a portion overlapping with the insulating portion in the thickness direction of the substrate.

12. The semiconductor memory device according to claim 8, wherein:

the 2 nd pad has a 3 rd region and a 4 th region located on the 1 st pad side with respect to the 3 rd region,

a difference between the 2 nd direction size of the 3 rd region and the 2 nd direction size of the 2 nd electrode is smaller than a difference between the 2 nd direction size of the 4 th region and the 2 nd direction size of the 2 nd electrode, and

the 2 nd electrode is disposed over at least a portion of the 3 rd region and at least a portion of the 4 th region.

13. The semiconductor memory device according to claim 8, wherein:

an edge on the 2 nd direction side of the 1 st region and an edge on the 2 nd direction side of the 2 nd region are linearly continuous.

14. A semiconductor memory device is characterized by comprising:

a substrate having a 1 st pad and a 2 nd pad;

a semiconductor memory part mounted on the substrate; and

a capacitor having a 1 st electrode fixed to the 1 st pad by solder and a 2 nd electrode fixed to the 2 nd pad by solder;

the 1 st pad has a 1 st region and a 2 nd region located on an opposite side of the 2 nd pad with respect to the 1 st region;

when the direction from the 1 st pad to the 2 nd pad is the 1 st direction and the direction intersecting the 1 st direction is the 2 nd direction,

the difference between the 2 nd direction dimension of the 2 nd region and the 2 nd direction dimension of the 1 st electrode is smaller than the difference between the 2 nd direction dimension of the 1 st region and the 2 nd direction dimension of the 1 st electrode.

15. The semiconductor memory device according to claim 14, wherein:

the dimension of the 1 st direction of the 2 nd region is smaller than the dimension of the 1 st direction of the 1 st electrode.

16. The semiconductor memory device according to claim 14, wherein:

the 1 st electrode is disposed over at least a portion of the 1 st region and at least a portion of the 2 nd region.

17. A semiconductor memory device is characterized by comprising:

a substrate having a 1 st pad and a 2 nd pad;

a semiconductor memory part mounted on the substrate; and

a capacitor having a 1 st electrode fixed to the 1 st pad by solder and a 2 nd electrode fixed to the 2 nd pad by solder;

the 1 st pad has a 1 st region and a 2 nd region located on an opposite side of the 2 nd pad with respect to the 1 st region; and is

When the direction from the 1 st pad to the 2 nd pad is the 1 st direction and the direction intersecting the 1 st direction is the 2 nd direction,

the difference between the 2 nd direction dimension of the 1 st region and the 2 nd direction dimension of the 1 st electrode is smaller than the difference between the 2 nd direction dimension of the 2 nd region and the 2 nd direction dimension of the 1 st electrode.

18. The semiconductor memory device according to claim 17, wherein:

the width of the 1 st region in the 1 st direction is smaller than the width of the 1 st electrode in the 1 st direction.

19. The semiconductor memory device according to claim 17, wherein:

the 1 st electrode is disposed over at least a portion of the 1 st region and at least a portion of the 2 nd region.

Technical Field

Embodiments of the present invention relate to a semiconductor memory device.

Background

A semiconductor memory device including a substrate, a semiconductor memory component, and a capacitor is known.

Disclosure of Invention

Drawings

Fig. 1 is a plan view showing a semiconductor memory device according to embodiment 1.

Fig. 2 is a bottom view showing the back surface of the 1 st capacitor of embodiment 1.

Fig. 3 is a bottom view showing the back surface of the 2 nd capacitor of embodiment 1.

Fig. 4 is a plan view showing a pad provided on a substrate according to embodiment 1.

Fig. 5 is a cross-sectional view showing a relationship between the pad and the 1 st capacitor in embodiment 1.

Fig. 6 is a sectional view taken along line F6-F6 of the semiconductor memory device shown in fig. 5.

Fig. 7 is a cross-sectional view showing a relationship between the pad and the 2 nd capacitor in embodiment 1.

Fig. 8 is a cross-sectional view showing a relationship between the pad and the 1 st capacitor in embodiment 2.

Fig. 9 is a cross-sectional view showing a relationship between the pad and the 2 nd capacitor in embodiment 2.

Fig. 10 is a cross-sectional view showing a relationship between the pad and the 1 st capacitor in embodiment 3.

Fig. 11 is a cross-sectional view showing a relationship between the pad and the 2 nd capacitor in embodiment 3.

Fig. 12 is a cross-sectional view showing a relationship between a pad and a 1 st capacitor in a modification of embodiment 3.

Embodiments provide a semiconductor memory device capable of suppressing a positional shift of a capacitor.