阅读说明：本技术 电容器组结构、半导体封装结构及其制造方法
(Capacitor bank structure, semiconductor packaging structure and manufacturing method thereof
) 是由 孔政渊
陈建桦
李德章
林弘毅
李宝男
王信翔
许民赐
陈柏豪 于 2019-06-21 设计创作，主要内容包括：一种电容器组结构包含多个电容器、保护材料、第一电介质层和多个第一支柱。所述电容器并排地安置。所述电容器中的每一个具有第一表面和与所述第一表面相对的第二表面,且包含多个第一电极和多个第二电极。所述第一电极安置为邻近于所述第一表面以用于外部连接,且所述第二电极安置为邻近于所述第二表面以用于外部连接。所述保护材料覆盖所述电容器、所述第一电极的侧壁和所述第二电极的侧壁,且具有对应于所述电容器的所述第一表面的第一表面和对应于所述电容器的所述第二表面的第二表面。所述第一电介质层安置于所述保护材料的所述第一表面上,且界定多个开口以暴露所述第一电极。所述第一支柱安置于所述第一电介质层的所述开口中且从所述第一电介质层突出。(A capacitor bank structure includes a plurality of capacitors, a protective material, a first dielectric layer, and a plurality of first pillars. The capacitors are arranged side by side. Each of the capacitors has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrode is disposed adjacent to the first surface for external connection, and the second electrode is disposed adjacent to the second surface for external connection. The protective material covers the capacitor, sidewalls of the first electrode, and sidewalls of the second electrode, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protective material and defines a plurality of openings to expose the first electrode. The first pillar is disposed in the opening of the first dielectric layer and protrudes from the first dielectric layer.)
1. A capacitor bank structure, comprising:
a plurality of capacitors disposed side-by-side, wherein each of the capacitors has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof for external connection and a plurality of second electrodes disposed adjacent to the second surface thereof for external connection;
a protective material covering the capacitors, sidewalls of the first electrodes, and sidewalls of the second electrodes, and having a first surface corresponding to the first surface of each of the capacitors and a second surface corresponding to the second surface of each of the capacitors;
a first dielectric layer disposed on the first surface of the protective material and defining a plurality of openings to expose the first electrode; and
a plurality of first pillars disposed in the openings of the first dielectric layer and protruding from the first dielectric layer.
2. The capacitor bank structure of claim 1, further comprising:
a plurality of conductive pads electrically connected to the second electrode, and the protective material covers sidewalls of the conductive pads;
a second dielectric layer disposed on the second surface of the protective material and covering the sidewalls of the conductive liner;
a third dielectric layer disposed on the second dielectric layer and defining a plurality of openings to expose the conductive pads; and
a plurality of second pillars disposed in the openings of the third dielectric layer and protruding from the third dielectric layer.
3. The capacitor bank structure of claim 1, wherein the protective material comprises an underfill or a molding compound.
4. The capacitor bank structure of claim 1, further comprising a plurality of conductive pads electrically connected to the second electrode, wherein the protective material includes a first protective material and a second protective material, the first protective material covering the capacitor, the sidewalls of the second electrode, and sidewalls of the conductive pads, and the second protective material covering the first protective material and the sidewalls of the first electrode.
5. The capacitor bank structure of claim 4, wherein a material of the first protective material is different from a material of the second protective material.
6. The capacitor bank structure of claim 1, further comprising a plurality of conductive posts disposed around the capacitor and extending through the protective material.
7. A semiconductor package structure, comprising:
a conductive structure having a top surface and a bottom surface opposite the top surface;
a semiconductor device electrically connected to the top surface of the conductive structure;
at least one capacitor disposed between the semiconductor device and the top surface of the conductive structure, wherein the capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof and electrically connected to the conductive structure and a plurality of second electrodes disposed adjacent to the second surface thereof and electrically connected to the semiconductor device;
an encapsulant covering the semiconductor device and the conductive structure; and
a plurality of outer pillars disposed around the semiconductor device and extending through the encapsulation.
8. The semiconductor package structure of claim 7, further comprising a capacitor bank structure disposed between the semiconductor device and the top surface of the conductive structure and electrically connected to the semiconductor device and the top surface of the conductive structure, wherein the encapsulation further covers the capacitor bank structure, the at least one capacitor includes a plurality of capacitors, and the capacitor bank structure comprises:
the capacitors disposed side-by-side;
a protective material covering the capacitors, sidewalls of the first electrodes, and sidewalls of the second electrodes, and having a first surface corresponding to the first surface of each of the capacitors and a second surface corresponding to the second surface of each of the capacitors;
a first dielectric layer disposed on the first surface of the protective material and defining a plurality of openings to expose the first electrode; and
a plurality of first pillars disposed in the openings of the first dielectric layer and protruding from the first dielectric layer.
9. The semiconductor package structure of claim 8, wherein the capacitor bank structure further comprises a plurality of conductive pillars disposed around the capacitor and extending through the protective material for electrically connecting the semiconductor device and the conductive structure.
10. The semiconductor package structure of claim 8, wherein an area of the capacitor bank structure as viewed from a top view is smaller than an area of the semiconductor device as viewed from the top view, and further comprising a plurality of internal pillars disposed outside the capacitor bank structure and electrically connected to the semiconductor device and the conductive structure.
11. The semiconductor package structure of claim 7, further comprising a redistribution layer disposed between the semiconductor device and the at least one capacitor, wherein the redistribution layer includes at least one fiducial marker.
12. The semiconductor package structure of claim 7, wherein the at least one capacitor comprises a plurality of capacitors disposed side-by-side, the capacitors disposed outside the encapsulation, the semiconductor package structure further comprising a bottom protective material covering the capacitors, wherein an area of the bottom protective material from a top view is greater than an area of the semiconductor device from the top view.
13. The semiconductor package structure of claim 7, wherein the encapsulant is a bottom encapsulant and the semiconductor package structure further comprises a top package electrically connected to the external posts, wherein the top package comprises:
a top substrate;
one or more memory dies electrically connected to the top substrate; and
a top encapsulant covering the one or more memory dies and the top substrate.
14. The semiconductor package structure of claim 13, further comprising a routing structure disposed between the bottom encapsulant and the top package, wherein the routing structure includes at least one circuit layer.
15. A method for fabricating a semiconductor package structure, comprising:
(a) providing at least one capacitor, an encapsulation, and a plurality of external pillars on a semiconductor device, wherein the at least one capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof and a plurality of second electrodes disposed adjacent to the second surface thereof, the second electrodes being electrically connected to the semiconductor device, the encapsulation covering the semiconductor device, and the external pillars extending through the encapsulation; and
(b) forming a conductive structure on the at least one capacitor, the encapsulation, and the outer pillars, wherein the first electrode of the at least one capacitor is electrically connected to the conductive structure, and the at least one capacitor is disposed between the semiconductor device and the conductive structure.
16. The method of claim 15, wherein (a) comprises:
(a1) providing the semiconductor device;
(a2) electrically connecting the second electrode of the at least one capacitor to the semiconductor device to form an assembly;
(a3) attaching the assembly and the external strut to a first support carrier, wherein the external strut is disposed around the assembly; and
(a4) forming the encapsulation to cover the semiconductor device, the at least one capacitor, and the external posts.
17. The method of claim 16, wherein in (a2), the at least one capacitor comprises a plurality of capacitors, and (a2) comprises:
(a21) providing the first support carrier and a second dielectric layer, wherein the second dielectric layer defines a plurality of openings;
(a22) forming a plurality of conductive pads in the openings of the second dielectric layer;
(a23) electrically connecting the second electrode of the capacitor to the conductive pad;
(a24) forming a protective material to cover the capacitor;
(a25) thinning the protective material to expose the first electrode of the capacitor;
(a26) forming a first dielectric layer on the protective material, wherein the first dielectric layer defines a plurality of openings to expose the first electrode of the capacitor; and
(a27) forming a plurality of first pillars in the openings of the first dielectric layer to contact the first electrodes of the capacitors, wherein the first pillars protrude from the first dielectric layer.
18. The method of claim 17, further comprising:
(a28) attaching a second support carrier to the first leg;
(a29) removing the first support carrier;
(a30) forming a third dielectric layer on the second dielectric layer, wherein the third dielectric layer defines a plurality of openings to expose the conductive pads;
(a31) forming a plurality of second pillars in the openings of the third dielectric layer to contact the conductive pads, wherein the second pillars protrude from the third dielectric layer; and
(a32) removing the second support carrier.
19. The method of claim 15, wherein (a) comprises:
(a1) providing the semiconductor device;
(a2) attaching the semiconductor device and the outer posts to a first support carrier, wherein the outer posts are disposed around the semiconductor device;
(a3) forming the encapsulation to cover the semiconductor device and the outer pillars; and
(a4) electrically connecting the second electrode of the at least one capacitor to the semiconductor device and the external post.
20. The method of claim 19, wherein after (b), the method further comprises:
(c) attaching a second support carrier to the electrically conductive structure and removing the first support carrier;
(d) electrically connecting a top package to the outer posts; and
(e) removing the second support carrier.
Technical Field
The invention relates to a capacitor bank structure and a semiconductor package structure comprising at least one capacitor, and methods of manufacturing the same.
Background
As microelectronic technology advances, the size of semiconductor devices will become smaller, which will cause the operating voltage of the overall electronic system to become lower and lower, and the stability of voltage variation will be an important issue. To achieve stability of the voltage variation, more electronic devices, such as decoupling capacitors (decoupling capacitors), should be integrated at the power supply of the electronic system. In addition to providing a more stable power output to an electronic system, decoupling capacitors can also effectively reduce noise of electronic devices coupled to a power supply; thereby indirectly reducing the impact of the noise (noise) of the electronic device on other electronic devices and suppressing undesirable radiation. That is, when the power of the electronic system is turned off, a voltage surge (voltage surge) can be effectively suppressed; and can also suppress voltage drop when the power of the electronic system is turned on.
Disclosure of Invention
In some embodiments, a capacitor bank structure includes a plurality of capacitors, a protective material, a first dielectric layer, and a plurality of first pillars. The capacitors are arranged side by side. Each of the capacitors has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrode is disposed adjacent to the first surface for external connection, and the second electrode is disposed adjacent to the second surface for external connection. The protective material covers the capacitor, sidewalls of the first electrode, and sidewalls of the second electrode, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protective material and defines a plurality of openings to expose the first electrode. The first pillar is disposed in the opening of the first dielectric layer and protrudes from the first dielectric layer.
In some embodiments, a semiconductor package structure includes a conductive structure, a semiconductor device, at least one capacitor, an encapsulant, and a plurality of external pillars. The conductive structure has a top surface and a bottom surface opposite the top surface. The semiconductor device is electrically connected to a top surface of a conductive structure. The capacitor is disposed between the semiconductor device and the top surface of the conductive structure. The capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof for electrically connecting to the conductive structures and a plurality of second electrodes disposed adjacent to the second surface thereof for electrically connecting to the semiconductor device. An encapsulant covers the semiconductor device and the conductive structure. An outer post is disposed around the semiconductor device and extends through the encapsulation.
In some embodiments, a method for fabricating a semiconductor package structure includes: (a) providing at least one capacitor, an encapsulation, and a plurality of external pillars on a semiconductor device, wherein the capacitor has a first surface and a second surface opposite the first surface, and includes a plurality of first electrodes disposed adjacent to the first surface thereof and a plurality of second electrodes disposed adjacent to the second surface thereof for electrical connection to the semiconductor device; an encapsulant covering the semiconductor device; and the outer struts extend through the encapsulation; and (b) forming a conductive structure over the at least one capacitor, the encapsulation, and the outer pillars, wherein a first electrode of the capacitor is electrically connected to the conductive structure, and the at least one capacitor is disposed between the semiconductor device and the conductive structure.
Drawings
Aspects of some embodiments of the invention are readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be necessarily drawn to scale, and that the dimensions of the various structures may be arbitrarily increased or decreased for clarity of discussion.
Figure 1 illustrates a cross-sectional view of a capacitor bank structure according to some embodiments of the invention.
Figure 2 illustrates a cross-sectional view of a capacitor bank structure according to some embodiments of the invention.
Figure 3 illustrates a cross-sectional view of a capacitor bank structure according to some embodiments of the invention.
Fig. 4 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 5 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 6 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 7 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 8 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 9 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 10 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 11 illustrates a cross-sectional view of a semiconductor package structure, according to some embodiments of the invention.
Fig. 12 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 13 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 14 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 15 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 16 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 17 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 18 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 19 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 20 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 21 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 22 illustrates one or more stages of an example of a method for fabricating a capacitor bank structure, in accordance with some embodiments of the invention.
Fig. 23 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 24 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 25 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 26 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 27 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 28 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 29 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 30 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 31 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 32 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 33 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, in accordance with some embodiments of the invention.
Fig. 34 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 35 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 36 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 37 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 38 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 39 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 40 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 41 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 42 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 43 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, in accordance with some embodiments of the invention.
Fig. 44 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 45 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 46 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 47 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 48 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 49 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 50 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 51 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 52 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 53 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, in accordance with some embodiments of the invention.
Fig. 54 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, in accordance with some embodiments of the invention.
Fig. 55 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Fig. 56 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, in accordance with some embodiments of the invention.
Fig. 57 illustrates one or more stages of an example of a method for fabricating a semiconductor package structure, according to some embodiments of the invention.
Detailed Description
Common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components. Embodiments of the present invention will be readily understood by the detailed description in conjunction with the accompanying drawings.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, references to the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In a comparative package structure, capacitors such as decoupling capacitors may be placed as close as possible to a semiconductor die or hotspot in order to increase its effectiveness. That is, the capacitor may be mounted on one side of the semiconductor die, on a pad of the substrate, or embedded in the substrate. These three types are described as follows. In a first type, the capacitors mounted on the sides of the semiconductor Die are referred to as "Die Side Capacitors (DSCs)". The capacitor and the semiconductor die are mounted side-by-side to the substrate. Although DSCs are easy to package, the disadvantage is that the current path is too long and wastes too much area. In the second type, a Capacitor Embedded inside a substrate is referred to as an "Embedded Capacitor (ECC)". While ECC has better performance than DSC, the thickness of the substrate that houses ECC is relatively large. Furthermore, the assembly cost of the ECC may be relatively high. In the third type, a capacitor mounted on a Land pad (Land pad) of the bottom surface of the substrate is referred to as a "Land Side Capacitor (LSC)". While LSCs do not have thickness and cost issues compared to ECCs, LSCs reduce the number of solder balls. Furthermore, the LSC increases the size of the solder balls.
At least some embodiments of the present invention provide a semiconductor package structure including at least one capacitor disposed between a semiconductor device and a conductive structure. Therefore, a decoupling loop (decoupling loop) is shortened, and a ball attachment area of a bottom surface of the conductive structure is increased.
Fig. 1 illustrates a cross-sectional view of a capacitor bank structure 1 according to some embodiments of the invention. The capacitor bank structure (capacitor bank structure)1 may include one or more capacitors 12, a protective material 13 (e.g., including a first protective material 13a and a second protective material 13b), a first dielectric layer 14, a plurality of first pillars 15, a plurality of conductive pads 16, a second dielectric layer 17, a third dielectric layer 18, a plurality of second pillars 19, and a plurality of conductive pillars 11.
The capacitors 12 are arranged side by side. The capacitor 12 may be a double-sided decoupling capacitor (double-sided decoupling capacitor) or a single-sided decoupling capacitor (single-sided decoupling capacitor). As shown in fig. 1, each of the capacitors 12 is a double-sided decoupling capacitor, and has a first surface 121 and a second surface 122 opposite to the first surface 121, and includes a plurality of first electrodes 123 and a plurality of second electrodes 124. A first electrode 123 is disposed adjacent to the first surface 121 of the capacitor 12 for external connection, and a second electrode 124 is disposed adjacent to the second surface 122 of the capacitor 12 for external connection. That is, both sides (e.g., the first surface 121 and the second surface 122) of the capacitor 12 may be used for electrical connection. Further, the first surface 121 is electrically connected to the second surface 122. Thus, the first electrode 123 on the first surface 121 may be electrically connected to the second electrode 124 on the second surface 122. It should be noted that the number of the first electrodes 123 may be equal to or different from the number of the second electrodes 124. In addition, each of the first electrodes 123 has a first surface 1231 and sidewalls 1233, and each of the second electrodes 124 has sidewalls 1243. The thickness of each of the capacitors 12 may be less than 50 μm, or less than 30 μm.
The conductive pad 16 is electrically connected to the second electrode 124 of the capacitor 12. In some embodiments, the conductive pad 16 may be a copper layer, and may further include at least one surface finishing layer (e.g., a nickel (Ni) layer 161 and a gold (Au) layer 162). The Au layer 162 of the surface finishing layer of the conductive pad 16 is connected or bonded to the second electrode 124 of the capacitor 12 through the solder layer 125. As shown in fig. 1, each of the conductive pads 16 has a second surface 164 and a sidewall 163.
The protective material 13 covers the capacitor 12, the sidewall 1233 of the first electrode 123, the sidewall 1243 of the second electrode 124, and the sidewall 163 of the conductive liner 16. As shown in fig. 1, the protective material 13 may be located between the first dielectric layer 14 and the second dielectric layer 17. The protective material 13 has a first surface 131 corresponding to the first surface 121 of the capacitor 12 and a second surface 132 corresponding to the second surface 122 of the capacitor 12. The first surface 131 of the protective material 13 may contact the first dielectric layer 14 and the second surface 132 of the protective material 13 may contact the second dielectric layer 17. In some embodiments, the protective material 13 may include an underfill (underfill) and/or a molding compound (molding compound). As shown in fig. 1, the protective material 13 may include a first protective material 13a and a second protective material 13 b. The first protective material 13a covers the capacitor 12, the sidewall 1243 of the second electrode 124, and the sidewall 163 of the conductive pad 16. The second protective material 13b covers the first protective material 13b and the sidewall 1233 of the first electrode 123. The material of the first protective material 13a may be the same as or different from the material of the second protective material 13 b. In some embodiments, the material of the first protective material 13a may be an underfill and the material of the second protective material 13b may be a molding compound 13 b. The first protective material 13a may have a first surface 131a and a second surface 132a opposite the first surface 131 a. The first surface 131a of the first protective material 13a may be substantially coplanar with the first surface 121 of the capacitor 12. The second protective material 13b may have a first surface 131b and a second surface 132b opposite the first surface 131 b. A portion of the second protective material 13b is disposed between the first surface 131a of the first protective material 13a and the first dielectric layer 14. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13. The second surface 132b of the second protective material 13b and the second surface 132a of the first protective material 13a constitute the second surface 132 of the protective material 13.
The conductive pillars 11 are disposed around the capacitor 12 and extend through the protective material 13. As shown in fig. 1, the conductive pillar 11 is disposed around the capacitor 12 and a first protective material 13a of the protective material 13, and extends through a second protective material 13b of the protective material 13. The conductive pillars 11 may be disposed between the first and third dielectric layers 14, 18 and extend through the second dielectric layer 17. Each of the conductive pillars 11 has a first surface 111 and a second surface 112 opposite the first surface 111. As shown in fig. 1, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11, and the first surface 131 of the protective material 13 are substantially coplanar with one another.
A first dielectric layer 14, such as a passivation layer, is disposed on the first surface 131 of the protective material 13 and defines a plurality of openings 141 to expose the first electrodes 123 and the conductive posts 11. The first dielectric layer 14 may include or be formed from: a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy or Polyimide (PI) containing a photoinitiator, or a combination of two or more of these. The first pillar 15 is disposed in the opening 141 of the first dielectric layer 14 and protrudes from the first dielectric layer 14. Thus, the first post 15 contacts the first surface 1231 of the first electrode 123 and the first surface 111 of the conductive post 11.
A second dielectric layer 17 (e.g., a passivation layer) is disposed on the second surface 132 of the protective material 13 and covers the sidewalls 163 of the conductive liner 16 and the sidewalls of the conductive pillars 11. The second dielectric layer 17 has a first surface 171 and a second surface 172 opposite the first surface 171. As shown in fig. 1, the second surface 164 of the conductive liner 16, the second surface 112 of the conductive pillar 11, and the second surface 172 of the second dielectric layer 17 are substantially coplanar with one another. The second dielectric layer 17 may include or be formed from: a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy or Polyimide (PI) containing a photoinitiator, or a combination of two or more of these.
A third dielectric layer 18, such as a passivation layer, is disposed on the second dielectric layer 17 and defines a plurality of openings 181 to expose the conductive pads 16 and the conductive pillars 11. The third dielectric layer 18 may include or be formed from: a photoresist layer, a cured photosensitive material, a cured photoimageable dielectric (PID) material, such as an epoxy or Polyimide (PI) containing a photoinitiator, or a combination of two or more of these. The second pillars 19 are disposed in the openings 181 of the third dielectric layer 18 and protrude from the third dielectric layer 18. Thus, the second leg 19 contacts the second surface 164 of the conductive pad 16 and the second surface 112 of the conductive leg 11. As shown in fig. 1, some of the second support posts 19 may be electrically connected to some of the first support posts 15 through the conductive pads 16, the Ni layer 161, the Au layer 162, the solder layer 125, the second electrode 124, the capacitor 12, and the first electrode 123. Additionally, some of the second support posts 19 may be electrically connected to some of the first support posts 15 through the conductive support posts 11.
Figure 2 illustrates a cross-sectional view of a capacitor bank structure 1a according to some embodiments of the invention. The capacitor bank structure 1a of fig. 2 may be similar to the capacitor bank structure 1 of fig. 1, except that the conductive pillars 11 are omitted and the protective material 13 may comprise the first protective material 13a or the second protective material 13b alone. As shown in fig. 2, the first surface 131a of the first protective material 13a is the first surface 131 of the protective material 13, and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.
Fig. 3 illustrates a cross-sectional view of a capacitor bank structure 1b according to some embodiments of the invention. The capacitor bank structure 1b of fig. 3 may be similar to the capacitor bank structure 1 of fig. 1, except that the conductive pillars 11 are omitted. As shown in fig. 3, the second surface 132b of the second protective material 13b is disposed on the first surface 131a of the first protective material 13 a. The first surface 131b of the second protective material 13b is the first surface 131 of the protective material 13, and the second surface 132a of the first protective material 13a is the second surface 132 of the protective material 13.
Fig. 4 illustrates a cross-sectional view of a semiconductor package structure 2, according to some embodiments of the invention. The semiconductor package structure 2 includes a conductive structure 24, a semiconductor device 25, one or more capacitors 12, an encapsulation (encapsulation) 26, a plurality of outer pillars 27, a top package 3, a plurality of inner pillars 28, a redistribution structure (redistribution structure)29, a wiring structure (wiring structure)4, and a plurality of solder bumps (solder bumps) 37.
The conductive structure 24 may be a substrate or interposer and may have a top surface 241 and a bottom surface 242 opposite the top surface 241. In some embodiments, the conductive structure 24 may include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The semiconductor device 25 may be a semiconductor logic die (semiconductor logic die), such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or an Application Processor (AP), and may be electrically connected to the top surface 241 of the conductive structure 24. As shown in fig. 4, the semiconductor device 25 has a first surface 251 and a second surface 252 opposite to the first surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 through the redistribution circuit structure 29, the capacitor bank structure 1a, and the internal support posts 28. The second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. The capacitor bank structure 1a may be the same as the capacitor bank structure 1a of fig. 2, and may include one or more capacitors 12. Thus, the capacitor 12 is disposed between the first surface 251 of the semiconductor device 25 and the top surface 241 of the conductive structure 24. The first electrode 123 is electrically connected to the conductive structure 24. The second electrode 124 is electrically connected to the semiconductor device 25 through the solder layer 125, the Ni layer 161, the Au layer 162, the conductive pad 16, the second support pillar 19, the conductive pad 281, and the redistribution circuit structure 29. The capacitor 12 is not embedded in the conductive structure 24. The area of the capacitor bank structure 1a in the top view is smaller than the area of the semiconductor device 25 in the top view. The inner post 28 is disposed outside the capacitor bank structure 1a and is electrically connected to the semiconductor device 25 and the conductive structure 24.
A redistribution circuit structure 29, e.g., including a first passivation layer 291, a second passivation layer 294, and a redistribution layer (RDL)293, is disposed between the semiconductor device 25 and the capacitor bank structure 1a, including the capacitor 12. The size of the redistribution circuit structure 29 may be substantially equal to the size of the semiconductor device 25. The inner support posts 28 may stand on the redistribution circuit structure 29. In addition, a redistribution layer (RDL)293 may contain fiducial marks 296. However, in some embodiments, redistribution circuitry 29 may be omitted.
An encapsulant 26 is disposed in the space between the wiring structure 4 and the conductive structure 24 to cover the semiconductor device 25, the capacitor bank structure 1a (including the capacitor 12), the conductive structure 24, the internal pillars 28, and the redistribution circuit structure 29. The material of the encapsulant 26 may be a molding compound.
Outer posts 27 are disposed around semiconductor device 25 and extend through encapsulation 26 to electrically connect wiring structure 4 and conductive structure 24. The wiring structure 4 is disposed between the encapsulation 26 and the top package 3. The wiring structure 4 comprises at least one dielectric layer and at least one circuit layer 40. However, in some embodiments, the wiring structure 4 may be omitted.
The top package 3 is electrically connected to the external posts 27 and the semiconductor device 25 through the internal solder 35 and the wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dies (memory dice)32, and a top encapsulant 34. The Memory die 32 may be a Synchronous Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a low power DDR (LPDDR), or a High Bandwidth Memory (HBM). The memory die 32 is electrically connected to the top substrate 30 by wire bonds. However, the memory die 32 may be electrically connected to the top substrate 30 by flip chip bonding. A top encapsulant 34 covers the plurality of memory dies 32 and the top substrate 30. Additionally, an intermediate encapsulant 36 may be included in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Further, solder bumps 37 are disposed on the second surface 242 of the conductive structure 24 for external connection.
In the semiconductor package structure 2 illustrated in fig. 4, the capacitor 12 is disposed between the semiconductor device 25 and the conductive structure 24. Thus, the decoupling loop can be shortened. Furthermore, the ball attachment area of the second surface 242 of the conductive structure 24 may be increased because the capacitor 12 is not attached to the second surface 242 of the conductive structure 24. That is, there may be more solder bumps 37 disposed on the second surface 242 of the conductive structure 24. Further, the amount of the capacitor 12 can be increased. In addition, the capacitor bank structure 1a is a reconstruction structure (reconstruction structure) that can reduce the manufacturing time of the semiconductor package 2 and improve the yield of the semiconductor package 2.
Fig. 5 illustrates a cross-sectional view of a semiconductor package structure 2a, according to some embodiments of the invention. The semiconductor package structure 2a of fig. 5 may be similar to the semiconductor package structure 2 of fig. 4, except that the capacitor bank structure 1a is replaced with the capacitor bank structure 1 of fig. 1, and the inner pillars 28 are omitted. As shown in fig. 5, the area of the capacitor bank structure 1a from the top view is substantially equal to the area of the semiconductor device 25 from the top view. Therefore, the inner post 28 of fig. 4 is not necessary, and the conductive post 11 of the capacitor bank structure 1 is electrically connected to the redistribution circuit structure 29 (or semiconductor device 25) and the conductive structure 24. In addition, an underfill 38 is formed between the space between the capacitor bank structure 1 and the redistribution circuit structure 29 (or the semiconductor device 25) to cover and protect the junction structure (junction structure) between the capacitor bank structure 1 and the redistribution circuit structure 29 (or the semiconductor device 25). The area of the underfill 38 as viewed from the top view is substantially equal to the area of the semiconductor device 25 as viewed from the top view.
Fig. 6 illustrates a cross-sectional view of a semiconductor package structure 2b, according to some embodiments of the invention. The semiconductor package 2b of fig. 6 may be similar to the semiconductor package 2 of fig. 4, and the differences are described as follows. The inner post 28 is disposed on the first surface 251 of the semiconductor device 25. An intermediate redistribution structure 43, including a redistribution layer (RDL)431, is disposed on the encapsulation 26 to electrically connect the inner and outer pillars 28, 27. The capacitor 12 is disposed on and electrically connected to a redistribution layer (RDL)431 of the intermediate redistribution structure 43. Each of the capacitors 12b is a double-sided decoupling capacitor, and has a first surface 121b and a second surface 122b opposite to the first surface 121b, and includes a plurality of first electrodes 123b and a plurality of second electrodes 124 b. The first electrode 123b is disposed adjacent to the first surface 121b of the capacitor 12b for external connection, and the second electrode 124b is disposed adjacent to the second surface 122b of the capacitor 12b for external connection. That is, both sides (e.g., the first surface 121b and the second surface 122b) of the capacitor 12b may be used for electrical connection. An under-protection material 42 (e.g., underfill) is disposed on the intermediate redistribution structure 43 to cover and protect the capacitor 12. It should be noted that the area of the bottom protective material 42 as viewed from the top view is larger than the area of the semiconductor device 25 as viewed from the top view. An insulating layer 46 is formed or disposed on the intermediate redistribution structure 43 to cover the bottom protective material 42 and the sidewalls of the first electrode 123b of the capacitor 12 b. The conductive structure 24 is disposed on the insulating layer 46 and electrically connected to the first electrode 123b of the capacitor 12 b. In addition, a plurality of outer posts 27' are disposed around capacitor 12b and bottom protective material 42, and electrically connect intermediate redistribution structure 43 and conductive structure 24.
Fig. 7 illustrates a cross-sectional view of a semiconductor package structure 2c according to some embodiments of the invention. The semiconductor package 2c of fig. 7 may be similar to the semiconductor package 2 of fig. 4, except for the location of the capacitor 12 c. As shown in fig. 7, capacitor 12c is embedded in conductive structure 24. In addition, the thickness of the semiconductor device 25c may be substantially equal to the height of the outer pillars 27.
Fig. 8 illustrates a cross-sectional view of a semiconductor package structure 2d, according to some embodiments of the invention. The semiconductor package 2d of fig. 8 may be similar to the semiconductor package 2 of fig. 4, except for the location of the capacitor 12 d. As shown in fig. 8, the capacitor 12d is disposed between the conductive structure 24 and the wiring structure 4. The capacitor 12d is disposed around the semiconductor device 25 d. That is, the capacitor 12d and the semiconductor device 25d are arranged side by side. The thickness of the semiconductor device 25d, the thickness of the capacitor 12d, and the height of the outer pillars 27 may be substantially equal to each other.
Fig. 9 illustrates a cross-sectional view of a semiconductor package structure 2e, according to some embodiments of the invention. The semiconductor package structure 2E includes a photo die (P-die) 50, an electrical die (E-die) 52, a plurality of capacitors 12E, a plurality of external posts 27, an encapsulant 26, and a plurality of solder bumps 37. The electrical die (E-die) 52, the capacitors 12E and the external posts 27 are electrically connected to the bottom surface of the optical die (P-die) 50. That is, the electrical die (E-die) 52 and the capacitor 12E are disposed side-by-side. The outer support 27 is disposed around the electrical die (E-die) 52 and the capacitor 12E. The encapsulant 26 covers the bottom surface of the photo die (P-die) 50, the electrical die (E-die) 52, the capacitor 12E, and the external posts 27. The outer struts 27 extend through the encapsulation 26 and are exposed from the bottom surface of the encapsulation 26. Solder bumps 37 are disposed on the bottom surface of the encapsulant 26 and electrically connected to the outer posts 27.
Fig. 10 illustrates a cross-sectional view of a semiconductor package structure 2f, according to some embodiments of the invention. The semiconductor package structure 2f includes a conductive structure 24, a capacitor bank structure 1b, a semiconductor device 54, a memory die 56, an encapsulation 26, and a plurality of solder bumps 37. The capacitor bank structure 1b is disposed on or electrically connected to the first surface 241 of the conductive structure 24. The capacitor bank structure 1b may include a plurality of capacitors 12f, a bridge die 58, a plurality of pillars 62, and a protective material 60. The capacitor 12f and the bridge die 58 are disposed side by side and covered by a protective material 60. The posts 62 extend through the protective material 60. The semiconductor device 54 and the memory die 56 are disposed on the capacitor bank structure 1b, and are electrically connected to the capacitors 12f and the bridge die 58. Thus, the capacitor bank structure 1b is disposed between the semiconductor devices 54 and the memory dies 56 and the conductive structures 24. The semiconductor device 54 is electrically connected to the memory die 56 through the bridge die 58. The encapsulant 26 covers the first surface 241 of the conductive structures 24, the capacitor bank structure 1b, the semiconductor devices 54, and the memory die 56. The solder bumps 37 are disposed on the second surface 242 of the conductive structure 24.
Fig. 11 illustrates a cross-sectional view of a semiconductor package structure 2g, according to some embodiments of the invention. Semiconductor package 2g of fig. 11 may be similar to semiconductor package 2f of fig. 10, except for the location of capacitor 12g and bridge die 58. As shown in fig. 11, the bridge die 58 is embedded in the conductive structure 24, and the capacitor 12g is disposed on or electrically connected with the first surface 241 of the conductive structure 24. The encapsulant 26 covers the first surface 241 of the conductive structures 24, the capacitors 12g, the semiconductor devices 54, and the memory die 56.
Fig. 12-22 illustrate methods for fabricating capacitor bank structures according to some embodiments of the invention. In some embodiments, the method is used to manufacture the capacitor bank structure 1 shown in fig. 1. Referring to fig. 12, a first support carrier 20 and a second dielectric layer 17 are provided. The second dielectric layer 17 is disposed on the first support carrier 20 and defines a plurality of openings 171.
Referring to fig. 13, a plurality of conductive pads 16 and a plurality of conductive pillars 11 are formed in openings 171 of a second dielectric layer 17. The conductive pad 16 may include at least one surface finishing layer (e.g., a Ni layer 161 and an Au layer 62) on its end face. As shown in fig. 13, each of the conductive pads 16 has a second surface 164 and sidewalls 163.
Referring to fig. 14, one or more capacitors 12 are electrically connected to conductive pads 16. The capacitor 12 may be a double-sided decoupling capacitor. The capacitor 12 has a first surface 121 and a second surface 122 opposite to the first surface 121, and includes a plurality of first electrodes 123 and a plurality of second electrodes 124. The first electrode 123 is disposed adjacent to the first surface 121 of the capacitor 12, and the second electrode 124 is disposed adjacent to the second surface 122 of the capacitor 12. The second electrode 124 of the capacitor 12 is connected to the surface finishing layer (e.g., the Ni layer 161 and the Au layer) of the conductive pad 16 through the solder layer 125. In addition, each of the first electrodes 123 has a first surface 1231 and sidewalls 1233, and each of the second electrodes 124 has sidewalls 1243.
Referring to fig. 15 and 16, protective material 13 (e.g., including first protective material 13a and second protective material 13b) is formed to cover capacitor 12, sidewall 1233 of first electrode 123, sidewall 1243 of second electrode 124, and sidewall 163 of conductive liner 16. Referring to fig. 15, a first protective material 13a is formed to cover the capacitor 12, the sidewall 1243 of the second electrode 124, and the sidewall 163 of the conductive pad 16. Referring to fig. 16, a second protective material 13b is formed to cover the first protective material 13a and the sidewalls 1233 of the first electrode 123 and the sidewalls of the conductive pillar 11. The protective material 13 (including the first protective material 13a and the second protective material 13b) and has a first surface 131 corresponding to the first surface 121 of the capacitor 12 and a second surface 132 corresponding to the second surface 122 of the capacitor 12.
Referring to fig. 17, the second protective material 13b of the protective material 13 is thinned from the first surface 131 to expose the first electrode 123 and the conductive pillar 11. Meanwhile, the first surface 1231 of the first electrode 123, the first surface 111 of the conductive pillar 11, and the first surface 131 of the protective material 13 are substantially coplanar with each other.
Referring to fig. 18, a first dielectric layer 14 is formed on the first surface 131 of the protective material 13. The first dielectric layer 14 defines a plurality of openings 141 to expose the first electrodes 123 and the conductive pillars 11.
Referring to fig. 19, a plurality of first pillars 15 are formed in the openings 141 of the first dielectric layer 14. The first pillar 15 contacts the first electrode 123 and the conductive pillar 11, and protrudes from the first dielectric layer 14.
Referring to fig. 20, the second support carrier 22 is attached to the first pillars 15 and the first dielectric layer 14 by an adhesive layer 221. Subsequently, the first support carrier 20 is removed.
Referring to fig. 21, a third dielectric layer 18 is formed on the second dielectric layer 17. The third dielectric layer 18 defines a plurality of openings 181 to expose the conductive pads 16 and the conductive pillars 11.
Referring to fig. 22, a plurality of second pillars 19 are formed in the openings 181 of the third dielectric layer 18. The second pillar 19 contacts the conductive pad 16 and the conductive pillar 11 and protrudes from the third dielectric layer 18. Subsequently, a singulation process (singulation process) is performed, and the second support carrier 22 and the adhesive layer 221 are removed so as to form the multiple capacitor bank structure 1 of fig. 1.
Fig. 23-36 illustrate methods for fabricating semiconductor package structures according to some embodiments of the invention. In some embodiments, the method is used to fabricate the semiconductor package structure 2 shown in fig. 4. Referring to fig. 23, a wafer 5 including a plurality of semiconductor devices 25 is provided. The semiconductor device 25 may be a logic die, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or an Application Processor (AP), and may have a first surface 251 and a second surface 252 opposite the first surface 251.
Referring to fig. 24, a first passivation layer 291 is formed on a first surface 251 of the semiconductor device 25 (e.g., a first surface of the wafer 5). The first passivation layer 291 defines a plurality of openings 292.
Referring to fig. 25, a redistribution layer (RDL)293 is formed in the opening 292 and on the first passivation layer 291. In some embodiments, a redistribution layer (RDL)293 may include fiducial marks 296.
Referring to fig. 26, a second passivation layer 294 is formed on the redistribution layer (RDL)293 and the first passivation layer 291. The second passivation layer 294 defines a plurality of openings 295 to expose portions of the redistribution layer (RDL) 293. At the same time, redistribution structure 29 (including first passivation layer 291, redistribution layer (RDL)293, and second passivation layer 294) is formed.
Referring to fig. 27, a plurality of conductive pads 281 and a plurality of inner pillars 28 are formed in openings 295 and on a redistribution layer (RDL) 293. At least one surface finish layer may be present on the end face of the conductive pad 281.
Referring to fig. 28, the capacitor bank structure 1a of fig. 2 is attached to a conductive pad 281. In one embodiment, the second leg 19 of the capacitor bank structure 1a is connected to the surface finish layer of the conductive pad 281. Thus, the capacitor 12 is electrically connected to the semiconductor device 25. The inner post 28 is disposed around the capacitor bank structure 1a (including the capacitor 12). It should be noted that the fiducial mark 296 of the redistribution layer (RDL)293 may be used for positioning when the capacitor bank structure 1a is attached to the redistribution structure 29.
Referring to fig. 29, a wafer 5 is subjected to a singulation process to form a plurality of assemblies 5 a.
Referring to fig. 30, a third support carrier 41 (or first carrier) is provided. Subsequently, a wiring structure 4 (comprising at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or first carrier). Subsequently, a plurality of outer posts 27 are formed or attached on the wiring structure 4.
Referring to fig. 31, the second surface 252 of the semiconductor device 25 of the assembly 5a is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or first carrier). At the same time, outer struts 27 are disposed around assembly 5 a.
Referring to fig. 32, an encapsulant 26 is formed to cover assembly 5a (including semiconductor device 25, capacitor 12) and outer posts 27.
Referring to fig. 33, the encapsulant 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the encapsulation 26, the bottom surface of the outer strut 27, the bottom surface of the inner strut 28, and the bottom surface of the first strut 15 are substantially coplanar with one another.
Referring to fig. 34, a conductive structure 24 is formed or disposed on the encapsulation 26 to electrically connect the outer pillar 27, the first pillar 15, and the inner pillar 28. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite the top surface 241. In some embodiments, the conductive structure 24 may include four dielectric layers 243 (e.g., four passivation layers) and four metal circuit layers 244 electrically connected to each other. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 through the redistribution circuit structure 29, the capacitor bank structure 1a, and the internal support posts 28. The capacitor 12 is not embedded in the conductive structure 24. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.
Referring to fig. 35, a fourth support carrier 45 (or second carrier) is attached to the second surface 242 of the conductive structure 24 by an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.
Referring to fig. 36, the top package 3 is electrically connected to the outer posts 27. In one embodiment, the top package 3 is electrically connected to the external posts 27 and the semiconductor device 25 through the internal solder 35 and the wiring structure 4. In one embodiment, the top package 3 includes a top substrate 30, one or more memory dies 32, and a top encapsulant 34. The memory die 32 may be Synchronous Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), low power ddr (lpddr), or High Bandwidth Memory (HBM). The memory die 32 is electrically connected to the top substrate 30 by wire bonds. However, the memory die 32 may be electrically connected to the top substrate 30 by flip chip bonding. A top encapsulant 34 covers the plurality of memory dies 32 and the top substrate 30. In addition, an intermediate encapsulant 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed so as to form the plurality of semiconductor package structures 2 of fig. 4.
Fig. 37-46 illustrate methods for fabricating semiconductor package structures according to some embodiments of the invention. In some embodiments, the method is used to fabricate the semiconductor package structure 2a shown in fig. 5. The initial stages of the illustrated process are the same as or similar to the stages illustrated in fig. 23-26. Fig. 37 depicts a stage subsequent to that depicted in fig. 26.
Referring to fig. 37, a plurality of conductive pads 281 are formed in openings 295 and on a redistribution layer (RDL) 293. A surface finish layer may be present on the end face of the conductive pad 281.
Referring to fig. 38, the capacitor bank structure 1 of fig. 1 is attached to a conductive pad 281. In one embodiment, the second pillars 19 and the conductive pillars 11 of the capacitor bank structure 1 are connected to the surface finish layer of the conductive liner 281. Thus, the capacitor 12 is electrically connected to the semiconductor device 25. Subsequently, an underfill 38 is formed between the space between the capacitor bank structure 1 and the redistribution circuit structure 29 (or the semiconductor device 25) to cover and protect the bonding structure between the capacitor bank structure 1 and the redistribution circuit structure 29 (or the semiconductor device 25).
Referring to fig. 39, the wafer 5 is subjected to a singulation process to form a plurality of assemblies 5 b.
Referring to fig. 40, a third support carrier 41 (or first carrier) is provided. Subsequently, a wiring structure 4 (comprising at least one dielectric layer and at least one circuit layer 40) is formed on the third support carrier 41 (or first carrier). Subsequently, a plurality of outer posts 27 are formed or attached on the wiring structure 4.
Referring to fig. 41, the second surface 252 of the semiconductor device 25 of the assembly 5b is attached (or adhered) to the wiring structure 4 on the third support carrier 41 (or first carrier). At the same time, outer struts 27 are disposed around assembly 5 b.
Referring to fig. 42, an encapsulant 26 is formed to cover assembly 5b (including semiconductor device 25, capacitor 12) and outer posts 27.
Referring to fig. 43, the encapsulant 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the encapsulation 26, the bottom surface of the outer strut 27, and the bottom surface of the first strut 15 are substantially coplanar with one another.
Referring to fig. 44, a conductive structure 24 is formed or disposed on the encapsulation 26 to electrically connect the outer pillar 27 and the first pillar 15. The conductive structure 24 has a top surface 241 and a bottom surface 242 opposite the top surface 241. The first surface 251 of the semiconductor device 25 is electrically connected to the top surface 241 of the conductive structure 24 through the redistribution circuit structure 29 and the capacitor bank structure 1. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.
Referring to fig. 45, a fourth support carrier 45 (or second carrier) is attached to the second surface 242 of the conductive structure 24 by an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.
Referring to fig. 46, the top package 3 is electrically connected to the outer posts 27. In one embodiment, the top package 3 is electrically connected to the external posts 27 and the semiconductor device 25 through the internal solder 35 and the wiring structure 4. In addition, an intermediate encapsulant 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form a plurality of semiconductor package structures 2a of fig. 5.
Fig. 47-57 illustrate methods for fabricating semiconductor package structures according to some embodiments of the invention. In some embodiments, the method is used to fabricate the semiconductor package structure 2b shown in fig. 6. The initial stages of the illustrated process are the same as or similar to the stages illustrated in fig. 23-26. Fig. 47 depicts a stage subsequent to that depicted in fig. 26.
Referring to fig. 47, a plurality of outer pillars 27 are formed on the wiring structure 4.
Referring to fig. 48, the second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4. An outer post 27 is disposed around the semiconductor device 25. Subsequently, a plurality of inner pillars 28 are formed on the first surface 251 of the semiconductor device 25. In some embodiments, the inner pillars 28 may be formed first on the first surface 251 of the semiconductor device 25; subsequently, the second surface 252 of the semiconductor device 25 is adhered to the wiring structure 4.
Referring to fig. 49, an encapsulant 26 is formed to cover the semiconductor device 25, the wiring structure 4, the inner pillars 28, and the outer pillars 27.
Referring to fig. 50, the encapsulant 26 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surfaces of the encapsulation 26, the outer struts 27, and the inner struts 28 are substantially coplanar with one another.
Referring to fig. 51, an intermediate redistribution structure 43, including a redistribution layer (RDL)431, is formed or disposed on the encapsulation 26 to electrically connect the outer posts 27 and the inner posts 28.
Referring to fig. 52, at least one capacitor 12b is disposed on and electrically connected to the intermediate redistribution structure 43. The second electrode 124b of the capacitor 12b is electrically connected to a redistribution layer (RDL)431 of the intermediate redistribution structure 43. Thus, the capacitor 12b can be electrically connected to the semiconductor device 25 and the outer post 27. Subsequently, an under-protection material 42 (e.g., underfill) is formed or disposed on the intermediate redistribution structure 43 to cover and protect the capacitor 12 b. It should be noted that the area of the bottom protective material 42 as viewed from the top view is larger than the area of the semiconductor device 25 as viewed from the top view. Subsequently, a plurality of outer struts 27' are formed or disposed on a redistribution layer (RDL)431 of the intermediate redistribution structure 43. The outer pillars 27' are disposed around the capacitor 12b and the underfill 42.
Referring to fig. 53, an insulating layer 46 is formed or disposed on the intermediate redistribution structure 43 to cover the bottom protective material 42, the sidewalls of the first electrode 123b of the capacitor 12b, and the outer posts 27'.
Referring to fig. 54, the insulating layer 46 is thinned from its bottom surface by, for example, grinding. Meanwhile, the bottom surface of the insulating layer 46, the bottom surface of the first electrode 124b of the capacitor 12b, and the bottom surface of the outer post 27' are substantially coplanar with each other.
Referring to fig. 55, the conductive structure 24 is formed or disposed on the insulating layer 46 and electrically connected to the first electrode 123b and the outer post 27' of the capacitor 12 b. In one embodiment, the conductive structure 24 may include four dielectric layers 243 and four metal circuit layers 244. Subsequently, a plurality of solder bumps 37 are formed on the second surface 242 of the conductive structure 24.
Referring to fig. 56, a fourth support carrier 45 (or second carrier) is attached to the second surface 242 of the conductive structure 24 by an adhesive layer 44. Subsequently, the third support carrier 41 (or the first carrier) is removed.
Referring to fig. 57, the top package 3 is electrically connected to the outer posts 27. In one embodiment, the top package 3 is electrically connected to the external posts 27 and the semiconductor device 25 through the internal solder 35 and the wiring structure 4. In addition, an intermediate encapsulant 36 may be formed or disposed in the space between the top substrate 30 and the wiring structure 4 to cover and protect the internal solder 35. Subsequently, a singulation process is performed, and the fourth support carrier 45 (or the second carrier) and the adhesive layer 44 are removed to form a plurality of semiconductor package structures 2b of fig. 6.
Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "above," "below," "upper," "on … …," "under … …," and the like are directed relative to the orientation shown in the figures. It is to be understood that the spatial descriptions used herein are for purposes of illustration only and that actual implementations of the structures described herein may be spatially arranged in any orientation or manner, provided that the embodiments of the invention are not disadvantaged by such arrangements.
As used herein, the terms "substantially", "essentially" and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to the situation in which the event or circumstance occurs explicitly, as well as the situation in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, a first numerical value can be considered to be "substantially" the same as or equal to a second numerical value if the first numerical value varies from less than or equal to ± 10% of the second numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° from 90 °, such as less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.
Two surfaces can be considered coplanar or substantially coplanar if the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm. A surface can be considered substantially flat if the displacement between the highest and lowest points of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
As used herein, the singular terms "a", "an" and "the" may include plural referents unless the context clearly dictates otherwise.
As used herein, the terms "conductive", "electrically conductive", and "conductivity" refer to the ability to transfer electrical current. Conductive materials generally indicate those materials that present little or zero opposition to current flow. One measure of conductivity is siemens per meter (S/m). Typically, the conductive material has a conductivity greater than about 104S/m (e.g. at least 10)5S/m or at least 106S/m) of the above-mentioned material. The conductivity of a material can sometimes change with temperature. Unless otherwise specified, the conductivity of the material was measured at room temperature.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not to be construed in a limiting sense. It should be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing methods and tolerances, there may be differences in art reproduction from actual equipment in this disclosure. There may be other embodiments of the invention not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.
