阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 东田吉生 白井克宗 于 2019-06-06 设计创作，主要内容包括：本发明提供一种半导体器件,其可实现内部电阻的降低。本发明的半导体器件包括：半导体元件,其包括：具有在z方向上彼此朝向相反侧的衬底主面和衬底背面的半导体衬底、形成于衬底主面的元件电极、及形成在衬底主面上且与元件电极导通的配线层；从衬底背面侧支承半导体元件的引线框；将半导体元件和引线框导通的第一导电性部件；从z方向看时与半导体元件重叠的第二导电性部件；密封树脂,其覆盖半导体元件、引线框的一部分、第一导电性部件及第二导电性部件,配线层包括彼此隔开间隔的第一焊垫部和第二焊垫部,第二导电性部件包括与第一焊垫部接合的第一接合部(接合部(321))和与第二焊垫部接合的第二接合部(接合部(322))。(The invention provides a semiconductor device which can realize reduction of internal resistance. The semiconductor device of the present invention includes: a semiconductor element, comprising: a semiconductor substrate having a substrate main surface and a substrate back surface facing opposite sides to each other in a z direction, an element electrode formed on the substrate main surface, and a wiring layer formed on the substrate main surface and electrically connected to the element electrode; a lead frame supporting the semiconductor element from the back side of the substrate; a first conductive member for electrically connecting the semiconductor element and the lead frame; a second conductive member overlapping the semiconductor element when viewed from the z direction; and a sealing resin covering the semiconductor element, a part of the lead frame, the first conductive member, and the second conductive member, wherein the wiring layer includes a first pad portion and a second pad portion spaced apart from each other, and the second conductive member includes a first bonding portion (321)) bonded to the first pad portion and a second bonding portion (322)) bonded to the second pad portion.)

1. A semiconductor device, comprising:

A semiconductor element, comprising: a semiconductor substrate having a substrate main surface and a substrate back surface facing opposite sides to each other in a first direction; an element electrode formed on the main surface of the substrate; and a wiring layer formed on the substrate main surface and electrically connected to the element electrode;

A lead frame supporting the semiconductor element from a back surface side of the substrate;

A first conductive member for electrically connecting the semiconductor element to the lead frame;

A second conductive member overlapping with the semiconductor element when viewed in the first direction; and

A sealing resin covering the semiconductor element, a part of the lead frame, the first conductive member, and the second conductive member,

The wiring layer includes first and second pad portions spaced apart from each other,

The second conductive member includes a first engagement portion engaged with the first pad portion and a second engagement portion engaged with the second pad portion.

2. The semiconductor device according to claim 1, wherein:

The first conductive member and the second conductive member are spaced apart from each other by a gap when viewed in the first direction,

the second conductive member does not intersect with an outer periphery of the semiconductor element when viewed in the first direction.

3. The semiconductor device according to claim 1 or 2, characterized in that:

The wiring layer includes a third pad portion spaced apart from both the first pad portion and the second pad portion,

The first conductive member includes a third bonding portion bonded to the third pad portion and a fourth bonding portion bonded to the lead frame.

4. The semiconductor device according to claim 3, wherein:

The semiconductor element further includes a protective layer formed on the wiring layer,

The first, second, and third pad portions are exposed from the protective layer.

5. the semiconductor device according to claim 4, wherein:

The wiring layer includes a plurality of conductive layers spaced apart from each other in the first direction,

The semiconductor element further includes: an interlayer insulating film formed between the plurality of conductive layers and insulating the conductive layers from each other; and a plurality of via holes formed to penetrate the interlayer insulating film and to conduct the conductive layers to each other.

6. The semiconductor device according to claim 5, wherein:

the plurality of conductive layers includes: a first conductive layer covered with the protective layer and including the first pad portion, the second pad portion, and the third pad portion; and a second conductive layer arranged closer to the substrate main surface than the first conductive layer in the first direction.

7. The semiconductor device according to claim 6, wherein:

The first conductive layer has a plurality of first plate-like members each having a rectangular shape when viewed in the first direction,

The plurality of first plate-like members include the first pad portions and the second pad portions, respectively.

8. The semiconductor device according to claim 7, wherein:

The second conductive layer has a plurality of second plate-like members each having a rectangular shape when viewed in the first direction,

The number of first plate-like members is smaller than the number of second plate-like members.

9. The semiconductor device according to claim 8, wherein:

The longitudinal direction of each of the plurality of first plate-like members is orthogonal to the longitudinal direction of each of the plurality of second plate-like members.

10. The semiconductor device according to claim 9, wherein:

the plurality of conductive layers further includes a third conductive layer arranged closer to the substrate main surface than the second conductive layer in the first direction.

11. The semiconductor device according to claim 10, wherein:

The third conductive layer has a plurality of third plate-like members each having a rectangular shape when viewed in the first direction,

The number of the second plate-like members is smaller than the number of the third plate-like members.

12. The semiconductor device according to claim 11, wherein:

the longitudinal direction of each of the plurality of third plate-like members is orthogonal to the longitudinal direction of each of the plurality of second plate-like members.

13. The semiconductor device according to any one of claims 7 to 12, wherein:

The element electrodes include at least a first electrode and a second electrode,

The plurality of first plate-like members include a first electrode conduction member in conduction with the first electrode and a second electrode conduction member in conduction with the second electrode.

14. The semiconductor device according to any one of claims 1 to 13, wherein:

The second conductive member is a bonding wire having a circular cross section.

15. the semiconductor device according to claim 14, wherein:

The first conductive member is a bonding wire having a circular cross-section,

The first conductive member and the second conductive member have the same thickness.

16. The semiconductor device according to any one of claims 1 to 15, wherein:

The first conductive member and the second conductive member are mainly composed of aluminum.

17. The semiconductor device according to any one of claims 1 to 16, wherein:

The semiconductor element is a MOSFET.

18. The semiconductor device according to any one of claims 1 to 17, further comprising:

A control IC for controlling driving of the semiconductor element; and

And a third conductive member connecting the control IC and the lead frame.

19. the semiconductor device according to claim 18, wherein:

The third conductive member is thinner than the first conductive member.

20. A semiconductor device, comprising:

A semiconductor element, comprising: a semiconductor substrate having a substrate main surface and a substrate back surface facing opposite sides to each other in a first direction; an element electrode formed on the main surface of the substrate; and a wiring layer formed on the substrate main surface and electrically connected to the element electrode;

a lead frame supporting the semiconductor element from a back surface side of the substrate;

a conductive member for electrically connecting the semiconductor element and the lead frame; and

A sealing resin covering the semiconductor element, a part of the lead frame, and the conductive member,

The wiring layer includes a rectangular plate-like member joined to the conductive member and extending long in a second direction orthogonal to the first direction as viewed in the first direction,

The conductive member includes an engaging portion that engages with the plate-like member,

The engaging portion extends in a longitudinal direction of the plate-like member as viewed in the first direction, and overlaps a center of the plate-like member in the longitudinal direction as viewed in the first direction.

Technical Field

The present invention relates to a semiconductor device.

Background

Patent document 1 discloses a conventional semiconductor device. The semiconductor device described in patent document 1 includes a semiconductor substrate, an insulating film, a plurality of wiring layers, and bonding wires. The semiconductor substrate is made of, for example, silicon, and is a base of the device element. As the device element, an arbitrary transistor structure such as a MOS transistor structure can be applied. An insulating film is formed on the semiconductor substrate. The plurality of wiring layers are connected to the device elements. In the semiconductor device described in patent document 1, the plurality of wiring layers include a lower layer wiring portion, an upper layer wiring, and a copper wiring. The lower wiring portion and the upper wiring are covered with an insulating film. The copper wiring is a surface layer wiring exposed from the insulating film and is bonded to the bonding wire. The bonding wire is bonded to an edge portion of the surface layer wiring (copper wiring).

Disclosure of Invention

Problems to be solved by the invention

In the conventional semiconductor device configured as described above, the area of the surface layer wiring tends to increase as the element area of the device element increases. When the area of the surface layer wiring is increased, the current path of the current flowing through the surface layer wiring is extended, and thus the internal resistance of the semiconductor device is increased. This increase in internal resistance becomes a main cause of electrical loss.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device in which reduction in internal resistance is achieved.

Means for solving the problems

a first aspect of the present invention provides a semiconductor device comprising: a semiconductor element, comprising: a semiconductor substrate having a substrate main surface and a substrate back surface facing opposite sides to each other in a first direction; an element electrode formed on the main surface of the substrate; and a wiring layer formed on the substrate main surface and electrically connected to the element electrode; a lead frame supporting the semiconductor element from a back surface side of the substrate; a first conductive member for electrically connecting the semiconductor element to the lead frame; a second conductive member overlapping with the semiconductor element when viewed in the first direction; and a sealing resin covering the semiconductor element, a part of the lead frame, the first conductive member, and the second conductive member, the wiring layer including a first pad portion and a second pad portion spaced apart from each other, the second conductive member including a first bonding portion bonded to the first pad portion and a second bonding portion bonded to the second pad portion.

In a preferred embodiment of the semiconductor device, the first conductive member and the second conductive member are spaced apart from each other by a gap when viewed in the first direction, and the second conductive member does not intersect with an outer periphery of the semiconductor element when viewed in the first direction.

In a preferred embodiment of the semiconductor device, the wiring layer includes a third pad portion spaced apart from both the first pad portion and the second pad portion, and the first conductive member includes a third bonding portion bonded to the third pad portion and a fourth bonding portion bonded to the lead frame.

In a preferred embodiment of the semiconductor device, the semiconductor element further includes a protective layer formed on the wiring layer, and the first pad portion, the second pad portion, and the third pad portion are exposed from the protective layer.

In a preferred embodiment of the semiconductor device, the wiring layer includes a plurality of conductive layers spaced apart from each other in the first direction, and the semiconductor element further includes: an interlayer insulating film formed between the plurality of conductive layers and insulating the conductive layers from each other; and a plurality of via holes formed to penetrate the interlayer insulating film and to conduct the conductive layers to each other.

In a preferred embodiment of the semiconductor device, the plurality of conductive layers include: a first conductive layer covered with the protective layer and including the first pad portion, the second pad portion, and the third pad portion; and a second conductive layer arranged closer to the substrate main surface than the first conductive layer in the first direction.

In a preferred embodiment of the semiconductor device, the first conductive layer has a plurality of first plate-like members each having a rectangular shape when viewed in the first direction, and the plurality of first plate-like members include the first pad portions and the second pad portions, respectively.

In a preferred embodiment of the semiconductor device, the second conductive layer has a plurality of second plate-like members each having a rectangular shape when viewed in the first direction, and the number of the first plate-like members is smaller than the number of the second plate-like members.

In a preferred embodiment of the semiconductor device, a longitudinal direction of each of the plurality of first plate-like members is orthogonal to a longitudinal direction of each of the plurality of second plate-like members.

In a preferred embodiment of the semiconductor device, the plurality of conductive layers further includes a third conductive layer arranged closer to the substrate main surface than the second conductive layer in the first direction.

In a preferred embodiment of the semiconductor device, the third conductive layer has a plurality of third plate-like members each having a rectangular shape when viewed in the first direction, and the number of the second plate-like members is smaller than the number of the third plate-like members.

In a preferred embodiment of the semiconductor device, a longitudinal direction of each of the plurality of third plate-like members is orthogonal to a longitudinal direction of each of the plurality of second plate-like members.

In a preferred embodiment of the semiconductor device, the element electrode includes at least a first electrode and a second electrode, and the plurality of first plate-like members includes a first electrode conduction member that is in conduction with the first electrode and a second electrode conduction member that is in conduction with the second electrode.

In a preferred embodiment of the semiconductor device, the second conductive member is a bonding wire having a circular cross section.

In a preferred embodiment of the semiconductor device, the first conductive member is a bonding wire having a circular cross section, and the first conductive member and the second conductive member have the same thickness.

In a preferred embodiment of the semiconductor device, the first conductive member and the second conductive member are mainly composed of aluminum.

In a preferred embodiment of the semiconductor device, the semiconductor element is a MOSFET.

In a preferred embodiment of the semiconductor device, the semiconductor device further includes: a control IC for controlling driving of the semiconductor element; and a third conductive member connecting the control IC and the lead frame.

In a preferred embodiment of the semiconductor device, the third conductive member is thinner than the first conductive member.

A second aspect of the present invention provides a semiconductor device comprising: a semiconductor element, comprising: a semiconductor substrate having a substrate main surface and a substrate back surface facing opposite sides to each other in a first direction; an element electrode formed on the main surface of the substrate; and a wiring layer formed on the substrate main surface and electrically connected to the element electrode; a lead frame supporting the semiconductor element from a back surface side of the substrate; a conductive member for electrically connecting the semiconductor element and the lead frame; and a sealing resin covering the semiconductor element, a part of the lead frame, and the conductive member, wherein the wiring layer includes a rectangular plate-like member that is joined to the conductive member and extends long in a second direction orthogonal to the first direction when viewed in the first direction, and the conductive member includes a joining portion that is joined to the plate-like member, the joining portion extending in a longitudinal direction of the plate-like member when viewed in the first direction and overlapping a center of the plate-like member in the longitudinal direction when viewed in the first direction.

Effects of the invention

According to the semiconductor device of the present invention, reduction in internal resistance of the semiconductor device can be achieved.

Drawings

Fig. 1 is a plan view showing a semiconductor device of a first embodiment.

fig. 2 is a front view showing the semiconductor device of the first embodiment.

Fig. 3 is a side view showing the semiconductor device of the first embodiment.

fig. 4 is a plan view of fig. 1 with the sealing resin 5 omitted.

Fig. 5 is an enlarged view of a main portion of fig. 4.

Fig. 6 is a sectional view taken along line VI-VI of fig. 4.

Fig. 7 is a sectional view taken along line VII-VII of fig. 4.

Fig. 8 is an exploded perspective view for explaining the first semiconductor element.

Fig. 9 is a main portion enlarged sectional view of an enlarged portion of fig. 6.

Fig. 10 is a plan view showing a semiconductor device of the second embodiment (sealing resin is omitted).

Fig. 11 is a plan view showing a semiconductor device of the third embodiment (sealing resin is omitted).

Fig. 12 is a plan view showing a semiconductor device of the fourth embodiment (sealing resin is omitted).

Fig. 13 is a plan view showing a semiconductor device of the fifth embodiment (sealing resin is omitted).

Fig. 14 is a plan view showing a semiconductor device according to a sixth embodiment (sealing resin is omitted).

Fig. 15 is a plan view showing a semiconductor device of the seventh embodiment (sealing resin is omitted).

Fig. 16 is a plan view (1 thereof) for explaining a terminal arrangement of the semiconductor device of the present invention.

Fig. 17 is a plan view (2 thereof) for explaining a terminal arrangement of the semiconductor device of the present invention.

fig. 18 is a plan view for explaining a terminal arrangement of the semiconductor device of the present invention (fig. 3 thereof).

fig. 19 is a plan view for explaining a terminal arrangement of the semiconductor device of the present invention (4 thereof).

Fig. 20 is a plan view for explaining a terminal configuration of the semiconductor device of the present invention (fig. 5 thereof).

Fig. 21 shows an example of a circuit diagram of the semiconductor device of the present invention.

Fig. 22 is a perspective view showing a semiconductor device according to a modification of the present invention.

Description of the reference numerals

A1-A7: semiconductor device with a plurality of transistors

1, 1A, 1B: first semiconductor element

11: semiconductor substrate

111: main surface of the substrate

112: back side of substrate

12: element electrode

121: a first electrode

122: second electrode

123: third electrode

13: wiring layer

14: first conductive layer

141: first plate-like member

141 a: first electrode conducting part

141 b: second electrode conducting part

142: pad part

142 a: first pad portion

142 b: second pad portion

142 c: third pad portion

15: second conductive layer

151: second plate-like member

151 a: first electrode conducting part

151 b: second electrode conducting part

16: third conductive layer

161: third plate-like member

161 a: first electrode conducting part

161 b: second electrode conducting part

161 c: third electrode conducting part

17: insulating layer

171: first interlayer insulating film

172: second interlayer insulating film

173: third interlayer insulating film

18: conducting hole

181: first via hole

182: second via hole

183: third via hole

19: protective layer

2: second semiconductor element

21: element main surface

211: pad part

22: element back surface

3: conductive member

31: first conductive member

311: joint (third joint)

312: joint (fourth joint)

32: second conductive member

32 a: end part

321: joint (first joint)

322: joint (second joint)

33: third conductive member

331: joint part

332: joint part

4: lead frame

41: bare pad portion

411: bonding material

42, 42a to 42 e: bonding pad portion

421 a: projection part

421 b: projection part

43, 43a to 43 f: lead wire part

44: side extension part

5: and (4) sealing the resin.

Detailed Description

Preferred embodiments of the semiconductor device of the present invention will be described below with reference to the drawings.

[ first embodiment ]

Fig. 1 to 7 show a semiconductor device according to a first embodiment. The semiconductor device a1 of the first embodiment includes a plurality of first semiconductor elements 1, second semiconductor elements 2, a plurality of first conductive members 31, a plurality of second conductive members 32, a plurality of third conductive members 33, a lead frame 4, and a sealing resin 5.

Fig. 1 is a plan view showing a semiconductor device a 1. Fig. 2 is a front view showing a semiconductor device a 1. Fig. 3 is a side view showing a semiconductor device a 1. Fig. 4 is a plan view of fig. 1 with the sealing resin 5 omitted. In the figure, the sealing resin 5 is indicated by a virtual line (two-dot chain line). Fig. 5 is an enlarged view of a main portion of fig. 4. Fig. 6 is a sectional view taken along line VI-VI of fig. 4. Fig. 7 is a sectional view taken along line VII-VII of fig. 4. For convenience of explanation, three directions orthogonal to each other are defined as an x direction, a y direction, and a z direction. The z direction is the thickness direction of the semiconductor device a 1. The x direction is a left-right direction of the plan view (see fig. 1) of the semiconductor device a 1. The y direction is the up-down direction of the plan view (see fig. 1) of the semiconductor device a 1. The z-direction and the y-direction correspond to the "first direction" and the "second direction" described in the claims.

The semiconductor device a1 is a device in a form of surface-mounted on a circuit board of various electronic apparatuses and the like. In this embodiment, the semiconductor device a1 is a semiconductor Package called an SOP (Small Outline Package). The semiconductor device a1 is, for example, a power supply IC in this embodiment, but is not limited thereto.

The plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2 are elements that become functional centers (key parts) of the semiconductor device a 1. Each of the plurality of first semiconductor elements 1 is a power semiconductor element. In the present embodiment, each first semiconductor element 1 is, for example, a lateral MOSFET. Each first semiconductor element 1 is not limited to a MOSFET. In this embodiment mode, the semiconductor device a1 includes two first semiconductor elements 1. For convenience of understanding, the two first semiconductor elements 1 may be referred to as first semiconductor elements 1A and first semiconductor elements 1B, respectively. Two first semiconductor elements 1A, 1B are arranged side by side in the x direction, and the first semiconductor element 1B is sandwiched by the first semiconductor element 1A and the second semiconductor element 2. The second semiconductor element 2 is a control IC for controlling the driving of the plurality of first semiconductor elements 1. The second semiconductor element 2 is electrically connected to each of the first semiconductor elements 1, and controls each of the first semiconductor elements 1. The plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2 are each rectangular in shape when viewed in the z direction (hereinafter, also referred to as "plan view"). The entirety of the plurality of first semiconductor elements 1 and the second semiconductor elements 2 has a rectangular shape in a plan view. Therefore, the y-direction dimensions of the plurality of first semiconductor elements 1 and the y-direction dimensions of the second semiconductor elements 2 are substantially the same. In addition, when the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2 are added together, the dimension in the x direction is about 3mm, and the dimension in the y direction is about 2 mm.

each of the first semiconductor elements 1 includes a semiconductor substrate 11, a plurality of element electrodes 12, a wiring layer 13, an insulating layer 17, a plurality of via holes 18, and a protective layer 19. In addition, the semiconductor substrate 11 may be shared by the first semiconductor elements 1A and 1B. Fig. 8 and 9 are diagrams for explaining the detailed structure of the first semiconductor element 1. Fig. 8 is an exploded perspective view for explaining the wiring layer 13, the insulating layer 17, and the plurality of via holes 18 of the plurality of first semiconductor elements 1. In the figure, the plurality of element electrodes 12, a part of the insulating layer 17, and the protective layer 19 are omitted. Fig. 9 is a main portion enlarged sectional view of a part of the sectional view shown in fig. 6.

the semiconductor substrate 11 is made of a semiconductor material. Examples of the semiconductor material include Si (silicon), SiC (silicon carbide), GaN (gallium nitride), and the like. In the present embodiment, one of the two first semiconductor elements 1 (the first semiconductor element 1A) is an n-type channel MOSFET, and the other of the two first semiconductor elements 1 (the first semiconductor element 1B) is a p-type channel MOSFET. As shown in fig. 9, the semiconductor substrate 11 has a substrate main surface 111 and a substrate rear surface 112 facing opposite sides to each other in the z direction.

As shown in fig. 9, the plurality of element electrodes 12 are formed so as to be exposed from the substrate main surface 111 of the semiconductor substrate 11. In the present embodiment, each of the first semiconductor elements 1 includes the first electrode 121, the second electrode 122, and the third electrode 123 as the plurality of element electrodes 12. In this embodiment, the first electrode 121 is a drain electrode, the second electrode 122 is a source electrode, and the third electrode 123 is a gate electrode. The arrangement of the first electrode 121, the second electrode 122, and the third electrode 123 in a plan view is not particularly limited, and the rectangular element electrodes 12 may be arranged in a grid pattern or may be arranged in a row in the x direction or the y direction.

As shown in fig. 9, the wiring layer 13 is formed on the substrate main surface 111 of the semiconductor substrate 11 and is electrically connected to the plurality of element electrodes 12. The wiring layer 13 includes a first conductive layer 14, a second conductive layer 15, and a third conductive layer 16, respectively, spaced apart from each other in the z direction with respect to each first semiconductor element 1. The number of the conductive layers of the wiring layer 13 is not limited to three. The first, second and third conductive layers 14, 15 and 16 are insulated from each other by an insulating layer 17.

As shown in fig. 9, the first conductive layer 14 is an outer layer of the wiring layer 13, and is located in a direction facing the substrate main surface 111 with respect to the second conductive layer 15 and the third conductive layer 16. The first conductive layer 14 includes a plurality of first plate-like members (sheet-like members) 141.

Each of the first plate-like members 141 is made of a conductive material. The conductive material is, for example, Al (aluminum) or Cu (copper). In the present embodiment, the material of each first plate-like member 141 is Al. Each first plate-like member 141 has a rectangular shape with its longitudinal direction along the y-direction in plan view. The width (dimension in the width direction) of each first plate-like member 141 is, for example, about 150 μm. The thickness (dimension in the z direction) of each first plate-like member 141 is, for example, about 3 μm. The plurality of first plate-like members 141 are arranged side by side in the x direction in a plan view. Note that, for ease of understanding, in fig. 4 and 5, the first plate-like members 141 adjacent in the x direction are illustrated so as to be in contact with each other, but the insulating layer 17 is formed between the adjacent first plate-like members 141. Thus, in the first conductive layer 14, the plurality of first plate-like members 141 are insulated from each other by the insulating layer 17. As shown in fig. 5, each of the first plate-like members 141 includes a first pad portion 142a, a second pad portion 142b, and a third pad portion 142c, respectively, exposed from the protective layer 19. For ease of understanding, in fig. 8, the first, second, and third pad portions 142a, 142b, and 142c are hatched.

The first, second, and third pad portions 142a, 142b, and 142c are arranged in the same plane of each first plate-like member 141. The first, second, and third pad portions 142a, 142b, and 142c are spaced apart from each other in each first plate-like member 141 and are arranged in the y-direction. In the present embodiment, the second pad portion 142b is disposed between the first pad portion 142a and the third pad portion 142 c. The first pad portion 142a is joined to one end (a joint portion 321 described later) of the second conductive member 32. The second pad portion 142b is joined to the other end (a joint portion 322 described later) of the second conductive member 32. The third pad portion 142c is joined to one end (a joint portion 311 described later) of the first conductive member 31.

As shown in fig. 9, the second conductive layer 15 is an intermediate layer of the wiring layer 13, and is disposed between the first conductive layer 14 and the third conductive layer 16. The second conductive layer 15 includes a plurality of second plate-like members 151.

Each of the second plate-like members 151 is made of a conductive material. The conductive material is, for example, Al or Cu. In the present embodiment, the material of each second plate-like member 151 is Al. Each second plate-like member 151 has a rectangular shape with its longitudinal direction along the x-direction in plan view. The width (dimension in the width direction) of each second plate-like member 151 is, for example, about 30 μm. The thickness (z-direction dimension) of each second plate-like member 151 is, for example, about 0.5 μm. The plurality of second plate-like members 151 are arranged in the y direction in a plan view, and the insulating layer 17 is formed between the second plate-like members 151 adjacent in the y direction. Thus, in the second conductive layer 15, the plurality of second plate-like members 151 are insulated from each other by the insulating layer 17.

as shown in fig. 9, the third conductive layer 16 is an inner layer of the wiring layer 13, is located in a direction toward the substrate back surface 112 with respect to the first conductive layer 14 and the second conductive layer 15, and is arranged closer to the substrate main surface 111 than the first conductive layer 14 and the second conductive layer 15. Third conductive layer 16 includes a plurality of third plate members 161.

The plurality of third plate members 161 are each made of a conductive material. The conductive material is, for example, Al or Cu. In the present embodiment, the raw material of each third plate-like member 161 is Al. Each third plate-like member 161 has a rectangular shape with its longitudinal direction along the y-direction in plan view. The width (dimension in the width direction) of each third plate-like member 161 is, for example, about 1.0 μm. The thickness (z-direction dimension) of each third plate-like member 161 is, for example, about 0.5 μm. The plurality of third plate members 161 are arranged in the x direction in a plan view, and the insulating layer 17 is formed between the third plate members 161 adjacent in the x direction. Thus, in the third conductive layer 16, the plurality of third plate-like members 161 are insulated from each other by the insulating layer 17. In the present embodiment, the plurality of third plate-like members 161 are arranged at a pitch of about 0.6 μm in the x direction.

in the wiring layer 13, the number of first plate-like members 141 is smaller than the number of second plate-like members 151, and the number of second plate-like members 151 is smaller than the number of third plate-like members 161. In addition, the number of the third plate-like members 161 is smaller than the number of the element electrodes 12. In the wiring layer 13, the third conductive layer 16 and the second conductive layer 15 collect the plurality of element electrodes 12 and are electrically connected to the first conductive layer 14 on the upper layer.

In the wiring layer 13, as shown in fig. 8, the longitudinal direction of each first plate-like member 141 and the longitudinal direction of each second plate-like member 151 are orthogonal to each other on a plane (x-y plane) orthogonal to the z-direction, and the longitudinal direction of each second plate-like member 151 and the longitudinal direction of each third plate-like member 161 are orthogonal to each other on the x-y plane.

In the wiring layer 13, the plurality of first plate-like members 141 include: a first electrode conduction part 141a conducting with the first electrode 121; and a second electrode conduction part 141b in conduction with the second electrode 122. The first electrode conduction parts 141a and the second electrode conduction parts 141b are alternately arranged in the x direction. In this embodiment, as shown in fig. 5, the first conductive layer 14 includes three first electrode conduction parts 141A that are in conduction with the first electrode 121 of the first semiconductor element 1A, and includes four first electrode conduction parts 141A that are in conduction with the first electrode 121 of the first semiconductor element 1B. In addition, the first conductive layer 14 includes four second electrode conduction parts 141B that are in conduction with the second electrode 122 of the first semiconductor element 1A, and includes four second electrode conduction parts 141B that are in conduction with the second electrode 122 of the first semiconductor element 1B. In the present embodiment, the first electrode conduction member 141a and the second electrode conduction member 141b of each first plate-like member 141 correspond to a "first electrode conduction member" and a "second electrode conduction member" described in the claims, respectively.

Similarly, the plurality of second plate-like members 151 include a first electrode conduction member 151a conducting with the first electrode 121 and a second electrode conduction member 151b conducting with the second electrode 122. The first electrode conduction parts 151a and the second electrode conduction parts 151b are alternately arranged in the y direction. In addition, the plurality of third plate-shaped members 161 include a first electrode conduction member 161a that is conducted with the first electrode 121 and a second electrode conduction member 161b that is conducted with the second electrode 122. And, the plurality of third plate members 161 includes a third electrode conduction member 161c which conducts with the third electrode 123. The third electrode conduction part 161c is disposed between the adjacent first electrode conduction part 161a and second electrode conduction part 161 b.

As shown in fig. 9, an insulating layer 17 is formed between the first conductive layer 14 and the semiconductor substrate 11 (substrate main surface 111). The material of the insulating layer 17 is not particularly limited as long as it has insulating properties, and is made of, for example, SiO₂And (4) forming. The insulating layer 17 includes a first interlayer insulating film 171, a second interlayer insulating film 172, and a third interlayer insulating film 173. The first interlayer insulating film 171 is formed between the first conductive layer 14 and the second conductive layer 15 to insulate them. The second interlayer insulating film 172 is formed between the second conductive layer 15 and the third conductive layer 16 to insulate them. The third interlayer insulating film 173 is formed between the third conductive layer 16 and the semiconductor substrate 11 (substrate main surface 111) to insulate the third conductive layer 16 from each element electrode 12. The insulating layer 17 is also formed between the first plate-like members 141 adjacent in the x direction in the first conductive layer 14, between the second plate-like members 151 adjacent in the y direction in the second conductive layer 15, and between the third plate-like members 161 adjacent in the x direction in the third conductive layer 16. In addition, in the figuresIn 8, the insulating layer 17 formed therebetween is omitted.

Each of the plurality of via holes (via)18 is composed of a through hole penetrating the insulating layer 17 and a conductive material filling the through hole. The conductive material of this embodiment is, for example, W (tungsten). The material of each via hole 18 is not limited to this, and may be aluminum, copper, or the like. The conductive material may be formed so as to cover the inner surface of the through hole, instead of filling the through hole. Each via 18 extends in the z-direction. In the present embodiment, as shown in fig. 8, each via hole 18 has a circular shape in a plan view. The shape of each via hole 18 in a plan view is not limited to this, and may be, for example, a rectangular shape, a polygonal shape, or the like. In the present embodiment, the plurality of via holes 18 include a plurality of first via holes 181, a plurality of second via holes 182, and a plurality of third via holes 183.

as shown in fig. 8 and 9, the plurality of first via holes 181 penetrate the first interlayer insulating film 171 and are formed between the first conductive layer 14 and the second conductive layer 15. Each first via hole 181 conducts the first conductive layer 14 and the second conductive layer 15. The arrangement of the plurality of first via holes 181 is not particularly limited, and may be appropriately designed based on the arrangement of the plurality of first plate-like members 141 of the first conductive layer 14 and the plurality of second plate-like members 151 of the second conductive layer 15.

As shown in fig. 8 and 9, the plurality of second via holes 182 penetrate the second interlayer insulating film 172 and are formed between the second conductive layer 15 and the third conductive layer 16. Each second via hole 182 conducts the second conductive layer 15 and the third conductive layer 16. The arrangement of the plurality of second via holes 182 is not particularly limited, and may be appropriately designed based on the arrangement of the plurality of second plate-like members 151 of the second conductive layer 15 and the plurality of third plate-like members 161 of the third conductive layer 16.

As shown in fig. 8 and 9, the plurality of third via holes 183 each penetrate the third interlayer insulating film 173 and are formed between the third conductive layer 16 and the element electrode 12. Each third via hole 183 conducts the third conductive layer 16 and the element electrode 12. The arrangement of the plurality of third via holes 183 is not particularly limited, and may be appropriately designed based on the arrangement of the plurality of third plate-like members 161 and the plurality of element electrodes 12 of the third conductive layer 16.

As shown in fig. 9, the protective layer 19 is formed so as to cover the upper surface of the wiring layer 13 (first conductive layer 14). The protective layer 19 is, for example, Si formed by a plasma CVD method₃N₄Layer, SiO₂A layer, or a polyimide resin layer formed by coating. Alternatively, they may be formed by a combination thereof. In the present embodiment, a portion of the protective layer 19 is opened, and the first pad portion 142a, the second pad portion 142b, and the third pad portion 142c are exposed from the opened portion, respectively.

The second semiconductor element 2 has an element principal surface 21 and an element back surface 22 facing opposite sides to each other in the z direction. The element main surface 21 and the substrate main surface 111 of the semiconductor substrate 11 face in the same direction. The element rear surface 22 faces the substrate rear surface 112 of the semiconductor substrate 11 in the same direction. As shown in fig. 5, the second semiconductor element 2 has a plurality of pad portions 211 formed on the element main surface 21. The pad portion 211 is a portion to which the third conductive member 33 is joined.

each of the first conductive members 31 is a member for electrically connecting any one of the first semiconductor elements 1 to the lead frame 4. Each first conductive member 31 intersects with the outer periphery of any of the plurality of first semiconductor elements 1 in a plan view. Each first conductive member 31 includes a bonding portion 311 bonded to the third pad portions 142c of the plurality of first semiconductor elements 1, and a bonding portion 312 bonded to a part of the lead frame 4 (a bonding pad portion 42 described later). Each first conductive member 31 is formed using, for example, a wedge tool, and the joint portions 311 and 312 are formed by wedge bonding (wedge bonding) using the wedge tool. Further, the lengthwise dimension of the engaging portions 311, 312 depends on the wedge tool used. In the present embodiment, the joint portion 311 corresponds to the "third joint portion" described in the claims, and the joint portion 312 corresponds to the "fourth joint portion" described in the claims.

each of the plurality of second conductive members 32 overlaps with any one of the plurality of first semiconductor elements 1 in a plan view. Therefore, each of the second conductive members 32 does not intersect with the outer periphery of any of the plurality of first semiconductor elements 1 in a plan view. Each second conductive member 32 is formed linearly along the longitudinal direction of the first plate-like member 141. In the present embodiment, as shown in fig. 4, the length of each second conductive member 32 in a plan view is about half of the longitudinal dimension of the first plate-like member 141. The length of each second conductive member 32 in the plan view is not limited to this, and may be longer than half the longitudinal dimension of the first plate-like member 141. Each second conductive member 32 includes a joint portion 321 joined to the first pad portions 142a of the plurality of first semiconductor elements 1, and a joint portion 322 joined to the second pad portions 142b of the plurality of first semiconductor elements 1. Each second conductive member 32 is formed by wedge bonding using a wedge tool, for example, and the bonding portions 321 and 322 are formed by wedge bonding using the wedge tool. Furthermore, the lengthwise dimension of the engagement portions 321, 322 depends on the wedge tool used. In the present embodiment, the joint 321 corresponds to the "first joint" described in the claims, and the joint 322 corresponds to the "second joint" described in the claims.

As shown in fig. 4 and 7, each second conductive member 32 has two end portions 32 a. The two end portions 32a are the respective endmost edges in the axial direction of the second conductive members 32. Each end portion 32a overlaps with the first pad portion 142a or the second pad portion 142 b. In the present embodiment, each end portion 32a is included in the joint portions 321, 322.

Each of the third conductive members 33 is a member for electrically connecting the second semiconductor element 2 and the lead frame 4. Each third conductive member 33 intersects the outer periphery of the second semiconductor element 2 in plan view. Each third conductive member 33 includes a bonding portion 331 bonded to the pad portion 211 of the second semiconductor element 2, and a bonding portion 332 bonded to a part of the lead frame 4 (a bonding pad portion 42 described later). Each third conductive member 33 is formed by wedge bonding using a wedge tool, for example, and the bonding portions 331 and 332 are formed by wedge bonding using the wedge tool. Further, the lengthwise dimension of the engaging portions 331, 332 depends on the wedge tool used.

In the present embodiment, each of the first conductive members 31, each of the second conductive members 32, and each of the third conductive members 33 is a so-called bonding wire (bonding wire),And is a linear member having a circular cross section. The present invention is not limited to a linear member, and may be a Ribbon-shaped member called a Ribbon wire (Ribbon wire). The linear member is made of Al as a main component of the material. That is, in the present embodiment, each of the first conductive members 31, each of the second conductive members 32, and each of the third conductive members 33 is an Al wire. The material of each of the first conductive members 31, the second conductive members 32, and the third conductive members 33 is not limited to this, and may be, for example, Cu or Au. In the present embodiment, the thicknesses (wire diameters) of all the first conductive member 31, the second conductive member 32, and the third conductive member 33 are set to be equal to each otherLeft and right.

The lead frame 4 is a portion constituting a conductive path between the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2 and a circuit board for mounting the semiconductor device a 1. The lead frame 4 supports the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2, and is in conduction with the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2. The lead frame 4 is formed by punching, shearing, bending, or the like from a thin metal plate of Cu or the like having a rectangular shape in plan view. Therefore, the main component of the material of the lead frame 4 is Cu. The material of the lead frame 4 is not limited to this. The lead frame 4 includes a die pad portion 41, a plurality of bonding pad portions 42a, 42b, 42c, 42d, a plurality of lead portions 43a, 43b, 43c, 43d, and a plurality of side extension portions 44. For convenience of explanation, the bonding pad portions 42 will be described as the bonding pad portions 42 without particularly distinguishing the plurality of bonding pad portions 42a to 42 d. Similarly, the lead portions 43 will be described as the lead portions 43 without particularly distinguishing the lead portions 43a to 43 d.

the die pad portion 41 is a portion on which the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2 are mounted. The plurality of first semiconductor elements 1 and second semiconductor elements 2 are bonded to the die pad portions 41 through the bonding material 411. The bonding material 411 is, for example, solder paste, Ag paste, or the like. The material of the bonding material 411 is not particularly limited.

each of the bonding pad portions 42a to 42d is a portion for bonding any one of the first conductive member 31, the second conductive member 32, and the third conductive member 33. The bonding pad portions 42a to 42d are arranged at intervals. In the present embodiment, each of the bonding pad portions 42a to 42d is arranged to be spaced apart from the pad portion 41. Further, any one of the plurality of bonding pad portions 42a to 42d and the die pad portion 41 may be formed integrally. In this case, the lead frame 4 may not include the plurality of side extensions 44. In the present embodiment, each of the bonding pad portions 42a to 42d has a rectangular shape in plan view.

The bonding pad portion 42a is electrically connected to the second electrode 122 of the first semiconductor element 1A via the first conductive member 31. Three lead portions 43a are connected to the bonding pad portion 42 a.

The bonding pad portion 42B is electrically connected to the second electrode 122 of the first semiconductor element 1B via the first conductive member 31. Three lead portions 43b are connected to the bonding pad portion 42 b.

the bonding pad portion 42c is electrically connected to each first electrode 121 of each first semiconductor element 1A, 1B via the first conductive member 31. Five lead portions 43c are connected to the bonding pad portion 42 c.

The plurality of bonding pad portions 42d are electrically connected to the second semiconductor element 2 through the third conductive members 33, respectively. One lead portion 43d is connected to each bonding pad portion 42 d.

As shown in fig. 4, each of the lead portions 43a to 43d is connected to one of the bonding pad portions 42a to 42d and extends from the bonding pad portion 42a to 42 d. Each lead portion 43 is partially exposed from the sealing resin 5, and the exposed portion from the sealing resin 5 is a terminal for mounting the semiconductor device a1 on a circuit board. At least the portion of each lead portion 43 exposed from the sealing resin 5 is covered by plating. Each lead portion 43 is bent at a portion exposed from the sealing resin 5. In the present embodiment, the eight lead portions 43 are exposed from the respective edges of the sealing resin 5 in the y direction in a plan view. The arrangement and number of the plurality of lead portions 43 are not limited to those shown in fig. 1 and 4.

The lead portions 43a are connected to the bonding pad portions 42a, respectively. As described above, since the bonding pad portion 42a is electrically connected to the second electrode 122 of the first semiconductor element 1A, and the second electrode 122 is a source electrode, the plurality of lead portions 43a are source terminals of the first semiconductor element 1A.

the lead portions 43b are connected to the bonding pad portions 42b, respectively. As described above, since the bonding pad portion 42B is electrically connected to the second electrode 122 of the first semiconductor element 1B, and the second electrode 122 is a source electrode, the plurality of lead portions 43B are source terminals of the first semiconductor element 1B.

The lead portions 43c are connected to the bonding pad portions 42c, respectively. As described above, since the bonding pad portion 42c is electrically connected to each first electrode 121 of each first semiconductor element 1A, 1B, and each first electrode 121 is a drain electrode, the plurality of lead portions 43c are drain terminals of each first semiconductor element 1. In the present embodiment, the drain terminals of the first semiconductor elements 1A and 1B are shared by the bonding pad portion 42c and the plurality of lead portions 43c, but the drain terminals of the first semiconductor elements 1A and 1B may be provided separately.

Each of the plurality of lead portions 43d is connected to each of the bonding pad portions 42 d. As described above, each of the bonding pad portions 42d is electrically connected to the second semiconductor element 2. The lead portions 43d are appropriately electrically connected to the second semiconductor element 2 so as to function as, for example, a Power grid (Power grid) terminal, a device control terminal, an analog Power supply input terminal, a feedback terminal, a soft start time setting terminal, a spectrum spread setting terminal, a mode switching terminal, an internal constant voltage control terminal, an ERAMP output terminal, or the like. These terminals are merely examples, and may be electrically connected to the second semiconductor element 2 so as to function as other terminals. Although not shown in fig. 4 and 5, in the present embodiment, the third electrode 123 of each first semiconductor element 1 is electrically connected to the second semiconductor element 2.

Each of the plurality of side extending portions 44 is a portion extending from the x-direction end edge of the pad portion 41. One end edge in the x direction of each side extending portion 44 is connected to the pad portion 41, and the other end edge in the x direction is exposed from the sealing resin 5. In the present embodiment, two side extending portions 44 extend from each end edge of the pad portion 41 in the x direction in a plan view, and the two side extending portions 44 are disposed on each end edge side of the pad portion 41 in the y direction.

As shown in fig. 1 to 7, the sealing resin 5 covers the plurality of first semiconductor elements 1, the second semiconductor elements 2, the plurality of first conductive members 31, the plurality of second conductive members 32, the plurality of third conductive members 33, and a part of the lead frame 4. The sealing resin 5 is made of a material having insulating properties. In the present embodiment, the sealing resin 5 is made of, for example, black epoxy resin. The sealing resin 5 has a rectangular shape in plan view.

Next, the operation and effect of the semiconductor device a1 according to the first embodiment will be described.

According to the semiconductor device a1, the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes the first pad parts 142a and the second pad parts 142 b. In addition, the second conductive member 32 includes the joint portion 321 joined to the first pad portion 142a and the joint portion 322 joined to the second pad portion 142 b. With this configuration, a current path through the second conductive member 32 can be ensured between the first pad portion 142a and the second pad portion 142 b. Therefore, the second conductive member 32 can serve as a bypass path for the current flowing through the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 1.

According to the semiconductor device a1, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141. Also, first and second pad portions 142a and 142b are included in each first plate-like member 141. With this configuration, a current path passing through the inside of each first plate-like member 141 and a current path passing through the second conductive member 32 can be ensured between the first pad portion 142a and the second pad portion 142 b. In particular, since the wiring resistance of the second conductive member 32 is smaller than that of the first plate-like member 141, the second conductive member 32 serves as a bypass path for the current flowing between the first pad portion 142a and the second pad portion 142 b. Therefore, since the wiring resistance of each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device a1 can be reduced. For example, the wiring resistance of one first plate-like member 141 is 11m Ω, and the first conductive layer 14 includes 10 first plate-like members 141. Thus, the wiring resistance of first conductive layer 14 is 110m Ω (═ 11[ m Ω ] × 10[ s ]). At this time, the second conductive member 32 having a wiring resistance of 2m Ω bypasses between the first pad portion 142a and the second pad portion 142b of the first plate-like member 131, and the wiring resistance of 110m Ω and the wiring resistance of 2m Ω are connected in parallel, and as a result, the wiring resistance of the first conductive layer 14 becomes 1.96m Ω. Thus, the internal resistance of the semiconductor device a1 decreases. Further, as the length of the second conductive member 32 in a plan view becomes longer, a bypass path having a low resistance can be secured, and thus the wiring resistance can be further reduced.

According to the semiconductor device a1, the wiring layer 13 includes three conductive layers (the first conductive layer 14, the second conductive layer 15, and the third conductive layer 16), and the plurality of element electrodes 12 are collected by these conductive layers. For example, in the wiring layer 13, more conductive layers may be stacked, but in this case, the current path from the plurality of element electrodes 12 to the first conductive layer 14 (surface layer) becomes longer. Therefore, by configuring the wiring layer 13 to have a structure in which the first conductive layer 14, the second conductive layer 15, and the third conductive layer 16 are stacked as in the semiconductor device a1, the current path from the plurality of element electrodes 12 to the first conductive layer 14 (surface layer) can be made relatively short. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 1.

according to the semiconductor device a1, the first conductive member 31, the second conductive member 32, and the third conductive member 33 are bonding wires of the same thickness. According to this structure, the first conductive member 31, the second conductive member 32, and the third conductive member 33 can all be joined by wedge bonding using the same bonding tool (wedge tool). Therefore, it is not necessary to prepare a plurality of bonding tools for bonding different wire diameters. This can improve the efficiency of manufacturing the semiconductor device a 1.

According to the semiconductor device a1, the plurality of lead portions 43a are connected to the bonding pad portions 42a, and the plurality of first conductive members 31 are bonded thereto. Further, a plurality of lead portions 43b are connected to the bonding pad portion 42b, and a plurality of first conductive members 31 are bonded thereto. Further, a plurality of lead portions 43c are connected to the bonding pad portion 42c, and a plurality of first conductive members 31 are bonded thereto. In the present embodiment, the lead portions 43a function as the source terminals of the first semiconductor element 1A, the lead portions 43B function as the source terminals of the first semiconductor element 1B, and the lead portions 43c function as the drain terminals common to the first semiconductor elements 1A and 1B. Therefore, in the semiconductor device a1, a relatively large current can flow between the drain and the source of each first semiconductor element 1.

Fig. 10 to 21 show other embodiments of the semiconductor device of the present invention. In the drawings, the same or similar elements as those of the above-described embodiment are denoted by the same reference numerals as those of the above-described embodiment.

[ second embodiment ]

fig. 10 shows a semiconductor device of a second embodiment. Fig. 10 is a plan view showing a semiconductor device a2 according to a second embodiment, and corresponds to fig. 4 according to the first embodiment. The semiconductor device a2 is different in thickness between the first conductive members 31 and the second conductive members 32 mainly from the semiconductor device a 1.

In the present embodiment, the first conductive members 31 and the second conductive members 32 have the same thicknessLeft and right. Therefore, each of the first conductive members 31 and each of the second conductive members 32 of the present embodiment is thicker than each of the first conductive members 31 and each of the second conductive members 32 of the semiconductor device a 1. Each third conductive member 33 of the present embodiment is the same as each third conductive member 33 of the semiconductor device a 1. Therefore, the thickness of each third conductive member 33 is set to beLeft and right.

in the first conductive layer 14 of the present embodiment, the width of each first plate-like member 141 is about 400 μm larger than the width of each first plate-like member 141 of the semiconductor device a 1. In the present embodiment, as shown in fig. 10, the first conductive layer 14 includes six first plate-like members 141. Therefore, the number of the first plate-like members 141 of the present embodiment is smaller than the number of the first plate-like members 141 of the semiconductor device a 1. In the present embodiment, as the six first plate-like members 141, one first electrode conduction member 141a and two second electrode conduction members 141b are provided for each of the first semiconductor elements 1.

the semiconductor device a2 has the following structure, similarly to the semiconductor device a 1. This structure is such that the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes a first pad portion 142a and a second pad portion 142 b. In addition, the second conductive member 32 includes the joint portion 321 joined to the first pad portion 142a and the joint portion 322 joined to the second pad portion 142 b. With this configuration, a current path through the second conductive member 32 can be ensured between the first pad portion 142a and the second pad portion 142 b. Therefore, the second conductive member 32 can serve as a bypass path for the current flowing through the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 2.

According to the semiconductor device a2, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141, as with the semiconductor device a 1. Also, first and second pad portions 142a and 142b are included in each first plate-like member 141. Therefore, similarly to the semiconductor device a1, since the wiring resistance of each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device a2 can be reduced.

According to the semiconductor device a2, the number of the first conductive members 31 and the second conductive members 32 is smaller than the number of the first conductive members 31 and the second conductive members 32 of the semiconductor device a 1. Therefore, a bonding failure of the first conductive member 31 or the second conductive member 32 is more easily confirmed than in the semiconductor device a 1.

According to the semiconductor device a2, the width of each first plate-like member 141 is larger than that of each first plate-like member 141 of the first embodiment. With this configuration, the width of the pad portions 142 of the first plate-like members 141 can be increased. Therefore, the wire diameters of the first conductive members 31 and the second conductive members 32 of the semiconductor device a2 can be made larger than the wire diameters of the first conductive members 31 and the second conductive members 32 of the first embodiment. This can reduce the wiring resistance of each of the first conductive members 31 and the second conductive members 32. However, since the larger the width of the first plate-like member 141 is, the larger the plan view size of the first semiconductor element 1 is, it is preferable that the first plate-like member 141 having a relatively small width is constituted as in the case of the semiconductor device a1 when the first semiconductor element 1 having a relatively small plan view size is used.

According to the semiconductor device a2, the wire diameters of the first conductive member 31 and the second conductive member 32 are larger than those of the first conductive member 31 and the second conductive member 32 of the semiconductor device a 1. That is, the first conductive member 31 and the second conductive member 32 of the semiconductor device a2 are thicker than the first conductive member 31 and the second conductive member 32 of the semiconductor device a 1. Therefore, in the semiconductor device a2, the occurrence of cracks in the neck portions of the first conductive member 31 and the second conductive member 32 can be suppressed as compared with the semiconductor device a 1.

[ third embodiment ]

Fig. 11 shows a semiconductor device of a third embodiment. Fig. 12 is a plan view showing a semiconductor device a3 according to a third embodiment, and corresponds to fig. 4 of the first embodiment. The semiconductor device A3 is different from the semiconductor device a2 mainly in the shape of the lead frame 4.

The lead frame 4 of the present embodiment includes a die pad portion 41, a plurality of bonding pad portions 42a, 42b, 42c, 42d, 42e, a plurality of lead portions 43a, 43b, 43c, 43d, 43e, 43f, and a plurality of lateral extension portions 44. Therefore, the lead frame 4 of the present embodiment is different from the lead frame 4 of the semiconductor device a2 in that it further includes the bonding pad portion 42e and the lead portions 43e and 43 f.

Each of the x-direction end edges of the plurality of bonding pad portions 42d and 42e is recessed. In the present embodiment, as shown in fig. 11, the y-direction central portion is recessed more than the vicinity of the y-direction both end edges at the x-direction end edges of the bonding pad portions 42d and 42 e. The bonding pad portions 42d and 42e are the same size. Each bonding pad portion 42d is electrically connected to the second semiconductor element 2 via the third conductive member 33. Each bonding pad portion 42e is electrically connected to the third electrode 123 of the first semiconductor element 1 via the third conductive member 33.

The lead portion 43f is not connected to any of the bonding pad portions 42a to 42e, and is not electrically connected to any of the plurality of first semiconductor elements 1 and the plurality of second semiconductor elements 2. As shown in fig. 11, the lead portion 43f is disposed between the lead portion 43a and the lead portion 43b adjacent to each other in the x direction. In the present embodiment, the two lead portions 43a and the two lead portions 43b are disposed on opposite sides with the lead portion 43f interposed therebetween in the x direction. The width of the portion of the lead portion 43f covered with the sealing resin 5 shown in fig. 11 is larger than the width of the portion exposed from the sealing resin 5, but the same may be used or may be smaller. However, by increasing the size as shown in fig. 11, the lead portion 43f can be prevented from coming off the sealing resin 5.

The bonding pad portions 42a and 42b of the present embodiment are not rectangular as in the first embodiment, but include protruding portions 421a and 421b protruding from one end edge in the x direction. The protruding portions 421a, 421b each overlap the lead portion 43f when viewed in the y direction.

The lead frame 4 of the present embodiment includes one bonding pad portion 42a, and two lead portions 43a are connected to the bonding pad portion 42 a. The lead frame 4 includes one bonding pad portion 42b, and two lead portions 43b are connected to the bonding pad portion 42 b. The lead frame 4 includes one bonding pad portion 42c, and three lead portions 43c are connected to the bonding pad portion 42 c. The lead frame 4 includes six bonding pad portions 42d, and one lead portion 43d is connected to each of the six bonding pad portions 42 d. The lead frame 4 includes two bonding pad portions 42e, and one lead portion 43e is connected to each of the two bonding pad portions 42 e. Further, the lead frame 4 includes one lead portion 43 f.

The third conductive member 33 of the present embodiment is composed of, for example, an Au (gold) wire or a Cu wire. Each third conductive member 33 is formed by, for example, ball bonding or stitch bonding using a capillary. Further, the material, forming method, and shape of the third conductive member 33 are not limited to the above. For example, the third conductive member 33 of the present embodiment may be formed of an Al wire instead of an Au wire or a Cu wire. In addition, the third conductive member 33 of the present embodiment may have a thickness similar to that of the first and second embodimentsLeft and right.

The semiconductor device A3 has the following structure as in the semiconductor device a 1. This structure is such that the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes a first pad portion 142a and a second pad portion 142 b. In addition, the second conductive member 32 includes the joint portion 321 joined to the first pad portion 142a and the joint portion 322 joined to the second pad portion 142 b. With this configuration, a current path through the second conductive member 32 can be ensured between the first pad portion 142a and the second pad portion 142 b. Therefore, the second conductive member 32 can serve as a bypass path for the current flowing through the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 3.

According to the semiconductor device A3, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141, as with the semiconductor device a 1. Also, first and second pad portions 142a and 142b are included in each first plate-like member 141. Therefore, similarly to the semiconductor device a1, since the wiring resistance of each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device A3 can be reduced.

According to the semiconductor device a3, the lead portion 43f that is not connected to any of the bonding pad portions 42a to 42e is further included. In the x direction, two lead portions 43a connected to the second electrode 122 of the first semiconductor element 1A and two lead portions 43B connected to the second electrode 122 of the first semiconductor element 1B are arranged with the lead portions 43f interposed therebetween. With this configuration, since the distance between the adjacent lead portions 43a and 43b can be increased, the short circuit between the second electrodes 122 of the two first semiconductor elements 1 can be suppressed.

According to the semiconductor device a3, the bonding pad portions 42a, 42b include the protrusions 421a, 421b, respectively. With this configuration, the bonding pad portions 42a and 42b can have an enlarged area in plan view. For example, when the plurality of first conductive members 31, the plurality of second conductive members 32, and the plurality of third conductive members 33 are wire bonded, a part of the bonding pad portion 42 is pressed by a fixing member of a wire bonding device such as a clip to fix the lead frame 4. Therefore, by enlarging the area, a region that can be pressed by the fixing member can be secured, and thus the lead frame 4 can be reliably fixed. Further, since the area is enlarged, the region where the plurality of first conductive members 31 are joined becomes larger when pressed by the fixing member or the like, and therefore, as shown in fig. 11, the plurality of first conductive members 31 are easily joined.

[ fourth embodiment ]

Fig. 12 shows a semiconductor device according to a fourth embodiment. Fig. 12 is a plan view showing a semiconductor device a4 according to a fourth embodiment, and corresponds to fig. 4 of the first embodiment. The semiconductor device a4 mainly has a different bonding position of the second conductive member 32 than the semiconductor device a 1.

Each second conductive member 32 of the present embodiment is curved in a plan view. In the present embodiment, a part of the second conductive members 32 is bonded to each of the first semiconductor elements 1 so as to straddle two first electrode conduction members 141a adjacent to each other in the x direction. Specifically, the bonding portion 321 of a part of the second conductive member 32 is bonded to the first pad portion 142a of one of the two first electrode conduction members 141a, and the bonding portion 322 is bonded to the second pad portion 142b of the other. In addition, a part of the second conductive members 32 is bonded to each of the first semiconductor elements 1 across two second electrode conduction members 141b adjacent to each other in the x direction. Specifically, the bonding portion 321 of a part of the second conductive member 32 is bonded to the first pad portion 142a of one of the two second electrode conduction members 141b, and the bonding portion 322 is bonded to the second pad portion 142b of the other.

The semiconductor device a4 has the following structure as in the semiconductor device a 1. This structure is such that the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes a first pad portion 142a and a second pad portion 142 b. In addition, the second conductive member 32 includes the joint portion 321 joined to the first pad portion 142a and the joint portion 322 joined to the second pad portion 142 b. With this configuration, a current path through the second conductive member 32 can be ensured between the first pad portion 142a and the second pad portion 142 b. Therefore, the second conductive member 32 can serve as a bypass path for the current flowing through the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 4.

In the semiconductor device a4, as shown in fig. 12, the configuration of the first conductive layer 14 of each first semiconductor element 1 is the same as the configuration of the first conductive layer 14 of each first semiconductor element 1 of the first embodiment, but the present invention is not limited to this, and even if the configuration is the same as the configuration of the first conductive layer 14 of each first semiconductor element 1 of the second embodiment and the third embodiment, the bonding position of the second conductive member 32 may be changed as in the present embodiment. For example, in the semiconductor device a2 shown in fig. 10, the second conductive members 32 may be bonded to each of the first semiconductor elements 1 across the second electrode conductive members 141b adjacent in the x direction.

In the semiconductor device a4, as shown in fig. 12, each first semiconductor element 1 (each first plate-like member 141) includes the first pad portion 142a and the second pad portion 142b to which the second conductive member 32 is not bonded, but these first pad portion 142a and second pad portion 142b may not be included. In this case, an accidental short circuit in which the pad portions 142 of the second conductive member 32 are not joined to each other can be suppressed.

[ fifth embodiment ]

Fig. 13 shows a semiconductor device of a fifth embodiment. Fig. 13 is a plan view showing a semiconductor device a5 of the fifth embodiment, and corresponds to fig. 4 of the first embodiment. The semiconductor device a5 differs from the semiconductor device a1 mainly in the thickness of the first conductive member 31 and in the absence of the second conductive member 32.

The first conductive layer 14 of the present embodiment includes one second electrode conduction member 141B that is electrically connected to the second electrode 122 of the first semiconductor element 1A, one second electrode conduction member 141B that is electrically connected to the second electrode 122 of the first semiconductor element 1B, and one first electrode conduction member 141A that is electrically connected to both of the first electrodes 121 of the first semiconductor elements 1. The first electrode conduction member 141a is commonly connected to both of the first electrodes 121 of the first semiconductor elements 1.

In the first conductive layer 14 of the present embodiment, the width of each first plate-like member 141 is larger than the width of each first plate-like member 141 of the first to fourth embodiments, and is about 650 μm. In addition, each first plate-like member 141 includes one pad portion 142.

The thickness (wire diameter) of each first conductive member 31 of the present embodiment isLeft and right. Therefore, each first conductive member 31 of the present embodiment is larger than any first conductive member 31 of the semiconductor devices a1 to a 4. Each third conductive member 33 of the present embodiment is the same as each third conductive member 33 of the first embodiment. Therefore, the thickness of each third conductive member 33 is set to beleft and right.

in each first conductive member 31 of the present embodiment, as shown in fig. 13, the bonding portion 311 is bonded to the pad portion 142. The bonding portion 311 overlaps the y-direction centers of the plurality of first semiconductor elements 1 in a plan view. Further, the bonding portion 311 bonded to the first electrode conduction member 141a which is in conduction with the first electrode 121 also overlaps the boundary between the two first semiconductor elements 1 in a plan view. In the present embodiment, the first conductive member 31 corresponds to the "conductive member" described in the claims. In the present embodiment, each first conductive member 31 is first wedge-bonded to the pad portion 142 of the first plate-like member 141, and then wedge-bonded to each bonding pad portion 42.

According to the semiconductor device a5, the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes the pad portions 142. Further, the first conductive member 31 includes a joint portion 311 joined to the pad portion 142. With this configuration, a current path can be secured in the pad portion 142 through the joint portion 311 of the first conductive member 31. Therefore, the junction 311 of the first conductive member 31 can serve as a bypass path for the current flowing in the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 5.

according to the semiconductor device a5, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141. Also, a pad portion 142 is included in each first plate-like member 141. With this configuration, the pad portions 142 can ensure current paths passing through the inside of the first plate-like members 141 and current paths passing through the joint portions 311 of the first conductive members 31. In particular, since the wiring resistance of the first conductive member 31 is lower than that of the first plate-like member 141, the joint portion 311 of the first conductive member 31 serves as a bypass path for the current flowing through the pad portion 142. Therefore, since the wiring resistance of each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device a5 can be reduced.

According to the semiconductor device a5, the bonding portion 311 of each first conductive member 31 overlaps the center of each first plate-like member 141 in the y direction in plan view. With this configuration, the maximum distance from the outer peripheral portion of each first plate-like member 141 to the joining portion 311 in a plan view can be shortened as compared with a case where the joining portion 311 is joined to one end edge side of each first plate-like member 141 in the y direction. Therefore, since the current path in each first plate-like member 141 can be shortened, the internal resistance of the semiconductor device a5 can be reduced.

[ sixth embodiment ]

Fig. 14 shows a semiconductor device according to a sixth embodiment. Fig. 14 is a plan view showing a semiconductor device a6 according to a sixth embodiment, and corresponds to fig. 4 of the first embodiment. The semiconductor device a6 is different from the semiconductor device a5 mainly in the shape of the lead frame 4.

As shown in fig. 14, the lead frame 4 of the present embodiment is formed in the same manner as the lead frame 4 of the third embodiment. However, in the lead frame 4 of the present embodiment, at least a part of each of the corners of the bonding pad portions 42a, 42b, and 42c is chamfered.

Each of the first conductive members 31 of the present embodiment is first wedge-bonded to each of the bonding pad portions 42, and then wedge-bonded to the pad portions 142 of the first plate-like member 141.

each third conductive member 33 of the present embodiment is formed of, for example, an Au wire or a Cu wire, as in the semiconductor device a 3. In addition, the thickness may be as large as the semiconductor device a5Left and right Al wires.

The semiconductor device a6 has the following structure as in the semiconductor device a 5. The structure is such that the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes a pad portion 142. Further, the first conductive member 31 includes a joint portion 311 joined to the pad portion 142. With this configuration, a current path can be secured in the pad portion 142 through the joint portion 311 of the first conductive member 31. Therefore, the junction 311 of the first conductive member 31 can serve as a bypass path for the current flowing in the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 6.

According to the semiconductor device a6, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141, as with the semiconductor device a 5. Also, a pad portion 142 is included in each first plate-like member 141. Therefore, similarly to the semiconductor device a5, since the wiring resistance in each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device a6 can be reduced.

According to the semiconductor device a6, the joint portion 311 of each first conductive member 31 overlaps the center of each first plate-like member 141 in the y direction in plan view, as in the semiconductor device a 5. With this configuration, the distance from the other edge side of the first plate-like member 141 to the joining portion 311 in a plan view can be shortened as compared with a case where the joining portion 311 of each first conductive member 31 is joined to one edge side of each first plate-like member 141 in the y direction. Therefore, since the current path in each first plate-like member 141 can be shortened, the internal resistance of the semiconductor device a6 can be reduced.

[ seventh embodiment ]

Fig. 15 shows a semiconductor device according to a seventh embodiment. Fig. 15 is a plan view showing a semiconductor device a7 according to a seventh embodiment, and corresponds to fig. 4 of the first embodiment. The semiconductor device a7 is different from the semiconductor device a5 mainly in the shape of the lead frame 4.

The arrangement of the side extending portion 44 of the lead frame 4 of the present embodiment is different from the arrangement of the side extending portion 44 of the semiconductor device a 4. The side extending portions 44 of the present embodiment extend one from each of the y-direction central portions at each end edge of the die pad portion 41 in the x direction. The side extension portion 44 protrudes from an edge of the sealing resin 5 in the x direction in a plan view.

In the present embodiment, any one of the plurality of first conductive members 31 is formed by bonding the bonding portion 312 to the pad portion 41. In fig. 15, the one first conductive member 31 is joined to the second electrode conduction member 141b, and the second electrode conduction member 141b is electrically conducted to the second electrode 122 of the first semiconductor element 1A.

in the present embodiment, as in the sixth embodiment, Au wires or Cu wires are used for the plurality of third conductive members 33. In addition, as in the fifth embodiment, an Al wire is used.

In the present embodiment, as shown in fig. 15, the first conductive layer 14 includes three first plate-like members 141, and the widths of the three first plate-like members 141 are substantially equal to each other. Further, the widths of the three first plate-like members 141 may be different.

The semiconductor device a7 has the following structure as in the semiconductor device a 5. The structure is such that the wiring layer 13 formed on each of the plurality of first semiconductor elements 1 includes a pad portion 142. Further, the first conductive member 31 includes a joint portion 311 joined to the pad portion 142. With this configuration, a current path can be secured in the pad portion 142 through the joint portion 311 of the first conductive member 31. Therefore, the junction 311 of the first conductive member 31 can serve as a bypass path for the current flowing in the wiring layer 13. This can reduce the wiring resistance of the wiring layer 13, and hence can reduce the internal resistance of the semiconductor device a 7.

According to the semiconductor device a7, the wiring layer 13 includes the first conductive layer 14, and the first conductive layer 14 includes the plurality of first plate-like members 141, as with the semiconductor device a 5. Also, a pad portion 142 is included in each first plate-like member 141. Therefore, similarly to the semiconductor device a5, since the wiring resistance of each first plate-like member 141 can be reduced, the internal resistance of the semiconductor device a7 can be reduced.

According to the semiconductor device a7, the joint portion 311 of each first conductive member 31 overlaps the center of each first plate-like member 141 in the y direction in plan view, as in the semiconductor device a 5. With this configuration, the distance from the other edge side of the first plate-like member 141 to the joining portion 311 in a plan view can be shortened as compared with a case where the joining portion 311 of each first conductive member 31 is joined to one edge side of each first plate-like member 141 in the y direction. Therefore, since the current path in each first plate-like member 141 can be shortened, the internal resistance of the semiconductor device a7 can be reduced.

In semiconductor device a7, two side extending portions 44 are shown extending one from each y-direction central portion at each end edge of die pad portion 41 in the x-direction, but the present invention is not limited to this. The plurality of side extending portions 44 of the lead frame 4 may be configured in the same manner as in the first to sixth embodiments, for example. That is, the plurality of side extending portions 44 may extend one from each end edge side in the y direction among the end edges in the x direction of the die pad portion 41. The same applies to the other way round. That is, in the semiconductor devices a1 to a6, the side extension portion 44 may be disposed as in the seventh embodiment.

in the first to seventh embodiments, the terminal arrangement of each lead portion 43 of the semiconductor devices a1 to a7 is not limited to the above. Fig. 16 to 20 show the terminal arrangement of another embodiment. Each symbol in these drawings functions as a terminal described below. I.e., GND, which is a ground terminal. Further, GND in fig. 19 is exposed from the bottom surface side. VIN is the power input terminal. SW is a switch output terminal. The PGD is a power grid terminal. EN is a control terminal of the device. AVIN is the analog section power input terminal. AGND is an analog section ground terminal. FB is the output voltage feedback terminal. SS is a terminal for setting soft start time. SSCG is a spectrum spread setting terminal. MODE is a terminal for switching various MODEs. VREG is an internal power supply output terminal. BST is the internal boost power supply output terminal. COMP is an erase output terminal. VCC _ EX is a power supply terminal for the internal circuit. The CTL is a control terminal for various functions. NC is an unconnected terminal. The semiconductor device of the present invention may be configured such that the arrangement and shape of each component element are appropriately changed so as to function as the terminal shown in fig. 16 to 20. The terminal arrangement shown in fig. 16 to 20 is only an example, and is not limited to this.

In the first to seventh embodiments, the circuit configurations of the semiconductor devices a1 to a7 are not particularly limited, and fig. 21 shows an example of the circuit configuration. Fig. 21 is a circuit diagram when the semiconductor devices a1 to a7 are configured as DC/DC converters. In fig. 21, sw1 and sw2 denote switching elements. Dr denotes a control circuit that controls switching operations of the switching elements sw1 and sw2, operations of various protection functions, and the like. R1 to R3 denote resistors, Vref denotes an internal reference voltage circuit, ss denotes a soft start circuit, and amp denotes an error amplifier that inputs a Vref output voltage and an FB terminal voltage. For example, one of the switching elements sw1 and sw2 corresponds to the first semiconductor element 1A, and the other corresponds to the first semiconductor element 1B. Further, a circuit including an internal reference voltage circuit Vref, a soft start circuit ss, an error amplifier amp, and a control circuit Dr corresponds to the second semiconductor element 2. PVIN is a power input terminal of the DC/DC converter, and PGND is a ground terminal of the DC/DC converter.

In the first to seventh embodiments, the semiconductor devices a1 to a7 are SOP type semiconductor packages, but the present invention is not limited thereto. For example, the semiconductor Package may be a QFP (Quad Flat Package) semiconductor Package, or a SON (small outline Non-leaded Package) or a leadless semiconductor Package called QFN (Quad Flat Non-leaded Package). For example, fig. 22 is a perspective view showing an example of a case where the QFN type semiconductor package is configured. The perspective view shown in fig. 22 shows the case when viewed from the bottom surface side.

In the first to seventh embodiments, the semiconductor devices a1 to a7 include a plurality of first semiconductor elements 1 and second semiconductor elements 2, but are not limited thereto. For example, the first semiconductor element 1 may be one, or the second semiconductor element 2 may not be included.

The semiconductor device of the present invention is not limited to the above-described embodiments. The specific structure of each part of the semiconductor device of the present invention can be changed in various ways.