阅读说明：本技术 一种半导体器件及其制造方法 (Semiconductor device and manufacturing method thereof ) 是由 张程 谢岩 于 2019-09-18 设计创作，主要内容包括：本发明提供一种半导体器件及其制造方法,衬底上形成有覆盖层、扩散阻挡层以及粘合层,在粘合层中形成连线层上的键合孔之后,继续刻蚀键合孔中连接孔下的扩散阻挡层,直至贯通至连线层,并过刻蚀连线层,连线层中过刻蚀部分的形貌基本呈倒梯形或方形,这样,这样的形貌更利于后续键合孔材料的填充,提高键合垫与连线层的电连接特性,进而提高器件的性能。(The invention provides a semiconductor device and a manufacturing method thereof.A covering layer, a diffusion barrier layer and a bonding layer are formed on a substrate, after bonding holes on a connecting layer are formed in the bonding layer, the diffusion barrier layer below connecting holes in the bonding holes is continuously etched until the bonding holes penetrate through the connecting layer, and the connecting layer is over-etched, wherein the over-etched part in the connecting layer is basically in an inverted trapezoid or square shape, so that the shape is more beneficial to filling of subsequent bonding hole materials, the electrical connection characteristic of a bonding pad and the connecting layer is improved, and the performance of the device is further improved.)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein a covering layer, an etching stop layer and an adhesive layer of a dielectric material are sequentially stacked on the substrate, a connecting line layer is formed in the covering layer, a bonding hole located on the connecting line layer is formed in the adhesive layer, and the bonding hole comprises a connecting hole and a through hole on the connecting hole;

Etching the etching stop layer below the connecting hole until the connecting line layer is over-etched to form a through bonding hole, wherein the size of the bottom appearance of the over-etched part in the connecting line layer is not larger than that of the upper appearance;

And filling the bonding holes to form bonding pads.

2. The method of claim 1, wherein the interconnect layer is made of aluminum and the bonding pads are made of copper.

3. A method of manufacturing according to claim 1 or 2, characterized in that the topography of the over-etched portions in the wiring level is substantially inverted trapezoidal.

4. The manufacturing method according to claim 3, wherein the performing of the etching stop layer under the connection hole comprises:

And performing main etching on the etching stop layer by adopting dry etching under a first process parameter until the etching stop layer penetrates through the wiring layer, and performing over-etching on the wiring layer under a second process parameter.

5. The manufacturing method according to claim 4, wherein the etching stop layer comprises a silicon nitride layer, a dielectric antireflection layer and a titanium nitride layer thereunder are further formed between the etching stop layer and the connecting line layer, and the etching gas for dry etching comprises: CHF₃and Ar, CHF being among the second process parameters₃The range of the ratio to Ar gas is: 15:1 to 20: 1.

6. the method as claimed in claim 5, wherein the pressure in the chamber is in the range of 8-12mtorr and the bias power is in the range of 900-1100W in the second process parameter.

7. The manufacturing method according to claim 1, wherein the method of forming the bonding hole in the adhesive layer includes:

performing patterning of the adhesive layer to form a connection hole in the adhesive layer;

Forming a filling layer on the connecting hole and the bonding layer;

Patterning the filling layer and the bonding layer with partial thickness on the connecting hole to form a via hole on the connecting hole;

And removing the filling layer.

8. A semiconductor device, comprising:

A substrate;

A covering layer, an etching stop layer and a bonding layer of a dielectric material are sequentially stacked on the substrate, and a connecting line layer is formed in the covering layer;

The bonding hole in the connecting line layer penetrates through the bonding layer and the etching stopping layer to reach partial thickness, the bonding hole comprises a connecting hole and a through hole on the connecting hole, and the size of the bottom appearance of the over-etched part in the connecting line layer is not larger than that of the upper appearance;

And a bonding pad filling the bonding hole.

9. The device of claim 8, wherein the material of the wiring layer is aluminum and the material of the bonding pad is copper.

10. The device of claim 9, wherein the topography of the over-etched portions of the wiring layer is substantially inverted trapezoidal.

Technical Field

The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a semiconductor device and a manufacturing method thereof.

Background

With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology is widely used, which utilizes wafer bonding technology to bond wafers with different functions together in a stacked manner, and has the advantages of high performance, low cost and high integration.

In the application of the wafer bonding technology, a bonding hole can be used for hybrid bonding, the bonding hole is connected with a connecting line layer, and the forming process of the bonding hole can affect the electrical connection characteristic with the connecting line layer, so that the performance of a device is affected.

Disclosure of Invention

in view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, which can improve the appearance of the bonding hole in the interconnection layer after over-etching, and improve the device performance.

in order to achieve the purpose, the invention has the following technical scheme:

A method of manufacturing a semiconductor device, comprising:

Providing a substrate, wherein a covering layer, an etching stop layer and an adhesive layer of a dielectric material are sequentially stacked on the substrate, a connecting line layer is formed in the covering layer, a bonding hole located on the connecting line layer is formed in the adhesive layer, and the bonding hole comprises a connecting hole and a through hole on the connecting hole;

Etching the etching stop layer below the connecting hole until the connecting line layer is over-etched to form a through bonding hole, wherein the size of the bottom appearance of the over-etched part in the connecting line layer is not larger than that of the upper appearance;

and filling the bonding holes to form bonding pads.

Optionally, the material of the interconnect layer is aluminum, and the material of the bonding pad is copper.

Optionally, the shape of the over-etched part in the connecting line layer is substantially in an inverted trapezoid.

optionally, the etching stop layer under the connection hole includes:

And performing main etching on the etching stop layer by adopting dry etching under a first process parameter until the etching stop layer penetrates through the wiring layer, and performing over-etching on the wiring layer under a second process parameter.

Optionally, the etching stop layer includes a silicon nitride layer, a dielectric antireflection layer and a titanium nitride layer thereunder are further formed between the etching stop layer and the interconnect layer, and the etching gas for dry etching includes: CHF₃And Ar, CHF being among the second process parameters₃The range of the ratio to Ar gas is: 15:1 to 20: 1.

Optionally, in the second process parameter, the pressure in the chamber is in a range of 8-12mtorr, and the bias power is in a range of 900-.

optionally, the method for forming the bonding hole in the bonding layer includes:

Performing patterning of the adhesive layer to form a connection hole in the adhesive layer;

Forming a filling layer on the connecting hole and the bonding layer;

Patterning the filling layer and the bonding layer with partial thickness on the connecting hole to form a via hole on the connecting hole;

and removing the filling layer.

a semiconductor device, comprising:

A substrate;

a covering layer, an etching stop layer and a bonding layer of a dielectric material are sequentially stacked on the substrate, and a connecting line layer is formed in the covering layer;

The bonding hole in the connecting line layer penetrates through the bonding layer and the etching stopping layer to reach partial thickness, the bonding hole comprises a connecting hole and a through hole on the connecting hole, and the size of the bottom appearance of the over-etched part in the connecting line layer is not larger than that of the upper appearance;

And a bonding pad filling the bonding hole.

Optionally, the material of the interconnect layer is aluminum, and the material of the bonding pad is copper.

Optionally, the shape of the over-etched part in the connecting line layer is substantially in an inverted trapezoid.

According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the covering layer, the diffusion barrier layer and the bonding layer are formed on the substrate, after the bonding hole on the connecting layer is formed in the bonding layer, the diffusion barrier layer below the connecting hole in the bonding hole is continuously etched until the bonding hole penetrates through the connecting layer, and the connecting layer is over-etched, wherein the dimension of the bottom appearance of the over-etched part in the connecting layer is not larger than that of the upper appearance, so that the appearance is more beneficial to filling of subsequent bonding hole materials, the electrical connection characteristic of the bonding pad and the connecting layer is improved, and the performance of the device is further improved.

drawings

in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;

FIGS. 2-8 are schematic cross-sectional views illustrating the formation of a semiconductor device according to a method of manufacturing an embodiment of the present invention;

Fig. 9 shows sectional photographs of connection holes formed by the methods of the related art and the embodiment of the present application, respectively.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.

next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background, in the application of the wafer bonding technology, a hybrid bonding may be performed using a bonding hole, the bonding hole is connected to a wiring layer, and the forming process of the bonding hole may affect the electrical connection characteristics with the wiring layer, thereby affecting the performance of the device.

Based on the above, the application provides a manufacturing method of a semiconductor device, wherein a covering layer, a diffusion barrier layer and a bonding layer are formed on a substrate, after bonding holes on a connecting layer are formed in the bonding layer, the diffusion barrier layer below connecting holes in the bonding holes is continuously etched until the diffusion barrier layer penetrates through the connecting layer, the connecting layer is over-etched, and the size of the bottom appearance of an over-etched part in the connecting layer is not larger than that of the upper appearance.

In order to better understand the technical solution and technical effects of the present application, a detailed description will be given below of specific embodiments with reference to the flowchart 1 and the accompanying fig. 2-8.

Referring to fig. 1, in step S01, a substrate 100 is provided, and cover layers 120 and 122, an etch stop layer 134, and adhesive layers 142 and 140 of dielectric materials are sequentially stacked on the substrate 100, wherein a wiring layer 124 is formed in the cover layers 120 and 122, and bonding holes are formed in the adhesive layers 142 and 140 on the wiring layer 124, and the bonding holes include a connection hole 160 and a via hole 164 thereon, as shown in fig. 6.

In the embodiment of the present application, the substrate 100 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In this embodiment, the substrate 100 may be a silicon substrate.

All processes before a bonding layer is completed on the substrate 100, for example, a device structure and an interconnection layer electrically connecting the device structure have been formed on the substrate 100, the device structure is covered by an interlayer dielectric layer 110, the interlayer dielectric layer 110 may be silicon oxide, the interconnection layer is formed in a dielectric material, the device structure may be a MOS device, a sensing device, a memory device and/or other passive devices, the interconnection layer may include multiple layers, the interconnection layer may include contact plugs, vias and a wiring layer, and the interconnection layer may be a metal material, and may be, for example, tungsten, aluminum, copper, and the like. In the illustration of the embodiments of the present application, only the top wiring layer 124 is illustrated, here only for the sake of simplifying the drawing, it being understood that this is merely an example, and in different designs and applications, the required number of interconnect layers can be formed as desired.

In the embodiment of the present application, the interconnect layer 124 is the topmost interconnect layer before forming the bonding holes, the interconnect layer may be a top metal layer (top metal), the capping layers 120 and 122 are dielectric materials for isolating the topmost interconnect layer 124, and the capping layers may be a single-layer or multi-layer structure.

in the embodiment, the capping layers 120 and 122 are stacked, and may include a silicon nitride layer 120 and a silicon oxide layer 122 thereon, the silicon nitride layer 120 may serve as a diffusion barrier layer, the silicon oxide layer 120 may be FSG (fluorinated silicate Glass), and in one example, the thickness of the silicon nitride layer 120 may be set asThe thickness of the silicon oxide layer 122 may be

In the embodiment of the present application, the interconnect layer 124 is the topmost interconnect layer before forming the bonding holes, the interconnect layer may be a top metal layer (top metal), the capping layers 120 and 122 are dielectric materials for isolating the topmost interconnect layer 124, and the capping layers may be a single-layer or multi-layer structure.

In the embodiment, the capping layers 120 and 122 are stacked, and may include a silicon nitride layer 120 and a silicon oxide 122 layer thereon, the silicon nitride layer 120 may serve as a diffusion barrier layer, the silicon oxide layer 120 may be FSG (fluorinated silicate Glass), and in one example, the thickness of the silicon nitride layer 120 may beThe thickness of the silicon oxide layer 122 may be

the wiring layer 124 is formed in the covering layer 122, and the wiring layer 124 may be formed of a metal material, and in this embodiment, the wiring layer 124 may be copper metal or aluminum metal. In this embodiment, a titanium nitride layer 130 and a Dielectric Anti-Reflection Coating (DARC) layer 132 may be further sequentially disposed on the capping layer, wherein the titanium nitride layer 130 prevents the formation of hillock on the interconnect layer and inhibits electromigration, and the DARC layer may reduce Reflection of the Dielectric Anti-Reflection Coating layer to the exposure light during photolithography. An etch stop layer 134 is also disposed on the dielectric anti-reflective layer 132, wherein the bonding hole stops on the etch stop layer 134, and the etch stop layer 134 can be formed by selecting a suitable material, such as silicon nitride, and has a diffusion barrier function.

The adhesive layer is used as a bonding material layer for bonding with other wafers, and in the embodiment of the present application, the adhesive layer is a dielectric material, which may be a single-layer or multi-layer structure, in which a bonding pad is formed, and the bonding pad is connected to the wiring layer 124, so that hybrid bonding with other wafers can be realized through the adhesive layer and the bonding pad.

in this embodiment, the adhesive layer includes the first adhesive layer 140 and the second adhesive layer 142 thereon, and the protective layer 146 may be further disposed on the second adhesive layer 142. The first adhesive layer 140 and the second adhesive layer 142 may be different bonding materials, and the second adhesive layer 142 may be a bonding material with better performance, in this embodiment, the first adhesive layer 140 may be a bonding silicon oxide (bonding oxide), the second adhesive layer 142 may be NDC (Nitrogen doped silicon Carbide), and the protective layer 146 is used for protecting the adhesive layer in a subsequent process, and may be a silicon oxide. In a specific example, the thicknesses of the first adhesive layer 140, the second adhesive layer 142, and the protective layer 146 may be respectively

Bonding holes have been formed in the adhesive layers 140, 142, the bonding holes including the connection hole 160 and the via 164 thereon, in this step, the connection hole 160 has not penetrated to the wiring layer 124 yet, the connection hole 160 stops on the etch stop layer 134, and a portion of the etch stop layer 134 may also be over-etched, and in a subsequent step, the connection hole 160 will be further opened and penetrate to the wiring layer 124 for electrical connection with the wiring layer 124.

In the present embodiment, after the adhesive layers 140, 142 are formed over the substrate 100, the bonding holes may be formed by the following method. In the present embodiment, referring to fig. 2, a capping layer 122 is formed on a substrate 100, a wiring layer 124 is formed in the capping layer 122, a titanium nitride layer 130, a DARC layer 132 and an etching stop layer 134 of silicon nitride are sequentially formed on the capping layer 122, the adhesion layers include a first adhesion layer 140 of silicon oxide and a second adhesion layer 142 of NDC, and a protective layer 146 of silicon oxide is formed on the second adhesion layer 142.

specifically, in step S101, patterning of the adhesive layers 140 and 142 is performed to form the connection hole 160 in the adhesive layers 140 and 142, as shown in fig. 3.

In the patterning process, a first photoresist layer 150 may be formed on the protection layer 146, and the thickness of the first photoresist layer 150 may be, for example, 1.2 μm, a pattern of a connection hole is formed in the first photoresist layer 150, and the protection layer 146, the second adhesive layer 142, and the first adhesive layer 140 are sequentially etched under the mask of the first photoresist layer 150, for example, reactive ion etching may be used until the etching stop layer 134, or a portion of the etching stop layer 134 may be over-etched, so that a connection hole 160 is formed, so that a pattern of a connection hole connected to the connection layer 124 is previously defined in the adhesive layer, and as shown in fig. 3, the first photoresist layer 150 is removed.

In step S102, a filling layer 162 is formed on the connection hole 160 and the adhesive layers 140 and 142, as shown in fig. 4.

As the protective layer of the connection hole 160, the filling layer 162 may be formed of a material having good step coverage and strong fluidity, and in this embodiment, the material of the filling layer 162 may beFor BARC (bottom anti-reflective coating), a fill layer 162 of BARC will be formed in the connection hole 160 and on the protective layer 146 after the BARC material is filled, as shown in fig. 4. In one specific example, the BARC fill layer 162 on the protective layer 146 may have a thickness

in step S103, a filling layer 162 and a partial thickness of the adhesive layers 140 and 142 are patterned over the connection hole 160 to form a via 164 on the connection hole 160, as shown in fig. 5.

In the patterning process, a second photoresist layer 152 may be formed on the filling layer 162, for example, to a thickness of 1.4 μm, and a pattern of via holes is formed in the second photoresist layer 152, as shown with reference to fig. 4. Then, under the masking of the second photoresist layer 152, the etching of the filling layer 162 is performed first, then the etching of the protective layer 146, the second adhesive layer 142 and the first adhesive layer 140 is performed, then, the etching of the filling layer in the connection hole 160 in the protective layer 146 and the etching of the filling layer in the connection hole 160 in the adhesive layer are performed, for example, reactive ion etching may be adopted, and the etching is stopped until the etching reaches the adhesive layer with a partial thickness through the control of etching time, so that the via hole 164 is formed on the connection hole 160, and then, the second photoresist layer is removed. In this embodiment, referring to fig. 5, the etching stops in a partial thickness of the second adhesion layer 140, and in one example, the thickness of the second adhesion layer 140 may bethe etching of the via 164 may removeThe second adhesive layer of (2).

In step S104, the filling layer 162 is removed, as shown in fig. 6.

After the fill layer 162 is removed, blind bond holes are formed over the interconnect layer 124. Thereafter, the connection hole may be further opened to form a bonding hole penetrating to the wiring layer 124. In this embodiment, the non-through bonding hole is formed above the etch stop layer, so that damage to the interconnect layer below the bonding hole can be reduced, and the electrical connection performance with the interconnect layer can be improved.

in step S02, the etching of the etching stop layer 134 under the connection hole 160 is performed until the wiring layer 124 is over-etched to form a through bonding hole, and the dimension of the bottom feature of the over-etched portion 1601 in the wiring layer 124 is not greater than the dimension of the upper feature, as shown in fig. 7.

In the practice of the applicant, in the application of forming an aluminum copper bond when the connecting line layer 124 is made of an aluminum material and the bonding hole is filled with a copper material, the electrical performance of the device is generally reduced, and in the research process, it is found that, in the process of etching the connecting hole 160 at the bottom of the bonding hole to the connecting line layer 124, due to the characteristics of the aluminum material, irregular erosion can be caused to the connecting line layer 124 of the aluminum, transverse underetching or longitudinal irregular erosion can occur, which can cause the occurrence of irregular topography at the bottom of the connecting hole 160, and during subsequent copper filling, the growth of copper seeds can be influenced, so that the aluminum copper bond is influenced, and the performance of the device is reduced.

In the application, in the process of opening the connection hole 160 until penetrating the connection layer 124, by controlling the etching process, the dimension of the bottom feature of the over-etched portion 1601 over-etched to the connection layer 124 is not larger than that of the upper feature, that is, the bottom of the over-etched portion is prevented from being expanded outward in the over-etching process, according to different process controls, the feature of the over-etched portion 1601 is different, for example, the over-etched portion can be in an inverted trapezoid shape or a square shape or other features without transversely expanding outward at the bottom, wherein the square shape includes a square and a rectangle, so that the connection layer 124 is prevented from being subjected to transverse underetching or longitudinally irregular erosion, the bottom of the connection hole 160 is in a more regular shape, the growth of copper seeds is facilitated, and the device performance is.

in a specific embodiment, the connection hole 160 may be opened by dry etching, in the dry etching process, first, main etching is performed under a first process parameter, the main etching is to open a film layer between the connection hole 160 and the wiring layer 124, and then, under a second process parameter, over-etching of the wiring layer is performed, in this process, etching gas may be kept unchanged, and by adopting a process parameter different from the main etching in the over-etching process, only a part of the process parameters may be changed, or all the process parameters may be changed, so that the morphology after the over-etching is controlled.

In the embodiment, the etching stop layer 134 comprises a silicon nitride layer, a dielectric anti-reflection layer 132 and a titanium nitride layer 130 thereunder are further formed between the etching stop layer 134 and the connecting line layer 124, and during the dry etching process, an etching gas combining chemical reaction and physical bombardment is used, and the used etching gas can comprise CHF₃and Ar, wherein CHF is an etching gas₃Mainly used as polymer gas, Ar is used as bombardment gas, plasma etching equipment is adopted for etching in the main etching process, the gas pressure range can be 8-12torr, and CHF is adopted in the over-etching process₃The range of the ratio to Ar gas is: 15:1 to 20:1, the gas pressure can range from 8-12torr, and the bias power can range from 800-. By adjusting the proportion of the etching gas, the shape after over-etching is more regular.

In the etching process for opening the connection hole 160, the protective layer 146 is consumed, in one embodiment, the main etching process is controlled to ensure the main etching while excessive consumption of the protective layer 146 is avoided, in this embodiment, the original thickness of the protective layer 146 isAfter opening the connection hole 160, the remaining protective layer 146 has a thicknessThe above.

Referring to fig. 9, where (a) and (B) are photographs of cross sections of the connecting holes formed by the prior art at the center and edge of the wiring layer, and (C) and (D) are photographs of cross sections of the connecting holes formed by the method of the above embodiment at the center and edge of the wafer, it can be seen that the connecting holes formed by the prior art have irregular undercutting in the longitudinal direction, whereas the connecting holes formed by the embodiments of the present application have regular bottom shapes and substantially rectangular shapes.

In step S03, the filling of the bonding holes is performed to form the bonding pads 170, as shown in fig. 8.

copper materials can be used for filling, and during copper filling, a copper seed layer can be better formed in the connecting hole 160 with a regular morphology, so that the connection performance of copper and the connection layer 124 is improved. After filling, a planarization process may be performed until the adhesive layer is exposed, as shown with reference to fig. 8, thereby forming a bonding pad 170 in the bonding hole.

The above describes in detail the manufacturing method of the embodiment of the present application, and in addition, the present application provides a semiconductor device formed by the above method, as shown in fig. 8, including:

A substrate 100;

covering layers 120 and 122, an etching stop layer 134 and bonding layers 140 and 142 of dielectric materials are sequentially stacked on the substrate 100, and a connecting line layer 124 is formed in the covering layers 120 and 122;

A bonding hole in the wiring layer 124 penetrating through the adhesion layers 140 and 142 and the etch stop layer 134 to a partial thickness, the bonding hole including a connection hole 160 and a via 164 thereon, and a size of a bottom profile penetrating through a connection hole portion 1601 in the wiring layer 124 is not greater than a size of an upper profile;

And a bonding pad 170 filling the bonding hole.

Further, the material of the interconnect layer 124 is aluminum, and the material of the bonding pad 170 is copper.

Further, the shape of the over-etched part in the connecting line layer is basically in an inverted trapezoid shape.

further, the etch stop layer 134 comprises a silicon nitride layer, and a dielectric anti-reflection layer 132 and a titanium nitride layer 130 thereunder are formed between the etch stop layer 134 and the interconnect layer 124.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, they are described relatively simply, and reference may be made to some descriptions of the method embodiments for relevant points.

the foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.