阅读说明：本技术 一种扇出芯片封装结构及封装方法 (A kind of fan-out chip packaging structure and packaging method ) 是由 姚大平 于 2019-08-28 设计创作，主要内容包括：本发明公开了一种扇出芯片封装结构及封装方法,该封装结构包括：塑封体,内部封装有至少一颗芯片；芯片的器件面显露于塑封体外；互连层,设置于塑封体上器件面所在的表面,内部设置有与芯片的焊盘相对应的导电凸点；导电凸点用于将相应的焊盘引出至互连层上表面；重布线层,设置于互连层上；重布线层与凸点电耦合。通过设置于重布线层与塑封体之间的互连层,使得封装塑封体与芯片之间的界面应力经过互连层之后有了较大幅度的降低,从而使得重布线层所受到的应力能够较大幅度地减小,即使细窄重布线受界面应力的影响而疲劳断裂的可能性也大大降低,提高了该封装结构的可靠性。(The invention discloses a kind of fan-out chip packaging structure and packaging method, which includes: plastic-sealed body, and enclosed inside has an at least chips；The device side of chip is revealed in outside plastic-sealed body；Interconnection layer is set on plastic-sealed body the surface where device side, is internally provided with conductive salient point corresponding with the pad of chip；Conductive salient point is used to corresponding pad leading to interconnection layer upper surface；Layer is rerouted, is set on interconnection layer；Layer is rerouted to be electrically coupled with salient point.By being set to the interconnection layer rerouted between layer and plastic-sealed body, so that the interfacial stress between encapsulation plastic-sealed body and chip is by there is reduction by a relatively large margin after interconnection layer, so that rerouting stress suffered by layer can greatly reduce, even if narrower reroute is influenced and a possibility that fatigue fracture is greatly reduced by interfacial stress, the reliability of the encapsulating structure is improved.)

1. a kind of fan-out chip packaging structure characterized by comprising

Plastic-sealed body (1), enclosed inside have an at least chips (11)；The device side of the chip (11) is revealed in the plastic-sealed body (1) outside；

Interconnection layer (2) is set to the surface on the plastic-sealed body (1) where the device side, is internally provided with and the chip (11) the corresponding conductive salient point of pad (21)；The conductive salient point (21) is used to corresponding pad leading to the interconnection Layer (2) upper surface；

It reroutes layer (3), is set on the interconnection layer (2)；The rewiring layer (3) and the conductive salient point (21) thermocouple It closes.

2. fan-out chip packaging structure according to claim 1, which is characterized in that the conductive salient point (21) and the device Part face is vertical.

3. fan-out chip packaging structure according to claim 1 or 2, which is characterized in that the interconnection layer (2) includes medium Layer (22) and the conductive salient point (21) being formed in the dielectric layer (22)；Wherein, the dielectric layer (22) is photosensitive Property photopolymer layer, silicon oxide layer or silicon nitride layer.

4. fan-out chip packaging structure according to claim 1, which is characterized in that the interconnection layer (2) with a thickness of institute State 1-3 times for rerouting layer (3) thickness.

5. a kind of fan-out chip packaging method, which comprises the following steps:

It provides plastic-sealed body (1)；Wherein, plastic-sealed body (1) enclosed inside has an at least chips (11)；The chip (11) Device side is revealed in the plastic-sealed body (1) outside；

Surface on the plastic-sealed body (1) where the device side prepares interconnection layer (2)；Setting inside the interconnection layer (2) There is conductive salient point (21) corresponding with the pad of the chip (11)；The conductive salient point (21) is for drawing corresponding pad Out to the interconnection layer (2) upper surface；

Preparation reroutes layer (3) on the interconnection layer (2), and the rewiring layer (3) is electrically coupled with the conductive salient point (21).

6. fan-out chip packaging method according to claim 5, which is characterized in that the institute on the plastic-sealed body (1) Before stating the step of the surface of device side prepares interconnection layer (2), further includes:

Temporary base (5) are mounted on the surface of the plastic-sealed body (1) far from the device side of the chip (11).

7. fan-out chip packaging method according to claim 5 or 6, which is characterized in that described on the plastic-sealed body (1) The surface of the device side prepares the step of interconnection layer (2) and includes:

Surface on the plastic-sealed body (1) where the device side forms dielectric layer (22)；

The blind hole (210) for appearing the pad of the chip (11) is formed in the dielectric layer (22)；

Filling conductive material forms the conductive salient point (21) in the blind hole (210), to prepare the interconnection layer (2).

8. fan-out chip packaging method according to claim 7, which is characterized in that the dielectric layer (22) is dry for light sensitivity Film layer, silicon oxide layer or silicon nitride layer.

9. fan-out chip packaging method according to claim 5, which is characterized in that the interconnection layer (2) with a thickness of institute State 1-3 times for rerouting layer (3) thickness.

Technical field

The present invention relates to semiconductor integrated circuit package technical field more particularly to a kind of fan-out chip packaging structure and Packaging method.

Background technique

Wafer scale fan-out package technology relies on it as the technology most outstanding of the cost performance in system integration encapsulation field The advantages that high density, light and short, good heat dissipation performance and good electric property, gradually the Fashion of Future system integration technology The direction of development.Fan-out package technology is just integrated etc. next-generation towards multi-chip, thin encapsulation and three dimension system at present Encapsulation technology direction is developed.

But be fanned out to encapsulation technology at present and still have many problems to be solved, wherein multiple chips integrate rewiring Integrity problem is exactly one of problem.Specifically, due in packaging body a variety of materials thermal expansion coefficient difference it is larger, especially core The coefficient of expansion between the material silicon of piece main body and capsulation material differs larger, therefore on surface where chip and encapsulating material When being rerouted, the effect for suffering from biggish drawing, pressure or shear stress is rerouted, and causes to reroute and crack, is caused Entire packaging failure.It is become apparent when rerouting more narrower, the line width of rewiring is thinner, and (especially line width is less than 5 Micron or less), in same stress state, a possibility that failure, is bigger, this in the high-end chip package of more pins It is to obtain the problem that the packaging of high reliability must overcome through becoming very important problem.

Summary of the invention

Therefore, the technical problem to be solved in the present invention is that, the rewiring solved in existing encapsulating structure is easy in core Under the coefficient of expansion mismatch case of piece and capsulation material and by stress rapture failure, the reliability of encapsulating structure is lower to be asked Topic.

For this purpose, according in a first aspect, the present invention provides a kind of fan-out chip packaging structures, comprising: plastic-sealed body, inside envelope Equipped with an at least chips；The device side of chip is revealed in outside plastic-sealed body；Interconnection layer is set on plastic-sealed body where device side Surface is internally provided with conductive salient point corresponding with the pad of chip；Conductive salient point is for leading to mutually corresponding pad Even layer upper surface；Layer is rerouted, is set on interconnection layer；Layer is rerouted to be electrically coupled with salient point.

Optionally, conductive salient point is vertical with device side.

Optionally, interconnection layer includes dielectric layer and the conductive salient point that is formed in dielectric layer；Wherein, dielectric layer is photosensitive Property photopolymer layer, silicon oxide layer or silicon nitride layer.

Optionally, 1-3 times with a thickness of rewiring thickness degree of interconnection layer.

According to second aspect, the present invention provides a kind of fan-out chip packaging methods, comprising the following steps: provides plastic packaging Body；Wherein, plastic-sealed body enclosed inside has an at least chips；The device side of chip is revealed in outside plastic-sealed body；The device on plastic-sealed body Surface where part face prepares interconnection layer；Interconnection layer is internally provided with salient point corresponding with the pad of chip；Conductive salient point is used In corresponding pad is led to interconnection layer upper surface；Preparation reroutes layer on interconnection layer, reroutes layer and is electrically coupled with salient point.

Optionally, before the step of surface where device side on plastic-sealed body prepares interconnection layer, further includes: in plastic-sealed body Temporary base is mounted on the surface of device side far from chip.

It optionally, include: the device on plastic-sealed body the step of the surface where device side on plastic-sealed body prepares interconnection layer Surface where face forms dielectric layer；The blind hole for appearing the pad of chip is formed in the dielectric layer；Conduction material is filled in blind hole Material forms conductive salient point, to prepare interconnection layer.

Optionally, dielectric layer is photosensitive dry film layer, silicon oxide layer or silicon nitride layer.

Optionally, 1-3 times with a thickness of rewiring thickness degree of interconnection layer.

Technical solution provided by the invention, has the advantages that

1, fan-out chip packaging structure provided by the invention is set by the surface where the device side of chip on plastic-sealed body Interconnection layer is set, and pad is led to by table on interconnection layer by the conductive salient point being arranged corresponding to the pad of chip inside interconnection layer Face makes interconnection layer surfaces upward wiring of the rewiring interconnected with conductive salient point in single material, the shadow from bottom interface stress Sound is just smaller, simultaneously as the interconnection layer being arranged between layer and plastic-sealed body is rerouted, so that the interfacial stress of plastic-sealed body and chip There is reduction by a relatively large margin after stopping by interconnection layer, so that rerouting stress suffered by layer can greatly subtract It is small, even if narrower reroute is influenced and a possibility that fatigue fracture is greatly reduced by interfacial stress, improve the encapsulation knot The reliability of structure.

2, fan-out chip packaging structure provided by the invention, by the way that the device side of conductive salient point and chip is vertically arranged, The conductive salient point is set to be parallel to the interface of the close conductive salient point of the intracorporal chip of plastic packaging, namely to be parallel to two kinds of coefficients of expansion poor Interface between different biggish material, suffered tension and compression or shear stress are just smaller, and reliability is higher, meanwhile, with chip The vertically disposed conductive salient point of device side can be realized the electricity of the pad of chip and the rewiring layer shortest distance of interconnection layer surfaces Coupling, so as to further increase the reliability of the encapsulating structure.

3, fan-out chip packaging structure provided by the invention reroutes thickness degree by setting the thickness of interconnection layer to 1-3 times namely interconnection layer will have certain thickness, guarantee that interconnection layer can carry external stress influence, so that position It is minimized in the rewiring layer on interconnection layer by internal stress influence caused by physical property difference between different materials, into one Step reduces a possibility that rerouting fracture failure, improves the reliability of the encapsulating structure.

4, fan-out chip packaging method provided by the invention is interconnected by preparing in the device side of chip on plastic-sealed body Layer, and be arranged inside the interconnection layer for corresponding pad to be led to interconnection layer upper surface conductive salient point, conductive salient point It draws from pad and is electrically coupled with rewiring, walk the rewiring interconnected with conductive salient point on the interconnection layer surfaces of single material Line, the influence from bottom interface stress is just smaller, is provided with interconnection layer between layer and plastic-sealed body simultaneously as rerouting, makes Stress caused by the interface of plastic-sealed body and chip is obtained by there is reduction by a relatively large margin after interconnection layer, so that weight cloth Stress suffered by line layer can greatly reduce, even if narrower reroute the possibility for being led to fatigue fracture by interfacial stress Property is greatly reduced, and improves the reliability of the encapsulating structure.

Detailed description of the invention

It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor It puts, is also possible to obtain other drawings based on these drawings.

Fig. 1 is a kind of structural schematic diagram for fan-out chip packaging structure that embodiment 1 provides；

Fig. 2 is a kind of a kind of process flow chart for fan-out chip packaging method that embodiment 2 provides；

The structural schematic diagram that Fig. 3 is presented for step S201 in execution embodiment 2；

The structural schematic diagram that Fig. 4 and Fig. 5 is presented for step S202 in execution embodiment 2；

The structural schematic diagram that Fig. 6 is presented for step S204 in execution embodiment 2；

Description of symbols:

1- plastic-sealed body；11- chip；12- plastic packaging layer；2- interconnection layer；21- conductive salient point；210- blind hole；22- dielectric layer；3- Reroute layer；4- substrate；41- first is temporarily bonded glue；5- temporary base；51- second is temporarily bonded glue.

Specific embodiment

Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship of the instructions such as term " on ", "lower" is base In orientation or positional relationship shown in the drawings, it is merely for convenience of description of the present invention and simplification of the description, rather than indication or suggestion Signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to this The limitation of invention.In addition, term " first ", " second ", " third " are used for description purposes only, it is not understood to indicate or imply Relative importance.