阅读说明：本技术 集成布线转接板的新型芯片封装结构 (Novel chip packaging structure of integrated wiring adapter plate ) 是由 张孝忠 于 2021-10-11 设计创作，主要内容包括：本申请公开了一种集成布线转接板的新型芯片封装结构,包括集成布线转接板,集成布线转接板包括外框,外框底部布设内外连导丝,内外连导丝一端连接外板引脚接点,内外连导丝另外一端连接芯片引脚接点和固定胶层,芯片引脚接点和固定胶层下部连接芯片本体的边缘,并且芯片引脚接点与芯片本体的引脚电连接,芯片引脚接点与固定胶层上贯穿设置一个第一预留风孔,第一预留风孔一端靠近芯片本体的几何中心,第一预留风孔另外一端靠近外板引脚接点,第一预留风孔具体配置：第一预留风孔的竖直向截面上下边界线均与水平线相交。本申请还公开了集成布线转接板的新型芯片封装结构的制作方法。(The application discloses novel chip package structure of integrated wiring keysets, including the integrated wiring keysets, the integrated wiring keysets includes the frame, the frame bottom is laid inside and outside even seal wire, planking pin contact is connected to inside and outside even seal wire one end, inside and outside even seal wire other end is connected chip pin contact and fixed glue film, the edge of chip pin contact and fixed glue film sub-unit connection chip body, and chip pin contact is connected with the pin electricity of chip body, run through on chip pin contact and the fixed glue film and set up a first reservation wind hole, first reservation wind hole one end is close to the geometric centre of chip body, first reservation wind hole other end is close to planking pin contact, first reservation wind hole concrete disposition: the upper boundary line and the lower boundary line of the vertical section of the first reserved air hole are intersected with the horizontal line. The application also discloses a manufacturing method of the novel chip packaging structure of the integrated wiring adapter plate.)

1. The utility model provides a novel chip package structure of integrated wiring keysets, includes the integrated wiring keysets, the integrated wiring keysets include the frame, frame bottom lay inside and outside even seal wire, inside and outside even seal wire one end connect planking pin contact, inside and outside even seal wire other one end connect chip pin contact and fixed glue film, a serial communication port, chip pin contact and the edge of fixed glue film sub-unit connection chip body, and chip pin contact be connected with the pin electricity of chip body, chip pin contact and fixed glue film on run through and set up a first reservation wind hole, first reservation wind hole one end be close to the geometric centre of chip body, the other one end of first reservation wind hole be close to planking pin contact, first reservation wind hole concrete disposition: the vertical boundary line all intersects with the water flat line about to the cross-section of first reservation wind hole, first reservation wind hole do not destroy the vertical to electric conductivity of chip pin joint when running through chip pin joint, first reservation wind hole do not destroy the vertical to fixed bolster function of fixed glue film when running through fixed glue film, in the encapsulation fixed glue film be close to planking pin joint one side still set up the protection adhesive tape layer.

2. The novel chip packaging structure of the integrated wiring adapter plate as claimed in claim 1, wherein the first reserved air holes are further specifically configured to: the first reserved air hole is vertically downwards inclined towards one end of the upper boundary line of the cross section close to the geometric center of the chip body, and the first reserved air hole is also vertically downwards inclined towards one end of the lower boundary line of the cross section close to the geometric center of the chip body.

3. The novel chip packaging structure of an integrated wiring adapter plate as claimed in claim 2, wherein an inner sealant layer is disposed on the upper portion of the outer frame, and the upper portion of the inner sealant layer is connected to the flip-chip protection plate.

4. The novel chip packaging structure of the integrated wiring adapter plate as claimed in claim 3, wherein a reserved groove is formed on one side of the inner sealant layer close to the geometric center of the chip body in a penetrating manner, a second reserved air hole is formed in the outer frame on the lower portion of the reserved groove, and the second reserved air hole penetrates through the outer frame.

5. The novel chip packaging structure of the integrated wiring adapter plate as claimed in claim 4, wherein one end of the second reserved air hole is close to the geometric center of the chip body, the other end of the second reserved air hole is close to the reserved groove, and the second reserved air hole is specifically configured as follows: the vertical upper and lower boundary lines of the cross section of the second reserved air hole are intersected with the horizontal line, the second reserved air hole does not damage the vertical frame supporting function of the outer frame and the whole stress of the outer frame when penetrating through the outer frame, and the second reserved air hole is also specifically configured: the upper boundary line of the vertical direction section of the second reserved air hole is downwards inclined at one end close to the geometric center of the chip body, and the lower boundary line of the vertical direction section of the second reserved air hole is also downwards inclined at one end close to the geometric center of the chip body.

6. The novel chip packaging structure of the integrated wiring adapter plate as claimed in claim 5, wherein an outer sealant layer is disposed between the flip-chip protection plate and the inner sealant layer, and a part of the outer sealant layer is filled in the preformed groove during packaging.

7. The novel chip package structure of an integrated wiring interposer as claimed in claim 6, wherein when the chip body is an electromagnetic wave-based sensor chip, the flip-chip protection plate is made of an electromagnetic-permeable material.

8. The novel chip packaging structure of the integrated wiring adapter plate as claimed in claim 7, wherein when the chip body is a visible light sensor chip, the flip-chip protection plate is made of glass, and a thermochromic layer is embedded in the flip-chip protection plate and is doped with silver tetraiodomercuric oxide.

9. The novel chip packaging structure of integrated wiring adapter board as claimed in claim 2, wherein said first pre-formed air hole is configured such that the upper boundary line of the vertical direction cross section of said first pre-formed air hole is inclined downward at the end near the geometric center of the chip body, the lower boundary line of the vertical direction cross section of said first pre-formed air hole is also inclined downward at the end near the geometric center of the chip body, a point a of the geometric center is marked on the upper surface of the chip body, a reference direction is selected on the side of the point a of the upper surface of the chip body as a positive direction, the direction opposite to the positive direction is a negative direction, a point of a unit distance is selected in the positive direction with the point a as an origin point as a first positive distance point and marked as a point d, a point of a unit distance is selected in the negative direction with the point a as an origin point as a first negative distance point and marked as an e point, and the port of the first pre-formed air hole closest to the pin connection point of the outer board is selected as an outer reference port, the highest point of the outer reference port is labeled p5 and the lowest point of the outer reference port is labeled p 6; a reference line f5 is formed by connecting the point p5 with the point d, and a line segment of the reference line f5 passing through the pin joint of the chip and the fixed glue layer is the upper boundary line of the vertical section of the first reserved air hole; a reference line f6 is formed by connecting the point p6 with the point e, and a line segment of the reference line f6 passing through the pin joint of the chip and the fixed glue layer is the lower boundary line of the vertical section of the first reserved air hole; and arranging a second reserved air hole on the outer frame according to the determined upper and lower boundary lines.

Technical Field

The invention relates to the field of semiconductor packaging, in particular to a novel chip packaging structure of an integrated wiring adapter plate and a manufacturing method thereof.

Background

Most of the existing chip packaging structures of the integrated wiring adapter plate are applied to packaging of sensor chips, and because the packaging of the sensor chips needs high cleanliness requirement, the chip packaging of the integrated wiring adapter plate needs to strictly control pollution sources such as dust, and although many related technologies are adopted in the prior art, such as technologies of high-cleanness working environment and the like, the pollution sources such as dust and the like in the chip packaging details can still be avoided, and the pollution sources are substantially caused by the fact that the integrated wiring adapter plate participates in packaging.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a novel chip packaging structure of an integrated wiring adapter plate and a manufacturing method thereof.

The technical scheme adopted by the invention for solving the technical problems is as follows: the utility model provides a novel chip package structure of integrated wiring keysets, includes the integrated wiring keysets, the integrated wiring keysets include the frame, frame bottom lay inside and outside even seal wire, inside and outside even seal wire one end connect planking pin contact, inside and outside even seal wire other one end connect chip pin contact and fixed glue film, chip pin contact and the edge of fixed glue film sub-unit connection chip body, and chip pin contact be connected with the pin electricity of chip body, chip pin contact and fixed glue film on run through and set up a first reservation wind hole, first reservation wind hole one end be close to the geometric centre of chip body, the other one end of first reservation wind hole be close to planking pin contact, first reservation wind hole concrete disposition: the vertical boundary line all intersects with the water flat line about to the cross-section of first reservation wind hole, first reservation wind hole do not destroy the vertical to electric conductivity of chip pin joint when running through chip pin joint, first reservation wind hole do not destroy the vertical to fixed bolster function of fixed glue film when running through fixed glue film, in the encapsulation fixed glue film be close to planking pin joint one side still set up the protection adhesive tape layer.

Further, the first reserved air hole is also specifically configured: the first reserved air hole is vertically downwards inclined towards one end of the upper boundary line of the cross section close to the geometric center of the chip body, and the first reserved air hole is also vertically downwards inclined towards one end of the lower boundary line of the cross section close to the geometric center of the chip body.

Further, frame upper portion set up interior glue sealing layer, interior glue sealing layer upper portion connect the flip-chip backplate.

Furthermore, one side of the inner sealing adhesive layer, which is close to the geometric center of the chip body, is provided with a reserved groove in a penetrating mode, a second reserved air hole is formed in the outer frame at the lower portion of the reserved groove, and the second reserved air hole penetrates through the outer frame.

Further, second reservation wind hole one end be close to the geometric centre of chip body, the other end of second reservation wind hole be close to the reservation recess, the second reservation wind hole concrete disposition: the vertical upper and lower boundary lines of the cross section of the second reserved air hole are intersected with the horizontal line, the second reserved air hole does not damage the vertical frame supporting function of the outer frame and the whole stress of the outer frame when penetrating through the outer frame, and the second reserved air hole is also specifically configured: the upper boundary line of the vertical direction section of the second reserved air hole is downwards inclined at one end close to the geometric center of the chip body, and the lower boundary line of the vertical direction section of the second reserved air hole is also downwards inclined at one end close to the geometric center of the chip body.

Further, an outer sealing adhesive layer is arranged between the inverted protective plate and the inner sealing adhesive layer, and a part of the outer sealing adhesive layer is filled in the reserved groove in the packaging process.

Further, when the chip body be based on the sensing chip of electromagnetic wave, flip-chip backplate adopt the material that has electromagnetic penetrability.

Furthermore, when the chip body adopts a visible light sensing chip, the inverted guard plate is made of glass, a thermochromatic layer is embedded in the inverted guard plate, and the thermochromatic layer adopts doped silver tetraiodomercuric acid.

Further, configuring that 'the upper boundary line of the vertical direction section of the first reserved air hole is inclined downwards at one end close to the geometric center of the chip body, the lower boundary line of the vertical direction section of the first reserved air hole is also inclined downwards at one end close to the geometric center of the chip body', specifically, marking a point a of the geometric center on the upper surface of the chip body, selecting a reference direction as a positive direction on one side of the point a of the upper surface of the chip body, taking the direction opposite to the positive direction as a negative direction, selecting a point of a unit distance in the positive direction by taking the point a as an origin as a first positive distance point and marking the point d as a point d, selecting a point of a unit distance in the negative direction by taking the point a as the origin as a first negative distance point and marking the point e as an outer reference port, and marking the highest point of the outer reference port as p5, the lowest point of the outer reference port is labeled p 6; a reference line f5 is formed by connecting the point p5 with the point d, and a line segment of the reference line f5 passing through the pin joint of the chip and the fixed glue layer is the upper boundary line of the vertical section of the first reserved air hole; a reference line f6 is formed by connecting the point p6 with the point e, and a line segment of the reference line f6 passing through the pin joint of the chip and the fixed glue layer is the lower boundary line of the vertical section of the first reserved air hole; and arranging a second reserved air hole on the outer frame according to the determined upper and lower boundary lines.

The invention has the advantages that in the chip body packaging, the chip body is firstly fixed, then the chip pin contact and the fixing glue layer are arranged at the edge of the chip body, then the first fan is started to enable the first fan to enter the first reserved air hole and then reach the geometric center area on the upper surface of the chip body to form air flow, the air flow forms upward branch flow on the upper side of the geometric center of the chip body, two or more groups of symmetrical air flow forming structures are arranged on the periphery of the corresponding chip body, therefore, in the subsequent packaging of the structures such as the internal and external connecting guide wires, the outer frame and the like, the upper layer of the chip body can be kept free from pollution sources such as dust and the like through continuous wind flow, and after the inner sealing glue layer and the inverted protection plate are packaged, a protective sealing glue layer is arranged on one side, close to the pin joint of the outer plate, of the fixed glue layer to seal the first reserved air hole, so that the first reserved air hole can be prevented from secondary pollution.

Drawings

Fig. 1 is a schematic vertical cross-sectional structure diagram of an embodiment of a novel chip packaging structure of an integrated wiring interposer according to the present application.

Fig. 2 is a schematic vertical cross-sectional structure diagram of another embodiment of the novel chip packaging structure of the integrated wiring interposer of the present application.

Fig. 3 is a schematic diagram illustrating a configuration of a vertical upper boundary line of a section of a first reserved air hole 201 of the novel chip packaging structure of the integrated wiring interposer according to the present application.

Fig. 4 is a schematic diagram illustrating a configuration of the second reserved air holes 106 of the novel chip packaging structure of the integrated wiring interposer according to the present application, which is vertically arranged toward the upper boundary of the cross section.

FIG. 5 is a schematic view of wind flow in the practice of the present application.

Fig. 6 is a schematic overall vertical cross-sectional configuration of the fig. 2 embodiment of the present application.

In the figure: 101-flip guard board; 102-outer sealant layer; 103-inner sealant layer; 104-reserving a groove; 105-an outer frame; 106-second reserved air holes; 107-internal and external connecting guide wires; 108-chip pin contacts; 109-fixing the adhesive layer; 110-protective sealant layer; 111-outer plate pin contacts; 201-a first reserved air hole; 200-a chip body; 205-a second fan; 206-first fan.

Detailed Description

In specific implementation, the embodiment of the novel chip packaging structure of the integrated wiring adapter plate of the present application, as shown in fig. 1, includes an integrated wiring adapter plate, the integrated wiring adapter plate includes an outer frame 105, an inner and outer connecting wire 107 is arranged at the bottom of the outer frame 105, one end of the inner and outer connecting wire 107 is connected to an outer plate pin contact 111, the other end of the inner and outer connecting wire 107 is connected to a chip pin contact 108 and a fixing glue layer 109, the lower portion of the chip pin contact 108 and the fixing glue layer 109 is connected to the edge of a chip body 200, the chip pin contact 108 is electrically connected to a pin of the chip body 200, a first reserved air hole 201 is arranged on the chip pin contact 108 and the fixing glue layer 109 in a penetrating manner, one end of the first reserved air hole 201 is close to the geometric center of the chip body 200, the other end of the first reserved air hole 201 is close to the outer plate pin contact 111, the first reserved air hole 201 is specifically configured as follows: the upper boundary line and the lower boundary line of the vertical section of the first reserved air hole 201 are intersected with the horizontal line, the vertical conductivity of the chip pin joint 108 is not damaged when the first reserved air hole 201 penetrates through the chip pin joint 108, the vertical fixing and supporting functions of the fixing adhesive layer 109 are not damaged when the first reserved air hole 201 penetrates through the fixing adhesive layer 109, and a protective adhesive sealing layer 110 is further arranged on one side, close to the outer plate pin joint 111, of the fixing adhesive layer 109 in packaging; the upper part of the outer frame 105 is provided with an inner sealant layer 103, and the upper part of the inner sealant layer 103 is connected with the inverted guard plate 101.

The overall structure of an embodiment of the novel chip package structure of the integrated wiring interposer of the present application is shown with reference to fig. 6 for ease of understanding.

In implementation, as shown in fig. 5, a first fan 206 is further configured in the packaging process of the present application, and the first fan 206 is disposed outside the chip body 200; in the packaging of the chip body 200, the chip body 200 is firstly fixed, then the chip pin contacts 108 and the fixing adhesive layer 109 are arranged at the edge of the chip body 200, then, the first fan 206 is started to enable the first fan 206 to enter the first reserved air hole 201 and then form air flow in the geometric center area on the upper surface of the chip body 200, the air flow forms upward branch flow on the upper side of the geometric center of the chip body 200, two or more groups of symmetrical air flow forming structures are arranged on the periphery of the corresponding chip body 200, therefore, in the subsequent packaging of the internal and external connecting wires 107, the outer frame 105 and other structures, the upper layer of the chip body 200 can be kept free from pollution sources such as dust through continuous wind flow, and after the inner sealant layer 103 and the inverted guard plate 101 are packaged, a protective sealant layer 110 is arranged on one side of the fixed sealant layer 109 close to the outer plate pin joint 111 to seal the first reserved air hole 201, so that the first reserved air hole 201 can avoid secondary pollution.

Therefore, in implementation, the method for manufacturing the novel chip packaging structure of the integrated wiring patch panel of the present application includes the steps of: the chip pin contacts 108 and the fixing glue layer 109 are arranged on the edge of the chip body 200, then the first fan 206 is started to enable the first fan 206 to enter the first reserved air holes 201 and then form air flow in the geometric center area above the chip body 200, the air flow forms upward branch flow on the upper side of the geometric center of the chip body 200, two or more groups of symmetrical air flow forming structures are arranged on the periphery of the corresponding chip body 200, then the upper layer of the chip body 200 is kept free of pollution sources such as dust through continuous air flow in other packaging processes, and after the inner sealing glue layer 103 and the inverted protective plate 101 are packaged, the protecting glue layer 110 is arranged on one side, close to the outer plate pin contacts 111, of the fixing glue layer 109 to seal the first reserved air holes 201.

In addition, in the implementation, preferably, before the encapsulation of the flip-chip protection plate 101 is completed, the protection sealing adhesive layer 110 is arranged on one side, close to the pin connection points 111 of the outer plate, of the fixing adhesive layer 109 to seal the first reserved air hole 201, and then the flip-chip protection plate 101 is encapsulated, so that short-time negative pressure can be formed instantly when the protection sealing adhesive layer 110 is arranged to seal the first reserved air hole 201, the short-time negative pressure is caused by air flow, and thus, a part of the protection sealing adhesive layer 110 overflows into the first reserved air hole 201 to be fully sealed.

The utility model provides an integrated wiring adapter plate's novel chip package structure's embodiment first reservation wind hole 201 still specifically dispose: the vertical upper boundary line of the section of the first reserved air hole 201 is inclined downwards at one end close to the geometric center of the chip body 200, and the vertical lower boundary line of the section of the first reserved air hole 201 is also inclined downwards at one end close to the geometric center of the chip body 200, so that the first fan 206 is started to enable the first fan 206 to enter the first reserved air hole 201 and then form air flow in the geometric center area above the chip body 200.

The utility model provides an embodiment of the novel chip package structure of integrated wiring adapter plate is shown in fig. 2, interior adhesive tape layer 103 on be close to one side of the geometric centre of chip body 200 and run through and set up a reservation recess 104, frame 105 of reservation recess 104 lower part on set up a second and reserve wind hole 106, second reserve wind hole 106 run through frame 105, more specific implementation, second reserve wind hole 106 one end and be close to the geometric centre of chip body 200, the second reserve wind hole 106 other one end and be close to reservation recess 104, second reserve wind hole 106 concrete configuration: the upper and lower boundary lines of the vertical section of the second reserved air hole 106 are intersected with the horizontal line, the second reserved air hole 106 does not damage the vertical frame supporting function of the outer frame 105 and the whole stress of the outer frame 105 when penetrating through the outer frame 105, and the second reserved air hole 106 is also specifically configured: in further implementation, an outer sealant layer 102 is arranged between the flip-chip protection plate 101 and the inner sealant layer 103, and a part of the outer sealant layer 102 is filled into the reserved groove 104 in the packaging process; the overall structure of an embodiment of the novel chip package structure of the integrated wiring interposer of the present application is shown with reference to fig. 6 for ease of understanding.

In the implementation, referring to the first implementation and the implementation flow thereof, the second blower 205 is disposed on one side of the outer frame 105 before the inner sealant layer 103 is packaged, thus, as shown in fig. 5, the second fan 205 is first turned on, so that the second fan 205 enters the second reserved air hole 106 and then enters the geometric center area on the chip body 200 to form an air current, the air current also forms an upward branch on the upper side of the geometric center of the chip body 200, two or more groups of symmetrical air current forming structures are circumferentially arranged on the corresponding chip body 200, therefore, in the subsequent packaging of the structure such as the inner sealant layer 103 and the like, the upper layer of the chip body 200 can be kept free from pollution sources such as dust through continuous wind flow, and the outer sealant layer 102 is packaged after the inner sealant layer 103 is packaged, so that the redundant outer sealant layer 102 can seal the second reserved air hole 106 through the reserved groove 104, and the second reserved air hole 106 can avoid secondary pollution.

Especially, the arrangement of the second reserved air holes 106 can actually increase the air source of the first reserved air holes 201, which generates air flow, so that the area of the upper air flow of the chip body 200 can be increased, and the anti-pollution effect is improved.

The utility model discloses a novel chip packaging structure of integrated wiring adapter plate works as when chip body 200 be based on the sensing chip of electromagnetic wave, flip-chip backplate 101 adopt the material that has electromagnetic penetrability, for example in specific one is implemented, when chip body 200 adopt the visible light sensing chip, flip-chip backplate 101 adopt and have the glass material, and flip-chip backplate 101 in inlay and set up the thermochromism layer, the thermochromism layer adopt doped tetraiodomercuric acid silver, other structure material of this application select can adopt the material among the prior art in addition, the thermochromism layer of this application in the implementation can specifically set up in flip-chip backplate 101 and the juncture of outer glue layer 102, can roughly judge chip operating condition through the colour change of thermochromism layer in the implementation to can roughly judge the working life or the work function of chip through the data of thermochromism layer colour change rate in the implementation, the specific method is determined according to the relation between the thermal efficiency and the service life of the chip.

In a more specific implementation, in the present application, specifically, the first reserved air hole 201 is vertically inclined downward toward the upper boundary line of the cross section at one end close to the geometric center of the chip body 200, and the first reserved air hole 201 is also vertically inclined downward toward the lower boundary line of the cross section at one end close to the geometric center of the chip body 200, as shown in fig. 3, a point a of the geometric center is marked on the upper surface of the chip body 200, a reference direction is selected as a positive direction on one side of the point a of the upper surface of the chip body 200, a direction opposite to the positive direction is a negative direction, a point of a unit distance is selected as a point d of a positive distance in the positive direction with the point a as an origin, a point of a unit distance is selected as a point e of a negative distance, an orifice of the first reserved air hole 201 closest to the outer board pin junction 111 is selected as an outer reference port, the highest point of the outer reference port is labeled p5 and the lowest point of the outer reference port is labeled p 6; a reference line f5 is formed by connecting the point p5 with the point d, and a line segment of the reference line f5 passing through the chip pin joint 108 and the fixing glue layer 109 is an upper boundary line of the vertical section of the first reserved air hole 201; a reference line f6 is formed by connecting the point p6 with the point e, and a line segment of the reference line f6 passing through the chip pin joint 108 and the fixing glue layer 109 is a vertical lower boundary line of the section of the first reserved air hole 201; and a second reserved air hole 106 is formed in the outer frame 105 according to the determined upper and lower boundary lines.

In the configuration of the present application, "the second reserved air hole 106 is inclined downward at an end close to the geometric center of the chip body 200 toward the vertical upper boundary line of the cross section, and the second reserved air hole 106 is also inclined downward at an end close to the geometric center of the chip body 200 toward the vertical lower boundary line of the cross section," specifically, reference may also be made to the configuration of the first reserved air hole 201, and a specific configuration schematic diagram is shown in fig. 4.