阅读说明：本技术 功率基板及具备该功率基板的高电压模块 (Power substrate and high-voltage module provided with same ) 是由 西冈圭 花田俊雄 中村孝 舟木刚 于 2020-03-26 设计创作，主要内容包括：本发明的功率基板(101)具备：多个绝缘基板(106),其沿着在同一方向上延伸的多个电流路径(P)排列配置；多个MOS晶体管(108),其经由第一导电层(107)、第一焊料接合层(109)搭载在多个绝缘基板(106)的一个主面上；以及散热部件(108),其经由第二导电层(107)、第二焊料接合层(109)与全部的所述绝缘基板的另一个主面接触,其中,一个一个的电流路径(P)由搭载在不同的绝缘基板(106)上的单个或多个MOS晶体管(108)彼此串联连接而形成。(A power substrate (101) is provided with: a plurality of insulating substrates (106) arranged in a row along a plurality of current paths (P) extending in the same direction; a plurality of MOS transistors (108) mounted on one main surface of the plurality of insulating substrates (106) via a first conductive layer (107) and a first solder bonding layer (109); and a heat dissipation member (108) that is in contact with the other main surface of all the insulating substrates via a second conductive layer (107) and a second solder bonding layer (109), wherein one current path (P) is formed by connecting one or more MOS transistors (108) mounted on different insulating substrates (106) in series.)

1. A power board is characterized by comprising:

a plurality of insulating substrates arranged along a plurality of current paths extending in the same direction;

a plurality of MOS transistors mounted on one main surface of the insulating substrates via a first conductive layer and a first solder bonding layer; and

a heat dissipation member in contact with the other main surface of the insulating substrate via a second conductive layer and a second solder bonding layer,

wherein one of the current paths is formed by connecting one or more of the MOS transistors mounted on different insulating substrates in series with each other.

2. The power substrate according to claim 1, wherein a resistor is provided between the adjacent insulating substrates, and the resistor is connected in parallel to the MOS transistor.

3. A high-voltage module is formed by sequentially stacking:

the power substrate of claim 1;

a gate drive substrate on which a plurality of gate drive circuit elements of the MOS transistors are mounted;

a power supply substrate formed with a plurality of coils on both sides with an insulating member interposed therebetween; and

a control unit that simultaneously controls on/off of a plurality of the gate drive circuit elements,

the MOS transistor is electrically connected with the gate drive circuit element, the gate drive circuit element is electrically connected with the coil, and the gate drive circuit element is electrically connected with the control unit.

4. High voltage module according to claim 3,

the control unit includes:

a CPLD substrate on which an EO converter for transmitting an optical signal for on/off control to the gate driver circuit element is mounted; and

an O/E substrate having an OE converter for receiving the optical signal and converting the optical signal into an electrical signal,

wherein the OE converter in the control unit is electrically connected to the gate drive circuit element.

[ technical field ]

The present invention relates to a power board and a high-voltage module including the same.

The present application claims priority based on Japanese application No. 2019-061598 filed on 27.3.2019, the contents of which are incorporated herein.

[ background art ]

It is known that the band gap of SiC is 3 times larger than Si and the dielectric breakdown strength of SiC is about 10 times higher than Si, and a semiconductor device such as a MOS transistor using SiC is attracting attention as a next-generation power device that handles high voltage and large current. In accordance with various applications, a high-voltage module has been developed in which a plurality of MOS transistors are combined to improve switching characteristics, withstand voltage characteristics, temperature characteristics, and the like (see, for example, patent document 1).

[ Prior art documents ]

Patent document

Patent document 1: japanese patent laid-open publication No. 2015-162845

[ summary of the invention ]

Problems to be solved by the invention

A plurality of MOS transistors constituting the high voltage module are directly mounted on the printed substrate in a discrete state, and they are connected in series with each other. In this state, since the heat of the mounted MOS transistor cannot be sufficiently dissipated, the magnitude of the current flowing through the MOS transistor has to be limited.

Further, since the gates of the MOS transistors in the high-voltage module are configured to be driven individually by an electromagnetic induction method, gate delay variation between a plurality of MOS transistors connected in series is large, and it is difficult to use them in combination.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a power substrate and a high-voltage module including the power substrate, which can improve heat dissipation and suppress gate delay variation to a low level.

Means for solving the problems

In order to solve the above problems, the present invention adopts the following means.

(1) A power board according to an aspect of the present invention includes: a plurality of insulating substrates arranged along a plurality of current paths extending in the same direction; a plurality of MOS transistors mounted on one main surface of the insulating substrates via a first conductive layer and a first solder bonding layer; and a heat dissipation member that is in contact with the other main surface of all the insulating substrates via a second conductive layer and a second solder bonding layer, wherein the current path of one of the MOS transistors is formed by connecting one or a plurality of the MOS transistors mounted on different insulating substrates in series. The solder bonding may be a sintering-type bonding material (silver sintering, copper sintering, or the like), a conductive resin, or the like.

(2) In the power substrate described in (1), it is preferable that a resistor is provided between the adjacent insulating substrates, and the resistor is connected in parallel to the MOS transistor.

(3) A high-voltage module according to an aspect of the present invention is formed by stacking the following components in this order: the power substrate of (1); a gate drive substrate on which a plurality of gate drive circuit elements of the MOS transistors are mounted; a power supply substrate formed with a plurality of coils on both sides with an insulating member interposed therebetween; and a control unit that simultaneously controls on/off of the plurality of gate drive circuit elements, wherein the MOS transistor is electrically connected to the gate drive circuit element, the gate drive circuit element is electrically connected to the coil, and the gate drive circuit element is electrically connected to the control unit.

(4) Preferably, in the high voltage module according to (3), the control unit includes: a CPLD substrate on which an EO converter for transmitting an optical signal for on/off control to the gate driver circuit element is mounted; and an O/E substrate including an OE converter that receives the optical signal and converts the optical signal into an electrical signal, wherein the OE converter in the control unit is electrically connected to the gate driver circuit element.

[ Effect of the invention ]

In the power substrate of the present invention, the insulating substrate on which the MOS transistor is mounted is in contact with the heat dissipation member, and therefore, the heat dissipation can be improved as compared with a conventional MOS transistor mounted in a discrete state. In the high-voltage module including the power board according to the present invention, the plurality of gate driver circuit elements are connected to one control unit, and the gate driver circuit elements can be controlled simultaneously. Therefore, the gate signal can be simultaneously input to each of the plurality of MOS transistors connected in series via the gate driver circuit element, and the gate delay variation between the MOS transistors can be suppressed to be low.

[ brief description of the drawings ]

Fig. 1 is a sectional view of a high-voltage module according to an embodiment of the present invention.

Fig. 2 is a perspective view of a power substrate constituting the high voltage module of fig. 1.

Fig. 3(a) is a cross-sectional view of the power substrate of fig. 2. (b) And (c) is a diagram of a modified example of the power substrate of (a).

Fig. 4 is an equivalent circuit diagram of a current path formed in the power substrate of fig. 2.

Fig. 5 is a plan view of a power supply substrate constituting the high voltage module of fig. 1.

[ detailed description of the invention ]

Hereinafter, a power board and a high-voltage module including the power board according to an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings used in the following description, for convenience of understanding of features, the features may be enlarged and shown, and the dimensional ratios of the components are not necessarily the same as the actual ones. The materials, dimensions, and the like described in the following description are examples, and the present invention is not limited thereto, and can be appropriately modified and implemented within a range not changing the gist thereof.

Fig. 1 is a sectional view of a high voltage module 100 according to an embodiment of the present invention. The high-voltage module 100 is mainly formed by sequentially stacking a power substrate 101, a gate drive substrate 102, a power supply substrate 103, and a control unit 104 in the thickness direction thereof. More specifically, the resin 105 is sandwiched between the power substrate 101 and the gate drive substrate 102, between the gate drive substrate 102 and the power supply substrate 103, and between the power supply substrate 103 and the control unit 104.

The power substrate 101 is a substrate on which a functional element such as a MOS transistor is mounted, and includes a heat dissipation member having a large area, and is preferably disposed at the lowermost layer of the high voltage module 100 as shown in fig. 1. The power substrate 101 includes: a plurality of insulating substrates 106; a plurality of functional elements (chips) such as MOS transistors 108 mounted on one main surface of the insulating substrate 106 via a conductive layer 107 (first conductive layer) and a solder bonding layer 109 (first solder bonding layer); and a heat dissipation member (heat sink) 110 that is in contact with the other principal surface of all the insulating substrates 106 via the conductive layer 107 (second conductive layer) and the solder bonding layer 109 (second solder bonding layer). Here, functional elements other than the MOS transistor 108 are not shown.

The insulating substrate 106 is mainly made of alumina (Al)₂O₃) Aluminum nitride (AlN), silicon nitride (Si)₃N₄) Etc. of an insulating material. The conductive layer 107 is mainly made of a conductive material such as copper or aluminum. The surface of conductive layer 107 may also be plated with nickel, silver, or the like.

Fig. 2 is a perspective view of the power substrate 101. The insulating substrates 106 extend along a plurality of current paths P (P) extending in parallel in the same direction₁、P₂、…、P_n) And (4) arranging and configuring. In fig. 2, n is 3, but may be less than 3 or 4 or more. One end of each of the current paths P is connected to a common input terminal (not shown), and the other end thereof is connected to a common output terminal (not shown). In addition, the same party hereThe term "in the direction" refers to a direction connecting a common input terminal and output terminal, and the extending directions of the plurality of current paths P may not be aligned parallel in a geometric sense.

Fig. 3(a) is a cross-sectional view of the power substrate 101 of fig. 2 cut by a plane passing along the α - α line. One by one current path P₁、P₂、…、P_nThe MOS transistors 108 are formed by connecting one or more (4 in this case) MOS transistors 108 in series among the MOS transistors 108 mounted on different insulating substrates 106. That is, a single or a plurality of MOS transistors mounted on the same insulating substrate 106 are connected in series with a single or a plurality of MOS transistors mounted on another insulating substrate 106. Here, although the case where one current path P is formed by 16 MOS transistors 108 is exemplified, the number of MOS transistors 108 connected in series is not limited.

Fig. 3(b) and (c) are diagrams illustrating a modification of the power substrate 101 illustrated in fig. 3 (a).

In fig. 3(a), the case where the number of MOS transistors belonging to the same current path P among the MOS transistors 108 mounted on the same insulating substrate 106 is 4 is illustrated, but the number is not limited to this.

For example, as shown in fig. 3(b), the number of MOS transistors 108 mounted on the same insulating substrate 106 and belonging to the same current path P may be increased. In this case, the insulating substrate 106 becomes large, and thus assembly is easy. Conversely, as shown in fig. 3(c), the number of MOS transistors 108 mounted on the same insulating substrate 106 and belonging to the same current path P may be reduced. In this case, since the insulating substrate 106 is small, the cost can be kept low, and the occurrence of cracking and warping can be kept low.

The MOS transistors 108 constituting the same current path P have a series relationship with each other, and the MOS transistors 108 constituting different current paths P have a parallel relationship with each other. The MOS transistors 108 mounted on different insulating substrates 106 have a series relationship with each other, and the MOS transistors 108 mounted on the same insulating substrate 106 have a parallel relationship with each other.

If the number of series connections is set to m, the MOS transistors 108 are arranged so as to form a matrix structure of m × n. The current path P here exemplifies a case of having a U shape including a folded portion, but may have a straight shape not including a folded portion in a case where the number of MOS transistors 108 is small.

Fig. 4 is a diagram of one current path (P) among a plurality of current paths P configured in the power substrate 101 of fig. 2₁、P₂、P₃Any of the above) is used. Here, a case where 16 MOS transistors 108 are connected in series in one current path is exemplified. A plurality of (here, 16) MOS transistors 108 constituting one current path are mounted on different insulating substrates 106, and are configured to be non-conductive on the body side. The gate electrodes of the MOS transistors 108 are connected to different gate driver circuit elements GD, respectively.

Preferably, the resistor 111 is provided between the adjacent insulating substrates 106 in order to maintain the partial pressure of one insulating substrate 106. The material of the resistor 111 is, for example, carbon.

The heat dissipation member 110 is made of a material having high thermal conductivity (for example, copper, aluminum, an alloy material, or the like), and has at least one surface that is in direct contact with all the insulating substrates 106 constituting the power substrate 101. The insulating substrate 106 is in contact with the heat dissipation member 110 on the surface opposite to the surface on which the functional element is mounted. By bringing the insulating substrate 106 on which the functional element is mounted into contact with the heat dissipation member, heat generated in the functional element can be easily dissipated to the outside via the insulating substrate 106 and the heat dissipation member 110. Therefore, by reducing the damage to the functional element due to heat generation, a large current can be continuously passed.

The plurality of insulating substrates 106 are arranged on one surface of the heat dissipation member 110 so as to be separated from each other to form islands. Therefore, the MOS transistors 108 mounted on the adjacent insulating substrates 106 can be prevented from being short-circuited with each other, and the withstand voltage of each insulating substrate 106 can be improved.

The MOS transistors 108 mounted on the respective insulating substrates 106 are connected in series in a plurality of stages via a wiring (not shown) extending across the groove 106a formed between the adjacent insulating substrates 106. That is, each of the plurality of MOS transistors 108 mounted on the adjacent one of the insulating substrates 106 is connected in series with each of the plurality of MOS transistors 108 mounted on the other insulating substrate 106 one to one. In more detail, one source electrode or drain electrode of the two adjacent MOS transistors 108 is connected to the other drain electrode or source electrode, and the source electrodes and the drain electrodes are alternately arranged over the entire current path P.

The gate driver substrate 102 is a substrate on which a gate driver circuit element 112 of a plurality of MOS transistors 108 is mounted. The gate drive substrate 102 is disposed and connected to be stacked on the side on which the functional element is mounted on the surface of the power substrate 101.

The plurality of gate driver circuit elements 112 are electrically connected to each of the plurality of MOS transistors 108 on the insulating substrate 106 via a wiring 113 penetrating between the gate driver substrate 102 and the power substrate 101. That is, one gate driver circuit element 112 is configured to be able to apply a gate voltage to a plurality of (three in this case) MOS transistors 108 mounted on one conductive layer 107 via a wiring 113. From the viewpoint of reducing the influence of noise, the gate driver circuit element 112 is preferably disposed directly above the MOS transistor 108 to which the gate voltage is applied so as to shorten the wiring 113.

More preferably, the gate drive substrate 102 is disposed directly above the power substrate 101 and substantially parallel thereto. With this arrangement, the distance between the gate driver circuit element 112 and the MOS transistor 108 is the shortest and substantially uniform regardless of the positions, and the length of the wiring 113 is substantially uniform. Therefore, a problem such as noise when a voltage is applied to a part of the MOS transistors 108 can be avoided.

The power supply substrate 103 is formed by providing a plurality of coils 115 and 116 on both sides with an insulating member 114 interposed therebetween. The power supply board 103 is configured such that a voltage input to a coil (primary coil) 115 provided on one side with an insulating member 114 interposed therebetween is converted into a desired magnitude by magnetic field coupling, and a voltage is output from a coil (secondary coil) 116 provided on the other side.

Fig. 5 is a plan view of the power supply substrate 103 viewed from the primary coil 115 side. The secondary coil 116 is disposed at a position overlapping the primary coil 115 on the opposite side with the insulating member 114 interposed therebetween. In order to improve the efficiency of magnetic field coupling, the primary coil 115 and the secondary coil 116 are preferably arranged such that the central axes overlap each other.

The power supply substrate 103 is disposed so that the secondary coil 116 side faces the gate drive substrate 102, and is configured to apply an output voltage to the gate drive circuit element 112. More specifically, each of the plurality of secondary coils 116 is electrically connected to each of the plurality of gate drive circuit elements 112 via a wire 117 that penetrates between the power supply substrate 103 and the gate drive substrate 102. That is, one secondary coil 116 is configured to be able to apply a signal voltage to one gate driver circuit element 112 via a wire 117.

The control unit 104 includes: a CPLD (complex Programmable Logic Device) substrate 118 on which an EO converter for simultaneously transmitting an optical signal for on/off control to the plurality of gate driver circuit elements 112 is mounted; and an O/E substrate 119 provided with an OE converter that receives the optical signal and converts it into an electrical signal. The optical transmitter 120 on the CPLD substrate 118 and the optical receiver 121 on the O/E substrate 119 are connected via an optical fiber 122. The light-receiving unit 121 is electrically connected to the gate driver circuit element 112 via a wire 123 penetrating between the O/E substrate 119 and the gate driver substrate 102.

In the power substrate 101 of the present embodiment, the insulating substrate 106 on which the MOS transistor 108 is mounted is in contact with the heat dissipation member 110, and therefore, heat dissipation can be improved compared to a conventional MOS transistor mounted in a discrete state. In the high-voltage module 100 including the power substrate 101 according to the present embodiment, the plurality of gate driver circuit elements 112 are connected to one control unit 104, and the gate driver circuit elements 112 can be controlled simultaneously. Therefore, the gate signal can be simultaneously input to each of the plurality of MOS transistors 108 connected in series via the gate driver circuit element 112, and the gate delay variation between the MOS transistors 108 can be suppressed to be low.

[ description of symbols ]

100: a high voltage module; 101: a power substrate; 102: a gate driving substrate; 103: a power supply substrate; 104: a control unit; 105: a resin; 106: an insulating substrate; 106 a: a groove; 107: a conductive layer; 108: a MOS transistor; 109: a solder bonding layer; 110: a heat dissipating member; 111: a resistor body; 112: a gate drive circuit element; 113: wiring; 114: an insulating member; 115: a primary coil; 116: a secondary coil; 117: wiring; 118: a CPLD substrate; 119: an O/E substrate; 120: an optical transmission unit; 121: a light receiving section; 122: an optical fiber; 123: wiring; p, P1, P2, P3: a current path.